[240] | 1 | /* -*- c++ -*- |
---|
| 2 | * File : vci_io_bridge.h |
---|
| 3 | * Copyright (c) UPMC, Lip6, SoC |
---|
| 4 | * Date : 16/04/2012 |
---|
[434] | 5 | * Authors: Cassio Fraga, Alain Greiner |
---|
[240] | 6 | * |
---|
| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
[715] | 8 | * |
---|
[240] | 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
[715] | 10 | * |
---|
[240] | 11 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
| 12 | * under the terms of the GNU Lesser General Public License as published |
---|
| 13 | * by the Free Software Foundation; version 2.1 of the License. |
---|
[715] | 14 | * |
---|
[240] | 15 | * SoCLib is distributed in the hope that it will be useful, but |
---|
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 18 | * Lesser General Public License for more details. |
---|
[715] | 19 | * |
---|
[240] | 20 | * You should have received a copy of the GNU Lesser General Public |
---|
| 21 | * License along with SoCLib; if not, write to the Free Software |
---|
| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
| 23 | * 02110-1301 USA |
---|
[715] | 24 | * |
---|
[240] | 25 | * SOCLIB_LGPL_HEADER_END |
---|
| 26 | */ |
---|
[434] | 27 | ///////////////////////////////////////////////////////////////////////////////// |
---|
| 28 | // This TSAR component is a bridge to access external peripherals |
---|
| 29 | // connected to an external I/O bus (such as Hypertransport or PCIe). |
---|
| 30 | // It connects three VCI networks: |
---|
[585] | 31 | // |
---|
[434] | 32 | // - INT network : to receive both configuration requests from processors |
---|
| 33 | // or software driven data access to peripherals. |
---|
| 34 | // - RAM network : to send DMA transactions initiated by peripherals |
---|
| 35 | // directly to the RAM (or L3 caches). |
---|
| 36 | // - IOX network : to receive DMA transactions from peripherals, or to send |
---|
| 37 | // configuration or data transactions to peripherals. |
---|
[240] | 38 | // |
---|
[712] | 39 | // It supports two types of transactions from peripherals: |
---|
| 40 | // - DMA transactions to the RAM network, |
---|
| 41 | // - WTI transactions to the INT network. |
---|
| 42 | // Regarding transactions initiated by external peripherals, it provides |
---|
[434] | 43 | // an - optional - IOMMU service : the 32 bits virtual address is translated |
---|
| 44 | // to a (up to) 40 bits physical address by a standard SoCLib generic TLB. |
---|
[585] | 45 | // In case of TLB MISS, the DMA transaction is stalled until the TLB is updated. |
---|
[715] | 46 | // In case of page fault or read_only violation (illegal access), a VCI error |
---|
[712] | 47 | // is returned to the faulty peripheral, and a IOMMU WTI is sent. |
---|
[434] | 48 | ///////////////////////////////////////////////////////////////////////////////// |
---|
| 49 | // General Constraints: |
---|
[240] | 50 | // |
---|
[585] | 51 | // - All VCI fields have the same widths on the RAM and IOX networks, |
---|
| 52 | // and the VCI DATA field is 64 bits. |
---|
| 53 | // - Only the VCI DATA field differ between INT and IOX/RAM networks, |
---|
| 54 | // as the VCI DATA field is 32 bits. |
---|
[434] | 55 | // - The common VCI ADDRESS width cannot be larger than 64 bits. |
---|
| 56 | // - All VCI transactions must be included in a single cache line. |
---|
| 57 | // - Page Tables must have the format required by the SoCLib generic_tlb. |
---|
| 58 | // - IO's segments must be the same in INT and IOX networks |
---|
[585] | 59 | // - Write operations on IOMMU configuration registers (PTPR, ACTIVE) are |
---|
| 60 | // delayed until DMA_TLB FSM is IDLE. It should, preferably, be done before |
---|
[240] | 61 | // starting any transfers. Pseudo register INVAL may be modified any time. |
---|
| 62 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 63 | |
---|
[715] | 64 | |
---|
[240] | 65 | ///////TODO List/////////////////////////////////////////////////////////////// |
---|
[434] | 66 | // - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit |
---|
| 67 | // (seulement 'data' et 'be') |
---|
[240] | 68 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 69 | |
---|
| 70 | #ifndef SOCLIB_CABA_VCI_IO_BRIDGE_H |
---|
| 71 | #define SOCLIB_CABA_VCI_IO_BRIDGE_H |
---|
| 72 | |
---|
| 73 | #include <inttypes.h> |
---|
| 74 | #include <systemc> |
---|
| 75 | #include "caba_base_module.h" |
---|
| 76 | #include "generic_fifo.h" |
---|
| 77 | #include "generic_tlb.h" |
---|
| 78 | #include "mapping_table.h" |
---|
[715] | 79 | #include "address_decoding_table.h" |
---|
| 80 | #include "address_masking_table.h" |
---|
[240] | 81 | #include "static_assert.h" |
---|
| 82 | #include "vci_initiator.h" |
---|
| 83 | #include "vci_target.h" |
---|
[715] | 84 | #include "transaction_tab_io.h" |
---|
[434] | 85 | #include "../../../include/soclib/io_bridge.h" |
---|
[240] | 86 | |
---|
| 87 | namespace soclib { |
---|
| 88 | namespace caba { |
---|
| 89 | |
---|
| 90 | using namespace soclib::common; |
---|
| 91 | |
---|
[434] | 92 | /////////////////////////////////////////////////////////////////////////////////// |
---|
| 93 | template<typename vci_param_int, |
---|
| 94 | typename vci_param_ext> |
---|
[240] | 95 | class VciIoBridge |
---|
[434] | 96 | /////////////////////////////////////////////////////////////////////////////////// |
---|
[240] | 97 | : public soclib::caba::BaseModule |
---|
| 98 | { |
---|
[712] | 99 | // Data and be fields have different widths on INT and EXT/IOC networks |
---|
[585] | 100 | typedef typename vci_param_ext::data_t ext_data_t; |
---|
| 101 | typedef typename vci_param_int::data_t int_data_t; |
---|
| 102 | typedef typename vci_param_ext::be_t ext_be_t; |
---|
[712] | 103 | typedef typename vci_param_int::be_t int_be_t; |
---|
[240] | 104 | |
---|
[715] | 105 | // Other fields must be equal |
---|
| 106 | typedef typename vci_param_int::fast_addr_t vci_addr_t; |
---|
| 107 | typedef typename vci_param_int::srcid_t vci_srcid_t; |
---|
[434] | 108 | typedef typename vci_param_int::trdid_t vci_trdid_t; |
---|
| 109 | typedef typename vci_param_int::pktid_t vci_pktid_t; |
---|
| 110 | typedef typename vci_param_int::plen_t vci_plen_t; |
---|
| 111 | typedef typename vci_param_int::cmd_t vci_cmd_t; |
---|
| 112 | typedef typename vci_param_int::contig_t vci_contig_t; |
---|
| 113 | typedef typename vci_param_int::eop_t vci_eop_t; |
---|
| 114 | typedef typename vci_param_int::const_t vci_cons_t; |
---|
| 115 | typedef typename vci_param_int::wrap_t vci_wrap_t; |
---|
| 116 | typedef typename vci_param_int::clen_t vci_clen_t; |
---|
| 117 | typedef typename vci_param_int::cfixed_t vci_cfixed_t; |
---|
| 118 | typedef typename vci_param_int::rerror_t vci_rerror_t; |
---|
[240] | 119 | |
---|
[715] | 120 | enum |
---|
[434] | 121 | { |
---|
[715] | 122 | CACHE_LINE_MASK = 0xFFFFFFFFC0LL, |
---|
| 123 | PPN1_MASK = 0x0007FFFF, |
---|
| 124 | PPN2_MASK = 0x0FFFFFFF, |
---|
| 125 | K_PAGE_OFFSET_MASK = 0x00000FFF, |
---|
[240] | 126 | M_PAGE_OFFSET_MASK = 0x001FFFFF, |
---|
| 127 | PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14. |
---|
[715] | 128 | PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 |
---|
[240] | 129 | }; |
---|
[715] | 130 | |
---|
[434] | 131 | // States for DMA_CMD FSM (from IOX to RAM) |
---|
[715] | 132 | enum dma_cmd_fsm_state |
---|
| 133 | { |
---|
[240] | 134 | DMA_CMD_IDLE, |
---|
[712] | 135 | DMA_CMD_DMA_REQ, |
---|
| 136 | DMA_CMD_WTI_IOX_REQ, |
---|
| 137 | DMA_CMD_ERR_WAIT_EOP, |
---|
| 138 | DMA_CMD_ERR_WTI_REQ, |
---|
| 139 | DMA_CMD_ERR_RSP_REQ, |
---|
| 140 | DMA_CMD_TLB_MISS_WAIT, |
---|
[240] | 141 | }; |
---|
[715] | 142 | |
---|
| 143 | // States for DMA_RSP FSM |
---|
| 144 | enum dma_rsp_fsm_state |
---|
| 145 | { |
---|
[712] | 146 | DMA_RSP_IDLE_DMA, |
---|
| 147 | DMA_RSP_IDLE_WTI, |
---|
| 148 | DMA_RSP_IDLE_ERR, |
---|
| 149 | DMA_RSP_PUT_DMA, |
---|
| 150 | DMA_RSP_PUT_WTI, |
---|
| 151 | DMA_RSP_PUT_ERR, |
---|
[240] | 152 | }; |
---|
[715] | 153 | |
---|
[434] | 154 | // States for TLB_MISS FSM |
---|
[715] | 155 | enum dma_tlb_fsm_state |
---|
| 156 | { |
---|
[434] | 157 | TLB_IDLE, |
---|
| 158 | TLB_MISS, |
---|
| 159 | TLB_PTE1_GET, |
---|
| 160 | TLB_PTE1_SELECT, |
---|
| 161 | TLB_PTE1_UPDT, |
---|
[715] | 162 | TLB_PTE2_GET, |
---|
[434] | 163 | TLB_PTE2_SELECT, |
---|
| 164 | TLB_PTE2_UPDT, |
---|
| 165 | TLB_WAIT, |
---|
| 166 | TLB_RETURN, |
---|
| 167 | TLB_INVAL_CHECK, |
---|
[715] | 168 | }; |
---|
| 169 | |
---|
| 170 | // States for CONFIG_CMD FSM |
---|
| 171 | enum config_cmd_fsm_state |
---|
| 172 | { |
---|
[240] | 173 | CONFIG_CMD_IDLE, |
---|
[715] | 174 | CONFIG_CMD_WAIT, |
---|
| 175 | CONFIG_CMD_HI, |
---|
| 176 | CONFIG_CMD_LO, |
---|
[585] | 177 | CONFIG_CMD_PUT, |
---|
| 178 | CONFIG_CMD_RSP, |
---|
[715] | 179 | }; |
---|
| 180 | |
---|
| 181 | // states for CONFIG_RSP FSM |
---|
| 182 | enum config_rsp_fsm_state |
---|
| 183 | { |
---|
[712] | 184 | CONFIG_RSP_IDLE_IOX, |
---|
| 185 | CONFIG_RSP_IDLE_LOC, |
---|
[715] | 186 | CONFIG_RSP_PUT_LO, |
---|
[585] | 187 | CONFIG_RSP_PUT_HI, |
---|
| 188 | CONFIG_RSP_PUT_UNC, |
---|
[712] | 189 | CONFIG_RSP_PUT_LOC, |
---|
| 190 | |
---|
[240] | 191 | }; |
---|
[715] | 192 | |
---|
| 193 | // States for MISS_WTI_RSP FSM |
---|
| 194 | enum miss_wti_rsp_state |
---|
| 195 | { |
---|
[434] | 196 | MISS_WTI_RSP_IDLE, |
---|
[712] | 197 | MISS_WTI_RSP_WTI_IOX, |
---|
| 198 | MISS_WTI_RSP_WTI_MMU, |
---|
[434] | 199 | MISS_WTI_RSP_MISS, |
---|
[715] | 200 | }; |
---|
[240] | 201 | |
---|
[434] | 202 | // PKTID values for TLB MISS and WTI transactions |
---|
| 203 | enum pktid_values_e |
---|
| 204 | { |
---|
[712] | 205 | PKTID_MISS = 0x0, // TSAR code for read data uncached |
---|
| 206 | PKTID_WTI_IOX = 0x4, // TSAR code for write |
---|
| 207 | PKTID_WTI_MMU = 0xC, // TSAR code for write |
---|
[434] | 208 | }; |
---|
[715] | 209 | |
---|
[240] | 210 | // Miss types for iotlb |
---|
| 211 | enum tlb_miss_type_e |
---|
| 212 | { |
---|
[715] | 213 | PTE1_MISS, |
---|
[434] | 214 | PTE2_MISS, |
---|
[715] | 215 | }; |
---|
| 216 | |
---|
[240] | 217 | public: |
---|
[434] | 218 | sc_in<bool> p_clk; |
---|
| 219 | sc_in<bool> p_resetn; |
---|
[240] | 220 | |
---|
[715] | 221 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_ram; |
---|
| 222 | |
---|
[434] | 223 | soclib::caba::VciTarget<vci_param_ext> p_vci_tgt_iox; |
---|
| 224 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ini_iox; |
---|
| 225 | |
---|
| 226 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt_int; |
---|
| 227 | soclib::caba::VciInitiator<vci_param_int> p_vci_ini_int; |
---|
| 228 | |
---|
[240] | 229 | private: |
---|
[715] | 230 | const size_t m_words; |
---|
[240] | 231 | |
---|
[434] | 232 | // INT & IOX Networks |
---|
| 233 | std::list<soclib::common::Segment> m_int_seglist; |
---|
[715] | 234 | const vci_srcid_t m_int_srcid; // SRCID on INT network |
---|
[434] | 235 | std::list<soclib::common::Segment> m_iox_seglist; |
---|
[715] | 236 | const vci_srcid_t m_iox_srcid; // SRCID on IOX network |
---|
[240] | 237 | |
---|
[715] | 238 | // INT & RAM srcid masking table |
---|
| 239 | const AddressMaskingTable<uint32_t> m_srcid_gid_mask; |
---|
| 240 | const AddressMaskingTable<uint32_t> m_srcid_lid_mask; |
---|
| 241 | |
---|
[434] | 242 | // TLB parameters |
---|
[715] | 243 | const size_t m_iotlb_ways; |
---|
| 244 | const size_t m_iotlb_sets; |
---|
[240] | 245 | |
---|
[715] | 246 | // debug variables |
---|
[434] | 247 | uint32_t m_debug_start_cycle; |
---|
| 248 | bool m_debug_ok; |
---|
| 249 | bool m_debug_activated; |
---|
[240] | 250 | |
---|
| 251 | /////////////////////////////// |
---|
| 252 | // MEMORY MAPPED REGISTERS |
---|
| 253 | /////////////////////////////// |
---|
[712] | 254 | sc_signal<uint32_t> r_iommu_ptpr; // page table pointer |
---|
[434] | 255 | sc_signal<bool> r_iommu_active; // iotlb mode |
---|
[712] | 256 | sc_signal<uint32_t> r_iommu_bvar; // bad vaddr |
---|
| 257 | sc_signal<uint32_t> r_iommu_etr; // error type |
---|
[715] | 258 | sc_signal<uint32_t> r_iommu_bad_id; // faulty srcid |
---|
| 259 | sc_signal<bool> r_iommu_wti_enable; // enable IOB WTI |
---|
[712] | 260 | sc_signal<uint32_t> r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb) |
---|
| 261 | sc_signal<uint32_t> r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb) |
---|
| 262 | |
---|
[715] | 263 | /////////////////////////////////// |
---|
[240] | 264 | // DMA_CMD FSM REGISTERS |
---|
| 265 | /////////////////////////////////// |
---|
[715] | 266 | sc_signal<int> r_dma_cmd_fsm; |
---|
[712] | 267 | sc_signal<vci_addr_t> r_dma_cmd_paddr; // output paddr |
---|
[434] | 268 | |
---|
[712] | 269 | sc_signal<bool> r_dma_cmd_to_miss_wti_cmd_req; |
---|
| 270 | sc_signal<vci_addr_t> r_dma_cmd_to_miss_wti_cmd_addr; |
---|
| 271 | sc_signal<vci_cmd_t> r_dma_cmd_to_miss_wti_cmd_cmd; |
---|
| 272 | sc_signal<vci_srcid_t> r_dma_cmd_to_miss_wti_cmd_srcid; |
---|
| 273 | sc_signal<vci_trdid_t> r_dma_cmd_to_miss_wti_cmd_trdid; |
---|
| 274 | sc_signal<vci_trdid_t> r_dma_cmd_to_miss_wti_cmd_pktid; |
---|
| 275 | sc_signal<int_data_t> r_dma_cmd_to_miss_wti_cmd_wdata; |
---|
| 276 | |
---|
| 277 | sc_signal<bool> r_dma_cmd_to_dma_rsp_req; |
---|
| 278 | sc_signal<vci_srcid_t> r_dma_cmd_to_dma_rsp_rsrcid; |
---|
| 279 | sc_signal<vci_trdid_t> r_dma_cmd_to_dma_rsp_rtrdid; |
---|
| 280 | sc_signal<vci_pktid_t> r_dma_cmd_to_dma_rsp_rpktid; |
---|
| 281 | sc_signal<vci_rerror_t> r_dma_cmd_to_dma_rsp_rerror; |
---|
| 282 | sc_signal<ext_data_t> r_dma_cmd_to_dma_rsp_rdata; |
---|
[715] | 283 | |
---|
[712] | 284 | sc_signal<bool> r_dma_cmd_to_tlb_req; |
---|
[715] | 285 | sc_signal<uint32_t> r_dma_cmd_to_tlb_vaddr; // input vaddr |
---|
[712] | 286 | |
---|
[434] | 287 | /////////////////////////////////// |
---|
| 288 | // DMA_RSP FSM REGISTERS |
---|
| 289 | /////////////////////////////////// |
---|
| 290 | sc_signal<int> r_dma_rsp_fsm; |
---|
[715] | 291 | |
---|
[434] | 292 | /////////////////////////////////// |
---|
| 293 | // CONFIG_CMD FSM REGISTERS |
---|
| 294 | /////////////////////////////////// |
---|
| 295 | sc_signal<int> r_config_cmd_fsm; |
---|
[585] | 296 | |
---|
[712] | 297 | sc_signal<bool> r_config_cmd_to_tlb_req; |
---|
| 298 | sc_signal<uint32_t> r_config_cmd_to_tlb_vaddr; |
---|
| 299 | |
---|
| 300 | sc_signal<bool> r_config_cmd_to_config_rsp_req; |
---|
| 301 | sc_signal<bool> r_config_cmd_to_config_rsp_rerror; |
---|
[715] | 302 | sc_signal<int_data_t> r_config_cmd_to_config_rsp_rdata; |
---|
| 303 | sc_signal<vci_srcid_t> r_config_cmd_to_config_rsp_rsrcid; |
---|
| 304 | sc_signal<vci_trdid_t> r_config_cmd_to_config_rsp_rtrdid; |
---|
| 305 | sc_signal<vci_pktid_t> r_config_cmd_to_config_rsp_rpktid; |
---|
[712] | 306 | |
---|
[585] | 307 | sc_signal<ext_data_t> r_config_cmd_wdata; |
---|
| 308 | sc_signal<ext_be_t> r_config_cmd_be; |
---|
| 309 | sc_signal<vci_plen_t> r_config_cmd_cmd; |
---|
| 310 | sc_signal<vci_addr_t> r_config_cmd_address; |
---|
| 311 | sc_signal<vci_srcid_t> r_config_cmd_srcid; |
---|
[715] | 312 | sc_signal<vci_trdid_t> r_config_cmd_trdid; |
---|
[585] | 313 | sc_signal<vci_pktid_t> r_config_cmd_pktid; |
---|
| 314 | sc_signal<vci_plen_t> r_config_cmd_plen; |
---|
| 315 | sc_signal<vci_clen_t> r_config_cmd_clen; |
---|
| 316 | sc_signal<vci_cons_t> r_config_cmd_cons; |
---|
| 317 | sc_signal<vci_contig_t> r_config_cmd_contig; |
---|
| 318 | sc_signal<vci_cfixed_t> r_config_cmd_cfixed; |
---|
| 319 | sc_signal<vci_wrap_t> r_config_cmd_wrap; |
---|
| 320 | sc_signal<vci_eop_t> r_config_cmd_eop; |
---|
| 321 | |
---|
[715] | 322 | TransactionTabIO m_iox_transaction_tab; |
---|
| 323 | |
---|
[434] | 324 | /////////////////////////////////// |
---|
| 325 | // CONFIG_RSP FSM REGISTERS |
---|
| 326 | /////////////////////////////////// |
---|
| 327 | sc_signal<int> r_config_rsp_fsm; |
---|
[715] | 328 | sc_signal<vci_srcid_t> r_config_rsp_rsrcid; |
---|
| 329 | sc_signal<vci_trdid_t> r_config_rsp_rtrdid; |
---|
[434] | 330 | |
---|
| 331 | /////////////////////////////////// |
---|
| 332 | // TLB FSM REGISTERS |
---|
| 333 | /////////////////////////////////// |
---|
[715] | 334 | sc_signal<int> r_tlb_fsm; // state register |
---|
[712] | 335 | sc_signal<bool> r_waiting_transaction; // Flag for returning from |
---|
[434] | 336 | sc_signal<int> r_tlb_miss_type; |
---|
[715] | 337 | sc_signal<bool> r_tlb_miss_error; |
---|
[434] | 338 | |
---|
[715] | 339 | sc_signal<vci_addr_t> r_tlb_paddr; // physical address of pte |
---|
| 340 | sc_signal<uint32_t> r_tlb_pte_flags; // pte1 or first word of pte2 |
---|
| 341 | sc_signal<uint32_t> r_tlb_pte_ppn; // second word of pte2 |
---|
| 342 | sc_signal<size_t> r_tlb_way; // selected way in tlb |
---|
| 343 | sc_signal<size_t> r_tlb_set; // selected set in tlb |
---|
[434] | 344 | |
---|
[712] | 345 | uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs |
---|
| 346 | sc_signal<bool> r_tlb_buf_valid; // one valit flag for all PTEs |
---|
[715] | 347 | sc_signal<vci_addr_t> r_tlb_buf_tag; // cache line number |
---|
| 348 | sc_signal<vci_addr_t> r_tlb_buf_vaddr; // vaddr for first PTE |
---|
[712] | 349 | sc_signal<bool> r_tlb_buf_big_page; // ??? |
---|
[434] | 350 | |
---|
[712] | 351 | sc_signal<bool> r_tlb_to_miss_wti_cmd_req; |
---|
[434] | 352 | |
---|
| 353 | /////////////////////////////////// |
---|
| 354 | // MISS_WTI_RSP FSM REGISTERS |
---|
| 355 | /////////////////////////////////// |
---|
| 356 | sc_signal<int> r_miss_wti_rsp_fsm; |
---|
[712] | 357 | sc_signal<bool> r_miss_wti_rsp_error_wti; // VCI error on WTI |
---|
| 358 | sc_signal<bool> r_miss_wti_rsp_error_miss; // VCI error on MISS |
---|
| 359 | sc_signal<size_t> r_miss_wti_rsp_count; // flits counter |
---|
| 360 | |
---|
| 361 | sc_signal<bool> r_miss_wti_rsp_to_dma_rsp_req; |
---|
| 362 | sc_signal<vci_rerror_t> r_miss_wti_rsp_to_dma_rsp_rerror; |
---|
| 363 | sc_signal<vci_srcid_t> r_miss_wti_rsp_to_dma_rsp_rsrcid; |
---|
| 364 | sc_signal<vci_trdid_t> r_miss_wti_rsp_to_dma_rsp_rtrdid; |
---|
| 365 | sc_signal<vci_pktid_t> r_miss_wti_rsp_to_dma_rsp_rpktid; |
---|
| 366 | |
---|
[715] | 367 | |
---|
[434] | 368 | ///////////////////////////////////////////////////// |
---|
| 369 | // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo |
---|
| 370 | ///////////////////////////////////////////////////// |
---|
[715] | 371 | sc_signal<bool> r_alloc_fifo_config_rsp_local; |
---|
[434] | 372 | |
---|
[715] | 373 | |
---|
[434] | 374 | ////////////////////////////////////////////////////////////////// |
---|
[715] | 375 | // IOTLB |
---|
[434] | 376 | ////////////////////////////////////////////////////////////////// |
---|
| 377 | GenericTlb<vci_addr_t> r_iotlb; |
---|
[715] | 378 | |
---|
| 379 | |
---|
[434] | 380 | ///////////////////////// |
---|
| 381 | // FIFOs |
---|
| 382 | ///////////////////////// |
---|
| 383 | |
---|
| 384 | // ouput FIFO to VCI INI port on RAM network (VCI command) |
---|
| 385 | GenericFifo<vci_addr_t> m_dma_cmd_addr_fifo; |
---|
[240] | 386 | GenericFifo<vci_srcid_t> m_dma_cmd_srcid_fifo; |
---|
| 387 | GenericFifo<vci_trdid_t> m_dma_cmd_trdid_fifo; |
---|
| 388 | GenericFifo<vci_pktid_t> m_dma_cmd_pktid_fifo; |
---|
[585] | 389 | GenericFifo<ext_be_t> m_dma_cmd_be_fifo; |
---|
[240] | 390 | GenericFifo<vci_cmd_t> m_dma_cmd_cmd_fifo; |
---|
| 391 | GenericFifo<vci_contig_t> m_dma_cmd_contig_fifo; |
---|
[434] | 392 | GenericFifo<ext_data_t> m_dma_cmd_data_fifo; |
---|
[240] | 393 | GenericFifo<vci_eop_t> m_dma_cmd_eop_fifo; |
---|
| 394 | GenericFifo<vci_cons_t> m_dma_cmd_cons_fifo; |
---|
| 395 | GenericFifo<vci_plen_t> m_dma_cmd_plen_fifo; |
---|
| 396 | GenericFifo<vci_wrap_t> m_dma_cmd_wrap_fifo; |
---|
| 397 | GenericFifo<vci_cfixed_t> m_dma_cmd_cfixed_fifo; |
---|
| 398 | GenericFifo<vci_clen_t> m_dma_cmd_clen_fifo; |
---|
| 399 | |
---|
[434] | 400 | // output FIFO to VCI TGT port on IOX network (VCI response) |
---|
| 401 | GenericFifo<ext_data_t> m_dma_rsp_data_fifo; |
---|
[240] | 402 | GenericFifo<vci_srcid_t> m_dma_rsp_rsrcid_fifo; |
---|
| 403 | GenericFifo<vci_trdid_t> m_dma_rsp_rtrdid_fifo; |
---|
| 404 | GenericFifo<vci_pktid_t> m_dma_rsp_rpktid_fifo; |
---|
| 405 | GenericFifo<vci_eop_t> m_dma_rsp_reop_fifo; |
---|
| 406 | GenericFifo<vci_rerror_t> m_dma_rsp_rerror_fifo; |
---|
[715] | 407 | |
---|
[434] | 408 | // output FIFO to VCI INI port on IOX network (VCI command) |
---|
| 409 | GenericFifo<vci_addr_t> m_config_cmd_addr_fifo; |
---|
[240] | 410 | GenericFifo<vci_srcid_t> m_config_cmd_srcid_fifo; |
---|
| 411 | GenericFifo<vci_trdid_t> m_config_cmd_trdid_fifo; |
---|
| 412 | GenericFifo<vci_pktid_t> m_config_cmd_pktid_fifo; |
---|
[585] | 413 | GenericFifo<ext_be_t> m_config_cmd_be_fifo; |
---|
[240] | 414 | GenericFifo<vci_cmd_t> m_config_cmd_cmd_fifo; |
---|
| 415 | GenericFifo<vci_contig_t> m_config_cmd_contig_fifo; |
---|
[434] | 416 | GenericFifo<ext_data_t> m_config_cmd_data_fifo; |
---|
[240] | 417 | GenericFifo<vci_eop_t> m_config_cmd_eop_fifo; |
---|
| 418 | GenericFifo<vci_cons_t> m_config_cmd_cons_fifo; |
---|
| 419 | GenericFifo<vci_plen_t> m_config_cmd_plen_fifo; |
---|
| 420 | GenericFifo<vci_wrap_t> m_config_cmd_wrap_fifo; |
---|
| 421 | GenericFifo<vci_cfixed_t> m_config_cmd_cfixed_fifo; |
---|
| 422 | GenericFifo<vci_clen_t> m_config_cmd_clen_fifo; |
---|
[715] | 423 | |
---|
| 424 | // output FIFO to VCI TGT port on INT network (VCI response) |
---|
[434] | 425 | GenericFifo<int_data_t> m_config_rsp_data_fifo; |
---|
| 426 | GenericFifo<vci_srcid_t> m_config_rsp_rsrcid_fifo; |
---|
| 427 | GenericFifo<vci_trdid_t> m_config_rsp_rtrdid_fifo; |
---|
| 428 | GenericFifo<vci_pktid_t> m_config_rsp_rpktid_fifo; |
---|
| 429 | GenericFifo<vci_eop_t> m_config_rsp_reop_fifo; |
---|
| 430 | GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo; |
---|
[715] | 431 | |
---|
[712] | 432 | // output FIFO to VCI_INI port on INT network (VCI command) |
---|
| 433 | GenericFifo<vci_addr_t> m_miss_wti_cmd_addr_fifo; |
---|
| 434 | GenericFifo<vci_srcid_t> m_miss_wti_cmd_srcid_fifo; |
---|
| 435 | GenericFifo<vci_trdid_t> m_miss_wti_cmd_trdid_fifo; |
---|
| 436 | GenericFifo<vci_pktid_t> m_miss_wti_cmd_pktid_fifo; |
---|
| 437 | GenericFifo<int_be_t> m_miss_wti_cmd_be_fifo; |
---|
| 438 | GenericFifo<vci_cmd_t> m_miss_wti_cmd_cmd_fifo; |
---|
| 439 | GenericFifo<vci_contig_t> m_miss_wti_cmd_contig_fifo; |
---|
| 440 | GenericFifo<int_data_t> m_miss_wti_cmd_data_fifo; |
---|
| 441 | GenericFifo<vci_eop_t> m_miss_wti_cmd_eop_fifo; |
---|
| 442 | GenericFifo<vci_cons_t> m_miss_wti_cmd_cons_fifo; |
---|
| 443 | GenericFifo<vci_plen_t> m_miss_wti_cmd_plen_fifo; |
---|
| 444 | GenericFifo<vci_wrap_t> m_miss_wti_cmd_wrap_fifo; |
---|
| 445 | GenericFifo<vci_cfixed_t> m_miss_wti_cmd_cfixed_fifo; |
---|
| 446 | GenericFifo<vci_clen_t> m_miss_wti_cmd_clen_fifo; |
---|
[715] | 447 | |
---|
[240] | 448 | //////////////////////////////// |
---|
| 449 | // Activity counters |
---|
| 450 | //////////////////////////////// |
---|
[715] | 451 | |
---|
[240] | 452 | uint32_t m_cpt_total_cycles; // total number of cycles |
---|
[715] | 453 | |
---|
[240] | 454 | // TLB activity counters |
---|
| 455 | uint32_t m_cpt_iotlb_read; // number of iotlb read |
---|
| 456 | uint32_t m_cpt_iotlb_miss; // number of iotlb miss |
---|
[434] | 457 | uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) |
---|
[715] | 458 | uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions |
---|
[434] | 459 | uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions |
---|
[240] | 460 | |
---|
| 461 | //Transaction Tabs (TRTs) activity counters |
---|
| 462 | uint32_t m_cpt_trt_dma_full; // DMA TRT full when a new command arrives |
---|
| 463 | uint32_t m_cpt_trt_dma_full_cost; // total number of cycles blocked |
---|
| 464 | uint32_t m_cpt_trt_config_full; // Config TRT full when a new command arrives |
---|
| 465 | uint32_t m_cpt_trt_config_full_cost; // total number of cycles blocked |
---|
| 466 | |
---|
| 467 | // FSM activity counters |
---|
| 468 | // unused on print_stats |
---|
[715] | 469 | uint32_t m_cpt_fsm_dma_cmd [32]; |
---|
| 470 | uint32_t m_cpt_fsm_dma_rsp [32]; |
---|
| 471 | uint32_t m_cpt_fsm_tlb [32]; |
---|
| 472 | uint32_t m_cpt_fsm_config_cmd [32]; |
---|
| 473 | uint32_t m_cpt_fsm_config_rsp [32]; |
---|
[434] | 474 | uint32_t m_cpt_fsm_miss_wti_rsp [32]; |
---|
[715] | 475 | |
---|
[240] | 476 | protected: |
---|
[712] | 477 | |
---|
[240] | 478 | SC_HAS_PROCESS(VciIoBridge); |
---|
| 479 | |
---|
| 480 | public: |
---|
[712] | 481 | |
---|
[240] | 482 | VciIoBridge( |
---|
[715] | 483 | sc_module_name insname, |
---|
| 484 | const soclib::common::MappingTable &mt_ext, // external network |
---|
| 485 | const soclib::common::MappingTable &mt_int, // internal network |
---|
| 486 | const soclib::common::MappingTable &mt_iox, // iox network |
---|
| 487 | const soclib::common::IntTab &int_tgtid, // INT network TGTID |
---|
| 488 | const soclib::common::IntTab &int_srcid, // INT network SRCID |
---|
| 489 | const soclib::common::IntTab &iox_tgtid, // IOX network TGTID |
---|
| 490 | const soclib::common::IntTab &iox_srcid, // IOX network SRCID |
---|
| 491 | const size_t dcache_words, |
---|
| 492 | const size_t iotlb_ways, |
---|
| 493 | const size_t iotlb_sets, |
---|
| 494 | const uint32_t debug_start_cycle, |
---|
| 495 | const bool debug_ok ); |
---|
[240] | 496 | |
---|
| 497 | ~VciIoBridge(); |
---|
| 498 | |
---|
| 499 | void print_stats(); |
---|
| 500 | void clear_stats(); |
---|
| 501 | void print_trace(size_t mode = 0); |
---|
| 502 | |
---|
[715] | 503 | |
---|
[240] | 504 | private: |
---|
[712] | 505 | |
---|
| 506 | bool is_wti( vci_addr_t paddr ); |
---|
[240] | 507 | void transition(); |
---|
| 508 | void genMoore(); |
---|
| 509 | }; |
---|
| 510 | |
---|
| 511 | }} |
---|
| 512 | |
---|
| 513 | #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ |
---|
| 514 | |
---|
| 515 | // Local Variables: |
---|
| 516 | // tab-width: 4 |
---|
| 517 | // c-basic-offset: 4 |
---|
| 518 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 519 | // indent-tabs-mode: nil |
---|
| 520 | // End: |
---|
| 521 | |
---|
| 522 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 523 | |
---|
| 524 | |
---|
| 525 | |
---|
| 526 | |
---|