[434] | 1 | /* -*- c++ -*- |
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[240] | 2 | * File : vci_io_bridge.cpp |
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| 3 | * Copyright (c) UPMC, Lip6, SoC |
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[434] | 4 | * Authors: Cassio Fraga, Alain Greiner |
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[240] | 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | #include <cassert> |
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| 28 | #include "arithmetics.h" |
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| 29 | #include "alloc_elems.h" |
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| 30 | #include "../include/vci_io_bridge.h" |
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| 31 | |
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[434] | 32 | |
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[240] | 33 | ////// debug services /////////////////////////////////////////////////////// |
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| 34 | // All debug messages are conditionned by two variables: |
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| 35 | // - compile time : DEBUG_*** : defined below |
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| 36 | // - execution time : m_debug_*** : defined by constructor arguments |
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[434] | 37 | // m_debug_activated = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) |
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[240] | 38 | ///////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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| 40 | #define DEBUG_DMA_CMD 1 |
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| 41 | #define DEBUG_DMA_RSP 1 |
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[434] | 42 | #define DEBUG_TLB_MISS 1 |
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[240] | 43 | #define DEBUG_CONFIG_CMD 1 |
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| 44 | #define DEBUG_CONFIG_RSP 1 |
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[434] | 45 | #define DEBUG_MISS_WTI 1 |
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[240] | 46 | |
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| 47 | namespace soclib { |
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| 48 | namespace caba { |
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| 49 | |
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| 50 | namespace { |
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| 51 | |
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[434] | 52 | const char *dma_cmd_fsm_state_str[] = |
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| 53 | { |
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[240] | 54 | "DMA_CMD_IDLE", |
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[434] | 55 | "DMA_CMD_FIFO_PUT_CMD", |
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| 56 | "DMA_CMD_FIFO_PUT_RSP", |
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| 57 | "DMA_CMD_MISS_WAIT", |
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| 58 | "DMA_CMD_WAIT_EOP", |
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[240] | 59 | }; |
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| 60 | |
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[434] | 61 | const char *dma_rsp_fsm_state_str[] = |
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| 62 | { |
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[240] | 63 | "DMA_RSP_IDLE", |
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| 64 | "DMA_RSP_FIFO_PUT", |
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| 65 | }; |
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| 66 | |
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[434] | 67 | const char *tlb_fsm_state_str[] = |
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| 68 | { |
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| 69 | "TLB_IDLE", |
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| 70 | "TLB_MISS", |
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| 71 | "TLB_PTE1_GET", |
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| 72 | "TLB_PTE1_SELECT", |
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| 73 | "TLB_PTE1_UPDT", |
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| 74 | "TLB_PTE2_GET", |
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| 75 | "TLB_PTE2_SELECT", |
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| 76 | "TLB_PTE2_UPDT", |
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| 77 | "TLB_WAIT", |
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| 78 | "TLB_RETURN", |
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| 79 | "TLB_INVAL_CHECK", |
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[240] | 80 | }; |
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| 81 | |
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[434] | 82 | const char *config_cmd_fsm_state_str[] = |
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| 83 | { |
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[240] | 84 | "CONFIG_CMD_IDLE", |
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[434] | 85 | "CONFIG_CMD_FIFO_PUT_CMD", |
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| 86 | "CONFIG_CMD_FIFO_PUT_RSP", |
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[240] | 87 | }; |
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| 88 | |
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[434] | 89 | const char *config_rsp_fsm_state_str[] = |
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| 90 | { |
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[240] | 91 | "CONFIG_RSP_IDLE", |
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| 92 | "CONFIG_RSP_FIFO_PUT", |
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| 93 | }; |
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| 94 | |
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[549] | 95 | const char *miss_wti_cmd_state_str[] = |
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| 96 | { |
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| 97 | "MISS_WTI_CMD_IDLE", |
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[434] | 98 | "MISS_WTI_CMD_WTI", |
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[549] | 99 | "MISS_WTI_CMD_MISS", |
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| 100 | }; |
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| 101 | const char *miss_wti_rsp_state_str[] = |
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| 102 | { |
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| 103 | "MISS_WTI_RSP_IDLE", |
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[434] | 104 | "MISS_WTI_RSP_WTI", |
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| 105 | "MISS_WTI_RSP_MISS", |
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[240] | 106 | }; |
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| 107 | } |
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| 108 | |
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[434] | 109 | #define tmpl(...) template<typename vci_param_int,typename vci_param_ext> __VA_ARGS__ VciIoBridge<vci_param_int,vci_param_ext> |
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[240] | 110 | |
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[434] | 111 | //////////////////////// |
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[240] | 112 | tmpl(/**/)::VciIoBridge( |
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| 113 | sc_module_name name, |
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[434] | 114 | const soclib::common::MappingTable &mt_ext, |
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| 115 | const soclib::common::MappingTable &mt_int, |
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| 116 | const soclib::common::MappingTable &mt_iox, |
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| 117 | const soclib::common::IntTab &int_tgtid, // INT network TGTID |
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| 118 | const soclib::common::IntTab &int_srcid, // INT network SRCID |
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| 119 | const soclib::common::IntTab &iox_tgtid, // IOX network TGTID |
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| 120 | const bool has_irqs, |
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| 121 | const size_t dcache_words, |
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| 122 | const size_t iotlb_ways, |
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| 123 | const size_t iotlb_sets, |
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| 124 | const uint32_t debug_start_cycle, |
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| 125 | const bool debug_ok) |
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[240] | 126 | : soclib::caba::BaseModule(name), |
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| 127 | |
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[434] | 128 | p_clk("p_clk"), |
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| 129 | p_resetn("p_resetn"), |
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| 130 | p_vci_ini_ram("p_vci_ini_ram"), |
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| 131 | p_vci_tgt_iox("p_vci_tgt_iox"), |
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| 132 | p_vci_ini_iox("p_vci_ini_iox"), |
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| 133 | p_vci_tgt_int("p_vci_tgt_int"), |
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| 134 | p_vci_ini_int("p_vci_ini_int"), |
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[240] | 135 | |
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[434] | 136 | m_words( dcache_words ), |
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| 137 | m_has_irqs( has_irqs ), |
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[240] | 138 | |
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[434] | 139 | // INT & IOX Network |
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| 140 | m_int_seglist( mt_int.getSegmentList( int_tgtid )), |
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| 141 | m_int_srcid( mt_int.indexForId( int_srcid )), |
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| 142 | m_iox_seglist( mt_iox.getSegmentList( iox_tgtid )), |
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| 143 | |
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[240] | 144 | m_iotlb_ways(iotlb_ways), |
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| 145 | m_iotlb_sets(iotlb_sets), |
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| 146 | |
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| 147 | m_debug_start_cycle(debug_start_cycle), |
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| 148 | m_debug_ok(debug_ok), |
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| 149 | |
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[434] | 150 | // addressable registers |
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[240] | 151 | r_iommu_ptpr("r_iommu_ptpr"), |
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| 152 | r_iommu_active("r_iommu_active"), |
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| 153 | r_iommu_bvar("r_iommu_bvar"), |
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| 154 | r_iommu_etr("r_iommu_etr"), |
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| 155 | r_iommu_bad_id("r_iommu_bad_id"), |
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[434] | 156 | r_iommu_wti_paddr("r_iommu_wti_paddr"), |
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| 157 | r_iommu_peri_wti(alloc_elems<sc_signal<vci_addr_t> >("r_peri_wti_paddr", 32)), |
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[240] | 158 | |
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[434] | 159 | // DMA_CMD FSM registers |
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[240] | 160 | r_dma_cmd_fsm("r_dma_cmd_fsm"), |
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[434] | 161 | r_dma_cmd_vaddr("r_dma_cmd_vaddr"), |
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| 162 | r_dma_cmd_paddr("r_dma_cmd_paddr"), |
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[240] | 163 | |
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[434] | 164 | //DMA_RSP FSM registers |
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| 165 | r_dma_rsp_fsm("r_dma_rsp_fsm"), |
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[240] | 166 | |
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[434] | 167 | // CONFIG_CMD FSM registers |
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| 168 | r_config_cmd_fsm("r_config_cmd_fsm"), |
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| 169 | r_config_cmd_rdata("r_config_cmd_rdata"), |
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| 170 | r_config_cmd_error("r_config_cmd_error"), |
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| 171 | r_config_cmd_inval_vaddr("r_config_cmd_inval_vaddr"), |
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[240] | 172 | |
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[434] | 173 | // CONFIG_RSP FSM registers |
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| 174 | r_config_rsp_fsm("r_config_rsp_fsm"), |
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| 175 | |
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| 176 | // TLB FSM registers |
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| 177 | r_tlb_fsm("r_tlb_fsm"), |
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[240] | 178 | r_waiting_transaction("r_waiting_transaction"), |
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| 179 | r_tlb_miss_type("r_tlb_miss_type"), |
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[434] | 180 | r_tlb_miss_error("r_tlb_miss_error"), |
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| 181 | r_tlb_paddr("r_tlb_paddr"), |
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| 182 | r_tlb_pte_flags("r_tlb_pte_flags"), |
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| 183 | r_tlb_pte_ppn("r_tlb_pte_ppn"), |
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| 184 | r_tlb_way("r_tlb_way"), |
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| 185 | r_tlb_set("r_tlb_set"), |
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| 186 | r_tlb_buf_valid("r_tlb_buf_valid"), |
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| 187 | r_tlb_buf_tag("r_tlb_buf_tag"), |
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| 188 | r_tlb_buf_vaddr("r_tlb_buf_vaddr"), |
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| 189 | r_tlb_buf_big_page("r_tlb_buf_big_page"), |
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[240] | 190 | |
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[434] | 191 | // MISS_WTI_CMD FSM registers |
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| 192 | r_miss_wti_cmd_fsm("r_miss_wti_cmd_fsm"), |
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| 193 | r_miss_wti_cmd_index("r_miss_wti_cmd_index"), |
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[240] | 194 | |
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[434] | 195 | // MISS_WTI_CMD FSM registers |
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| 196 | r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), |
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| 197 | r_miss_wti_rsp_error("r_miss_wti_rsp_error"), |
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| 198 | |
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| 199 | // allocator for CONFIG_RSP & DMA_RSP fifos |
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| 200 | r_alloc_fifo_config_rsp_local("r_alloc_fifo_config_rsp_local"), |
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| 201 | r_alloc_fifo_dma_rsp_local("r_alloc_fifo_dma_rsp_local"), |
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| 202 | |
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| 203 | // IRQs registers |
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| 204 | r_irq_pending(alloc_elems<sc_signal<bool> >("r_irq_pending", 32)), |
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| 205 | r_irq_request(alloc_elems<sc_signal<bool> >("r_irq_request", 32)), |
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[240] | 206 | |
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[434] | 207 | // TLB for IOMMU |
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| 208 | r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), |
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| 209 | |
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| 210 | // Inter-FSM communications |
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[240] | 211 | r_dma_tlb_req("r_dma_tlb_req"), |
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| 212 | r_config_tlb_req("r_config_tlb_req"), |
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[434] | 213 | r_tlb_miss_req("r_tlb_miss_req"), |
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[240] | 214 | |
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[434] | 215 | // DMA_CMD FIFOs |
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| 216 | m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), |
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| 217 | m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), |
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| 218 | m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), |
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| 219 | m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), |
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| 220 | m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), |
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| 221 | m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), |
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| 222 | m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), |
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| 223 | m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), |
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| 224 | m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",2), |
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| 225 | m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), |
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| 226 | m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), |
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| 227 | m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), |
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| 228 | m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",2), |
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| 229 | m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), |
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[240] | 230 | |
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[434] | 231 | // DMA_RSP FIFOs |
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| 232 | m_dma_rsp_data_fifo("m_dma_rsp_data_fifo",2), |
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| 233 | m_dma_rsp_rsrcid_fifo("m_dma_rsp_rsrcid_fifo",2), |
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| 234 | m_dma_rsp_rtrdid_fifo("m_dma_rsp_rtrdid_fifo",2), |
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| 235 | m_dma_rsp_rpktid_fifo("m_dma_rsp_rpktid_fifo",2), |
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| 236 | m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",2), |
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| 237 | m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",2), |
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| 238 | |
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| 239 | // CONFIG_CMD FIFOs |
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| 240 | m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",2), |
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| 241 | m_config_cmd_srcid_fifo("m_config_cmd_srcid_fifo",2), |
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| 242 | m_config_cmd_trdid_fifo("m_config_cmd_trdid_fifo",2), |
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| 243 | m_config_cmd_pktid_fifo("m_config_cmd_pktid_fifo",2), |
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| 244 | m_config_cmd_be_fifo("m_config_cmd_be_fifo",2), |
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| 245 | m_config_cmd_cmd_fifo("m_config_cmd_cmd_fifo",2), |
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| 246 | m_config_cmd_contig_fifo("m_config_cmd_contig_fifo",2), |
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| 247 | m_config_cmd_data_fifo("m_config_cmd_data_fifo",2), |
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| 248 | m_config_cmd_eop_fifo("m_config_cmd_eop_fifo",2), |
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| 249 | m_config_cmd_cons_fifo("m_config_cmd_cons_fifo",2), |
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| 250 | m_config_cmd_plen_fifo("m_config_cmd_plen_fifo",2), |
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| 251 | m_config_cmd_wrap_fifo("m_config_cmd_wrap_fifo",2), |
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| 252 | m_config_cmd_cfixed_fifo("m_config_cmd_cfixed_fifo",2), |
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| 253 | m_config_cmd_clen_fifo("m_config_cmd_clen_fifo",2), |
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| 254 | |
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| 255 | // CONFIG_RSP FIFOs |
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| 256 | m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), |
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| 257 | m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",2), |
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| 258 | m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",2), |
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| 259 | m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",2), |
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| 260 | m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",2), |
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| 261 | m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",2) |
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[240] | 262 | { |
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[434] | 263 | std::cout << " - Building VciIoBridge : " << name << std::endl; |
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| 264 | |
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| 265 | // checking segments on INT network |
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| 266 | assert ( ( not m_int_seglist.empty() ) and |
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| 267 | "VCI_IO_BRIDGE ERROR : no segment allocated on INT network"); |
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| 268 | |
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| 269 | std::list<soclib::common::Segment>::iterator int_seg; |
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| 270 | for ( int_seg = m_int_seglist.begin() ; int_seg != m_int_seglist.end() ; int_seg++ ) |
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| 271 | { |
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| 272 | std::cout << " => segment " << int_seg->name() |
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| 273 | << " / base = " << std::hex << int_seg->baseAddress() |
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[549] | 274 | << " / size = " << int_seg->size() |
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| 275 | << " / special = " << int_seg->special() << std::endl; |
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[434] | 276 | } |
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| 277 | |
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| 278 | // checking segments on IOX network |
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| 279 | assert ( ( not m_iox_seglist.empty() ) and |
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| 280 | "VCI_IO_BRIDGE ERROR : no segment allocated on IOX network"); |
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| 281 | |
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| 282 | std::list<soclib::common::Segment>::iterator iox_seg; |
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| 283 | for ( iox_seg = m_iox_seglist.begin() ; iox_seg != m_iox_seglist.end() ; iox_seg++ ) |
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| 284 | { |
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| 285 | std::cout << " => segment " << iox_seg->name() |
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| 286 | << " / base = " << std::hex << iox_seg->baseAddress() |
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| 287 | << " / size = " << iox_seg->size() << std::endl; |
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| 288 | } |
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| 289 | |
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| 290 | assert( (vci_param_int::N == vci_param_ext::N) and |
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| 291 | "VCI_IO_BRIDGE ERROR: VCI ADDRESS widths must be equal on the 3 networks"); |
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| 292 | |
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| 293 | assert( (vci_param_int::N <= 64) and |
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| 294 | "VCI_IO_BRIDGE ERROR: VCI ADDRESS width cannot be bigger than 64 bits"); |
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| 295 | |
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| 296 | assert( ((vci_param_int::B == 4) or (vci_param_int::B == 8)) and |
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| 297 | "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or 64 bits on internal network"); |
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| 298 | |
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| 299 | assert( ((vci_param_ext::B == 4) or (vci_param_ext::B == 8)) and |
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| 300 | "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or 64 bits on external network"); |
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| 301 | |
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| 302 | assert( (vci_param_int::S == vci_param_ext::S) and |
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| 303 | "VCI_IO_BRIDGE ERROR: SRCID widths must be equal on the 3 networks"); |
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| 304 | |
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| 305 | // contruct 32 IRQ ports if required |
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| 306 | if ( has_irqs ) |
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| 307 | { |
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| 308 | for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_core::sc_in<bool>; |
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| 309 | } |
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[240] | 310 | |
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[434] | 311 | // Cache line buffer |
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| 312 | r_tlb_buf_data = new uint32_t[dcache_words]; |
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| 313 | |
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[240] | 314 | SC_METHOD(transition); |
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| 315 | dont_initialize(); |
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| 316 | sensitive << p_clk.pos(); |
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| 317 | |
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| 318 | SC_METHOD(genMoore); |
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| 319 | dont_initialize(); |
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| 320 | sensitive << p_clk.neg(); |
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| 321 | |
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| 322 | } |
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| 323 | |
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| 324 | ///////////////////////////////////// |
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| 325 | tmpl(/**/)::~VciIoBridge() |
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| 326 | ///////////////////////////////////// |
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| 327 | { |
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[434] | 328 | delete [] r_iommu_peri_wti; |
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| 329 | delete [] r_tlb_buf_data; |
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| 330 | soclib::common::dealloc_elems(p_irq, 32); |
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| 331 | soclib::common::dealloc_elems(r_irq_request, 32); |
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| 332 | soclib::common::dealloc_elems(r_irq_pending, 32); |
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[240] | 333 | } |
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| 334 | |
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| 335 | //////////////////////////////////// |
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| 336 | tmpl(void)::print_trace(size_t mode) |
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| 337 | //////////////////////////////////// |
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| 338 | { |
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[549] | 339 | // b0 : IOTLB trace |
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[240] | 340 | |
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| 341 | std::cout << std::dec << "IO_BRIDGE " << name() << std::endl; |
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| 342 | |
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[434] | 343 | std::cout << " " << dma_cmd_fsm_state_str[r_dma_cmd_fsm.read()] |
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[240] | 344 | << " | " << dma_rsp_fsm_state_str[r_dma_rsp_fsm.read()] |
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[434] | 345 | << " | " << tlb_fsm_state_str[r_tlb_fsm.read()] |
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[240] | 346 | << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] |
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| 347 | << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()] |
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[549] | 348 | << " | " << miss_wti_cmd_state_str[r_miss_wti_cmd_fsm.read()] |
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| 349 | << " | " << miss_wti_rsp_state_str[r_miss_wti_rsp_fsm.read()] |
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[434] | 350 | << std::endl; |
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[240] | 351 | |
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| 352 | if(mode & 0x01) |
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| 353 | { |
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| 354 | std::cout << " IOTLB" << std::endl; |
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| 355 | r_iotlb.printTrace(); |
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| 356 | } |
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| 357 | } |
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| 358 | |
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| 359 | //////////////////////// |
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| 360 | tmpl(void)::print_stats() |
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| 361 | //////////////////////// |
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| 362 | { |
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| 363 | std::cout << name() << std::endl |
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| 364 | << "- IOTLB MISS RATE = " << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read << std::endl |
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| 365 | << "- IOTLB MISS COST = " << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss << std::endl |
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| 366 | << "- IOTLB MISS TRANSACTION COST = " << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction << std::endl |
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| 367 | << "- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss << std::endl; |
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| 368 | } |
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| 369 | |
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| 370 | //////////////////////// |
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| 371 | tmpl(void)::clear_stats() |
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| 372 | //////////////////////// |
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| 373 | { |
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| 374 | m_cpt_iotlb_read = 0; |
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| 375 | m_cpt_iotlb_miss = 0; |
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| 376 | m_cost_iotlb_miss = 0; |
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| 377 | m_cpt_iotlbmiss_transaction = 0; |
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| 378 | m_cost_iotlbmiss_transaction = 0; |
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| 379 | } |
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| 380 | |
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| 381 | ///////////////////////// |
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| 382 | tmpl(void)::transition() |
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| 383 | ///////////////////////// |
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| 384 | { |
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| 385 | if ( not p_resetn.read() ) |
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| 386 | { |
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[434] | 387 | r_dma_cmd_fsm = DMA_CMD_IDLE; |
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| 388 | r_dma_rsp_fsm = DMA_RSP_IDLE; |
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| 389 | r_tlb_fsm = TLB_IDLE; |
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| 390 | r_config_cmd_fsm = CONFIG_CMD_IDLE; |
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| 391 | r_config_rsp_fsm = CONFIG_RSP_IDLE; |
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| 392 | r_miss_wti_cmd_fsm = MISS_WTI_CMD_IDLE; |
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| 393 | r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; |
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[240] | 394 | |
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[434] | 395 | r_alloc_fifo_config_rsp_local = true; |
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| 396 | r_alloc_fifo_dma_rsp_local = true; |
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[240] | 397 | |
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[434] | 398 | r_tlb_buf_valid = false; |
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| 399 | r_iommu_active = false; |
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| 400 | r_iommu_wti_enable = false; |
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[240] | 401 | |
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| 402 | // initializing FIFOs |
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| 403 | m_dma_cmd_addr_fifo.init(); |
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| 404 | m_dma_cmd_srcid_fifo.init(); |
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| 405 | m_dma_cmd_trdid_fifo.init(); |
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| 406 | m_dma_cmd_pktid_fifo.init(); |
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| 407 | m_dma_cmd_be_fifo.init(); |
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| 408 | m_dma_cmd_cmd_fifo.init(); |
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| 409 | m_dma_cmd_contig_fifo.init(); |
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| 410 | m_dma_cmd_data_fifo.init(); |
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| 411 | m_dma_cmd_eop_fifo.init(); |
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| 412 | m_dma_cmd_cons_fifo.init(); |
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| 413 | m_dma_cmd_plen_fifo.init(); |
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| 414 | m_dma_cmd_wrap_fifo.init(); |
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| 415 | m_dma_cmd_cfixed_fifo.init(); |
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| 416 | m_dma_cmd_clen_fifo.init(); |
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| 417 | |
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| 418 | m_dma_rsp_rsrcid_fifo.init(); |
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| 419 | m_dma_rsp_rtrdid_fifo.init(); |
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| 420 | m_dma_rsp_rpktid_fifo.init(); |
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| 421 | m_dma_rsp_data_fifo.init(); |
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| 422 | m_dma_rsp_rerror_fifo.init(); |
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| 423 | m_dma_rsp_reop_fifo.init(); |
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| 424 | |
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| 425 | m_config_cmd_addr_fifo.init(); |
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| 426 | m_config_cmd_srcid_fifo.init(); |
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| 427 | m_config_cmd_trdid_fifo.init(); |
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| 428 | m_config_cmd_pktid_fifo.init(); |
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| 429 | m_config_cmd_be_fifo.init(); |
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| 430 | m_config_cmd_cmd_fifo.init(); |
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| 431 | m_config_cmd_contig_fifo.init(); |
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| 432 | m_config_cmd_data_fifo.init(); |
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| 433 | m_config_cmd_eop_fifo.init(); |
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| 434 | m_config_cmd_cons_fifo.init(); |
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| 435 | m_config_cmd_plen_fifo.init(); |
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| 436 | m_config_cmd_wrap_fifo.init(); |
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| 437 | m_config_cmd_cfixed_fifo.init(); |
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| 438 | m_config_cmd_clen_fifo.init(); |
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| 439 | |
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| 440 | m_config_rsp_rsrcid_fifo.init(); |
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| 441 | m_config_rsp_rtrdid_fifo.init(); |
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| 442 | m_config_rsp_rpktid_fifo.init(); |
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| 443 | m_config_rsp_data_fifo.init(); |
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| 444 | m_config_rsp_rerror_fifo.init(); |
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| 445 | m_config_rsp_reop_fifo.init(); |
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| 446 | |
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[434] | 447 | // SET/RESET Communication flip-flops |
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| 448 | r_dma_tlb_req = false; |
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| 449 | r_config_tlb_req = false; |
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| 450 | r_tlb_miss_req = false; |
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[240] | 451 | |
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[434] | 452 | // Debug variable |
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| 453 | m_debug_activated = false; |
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[240] | 454 | |
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[434] | 455 | for ( size_t n=0 ; n<32 ; n++ ) |
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| 456 | { |
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| 457 | r_irq_pending[n] = false; |
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| 458 | r_irq_request[n] = false; |
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| 459 | } |
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[240] | 460 | |
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| 461 | // activity counters |
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[434] | 462 | m_cpt_total_cycles = 0; |
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| 463 | m_cpt_iotlb_read = 0; |
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| 464 | m_cpt_iotlb_miss = 0; |
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| 465 | m_cpt_iotlbmiss_transaction = 0; |
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| 466 | m_cost_iotlbmiss_transaction = 0; |
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[240] | 467 | |
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[434] | 468 | m_cpt_trt_dma_full = 0; |
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| 469 | m_cpt_trt_dma_full_cost = 0; |
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| 470 | m_cpt_trt_config_full = 0; |
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| 471 | m_cpt_trt_config_full_cost = 0; |
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[240] | 472 | |
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| 473 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_cmd [i] = 0; |
---|
| 474 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_rsp [i] = 0; |
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[434] | 475 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tlb [i] = 0; |
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[240] | 476 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_cmd [i] = 0; |
---|
| 477 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_rsp [i] = 0; |
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[434] | 478 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_cmd [i] = 0; |
---|
| 479 | for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_rsp [i] = 0; |
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| 480 | |
---|
[240] | 481 | return; |
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| 482 | } |
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| 483 | |
---|
[434] | 484 | // default values for FIFOs |
---|
| 485 | bool dma_cmd_fifo_put = false; |
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| 486 | bool dma_cmd_fifo_get = false; |
---|
| 487 | |
---|
| 488 | bool dma_rsp_fifo_put = false; |
---|
| 489 | bool dma_rsp_fifo_get = false; |
---|
[240] | 490 | |
---|
[434] | 491 | bool config_cmd_fifo_put = false; |
---|
| 492 | bool config_cmd_fifo_get = false; |
---|
[240] | 493 | |
---|
[434] | 494 | bool config_rsp_fifo_put = false; |
---|
| 495 | bool config_rsp_fifo_get = false; |
---|
| 496 | |
---|
[240] | 497 | #ifdef INSTRUMENTATION |
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| 498 | m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; |
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| 499 | m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; |
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[434] | 500 | m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; |
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[240] | 501 | m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; |
---|
| 502 | m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; |
---|
[434] | 503 | m_cpt_fsm_miss_wti_cmd [r_miss_wti_cmd_fsm.read() ] ++; |
---|
| 504 | m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; |
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[240] | 505 | #endif |
---|
| 506 | |
---|
| 507 | m_cpt_total_cycles++; |
---|
| 508 | |
---|
[434] | 509 | m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; |
---|
[240] | 510 | |
---|
[434] | 511 | ////////////////////////////////////////////////////////////////////////////// |
---|
| 512 | // The DMA_CMD_FSM handles DMA transactions requested by peripherals |
---|
| 513 | // It makes the address translation if IOMMU is activated. |
---|
[240] | 514 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 515 | |
---|
| 516 | switch( r_dma_cmd_fsm.read() ) |
---|
| 517 | { |
---|
[434] | 518 | ////////////////// |
---|
| 519 | case DMA_CMD_IDLE: // waiting DMA VCI transaction |
---|
[240] | 520 | { |
---|
[434] | 521 | if ( p_vci_tgt_iox.cmdval.read() ) // compute physical address |
---|
[240] | 522 | { |
---|
[434] | 523 | if ( not r_iommu_active.read() ) // tlb not activated |
---|
[240] | 524 | { |
---|
[434] | 525 | #if DEBUG_DMA_CMD |
---|
| 526 | if( m_debug_activated ) |
---|
| 527 | std::cout << " <IOB DMA_CMD_IDLE> IOMMU not activated" << std::endl; |
---|
| 528 | #endif |
---|
| 529 | // put DMA transaction into DMA_CMD fifo |
---|
| 530 | r_dma_cmd_paddr = p_vci_tgt_iox.address.read(); |
---|
| 531 | r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; |
---|
[240] | 532 | } |
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[434] | 533 | else if (r_tlb_fsm.read() == TLB_IDLE || |
---|
| 534 | r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible |
---|
[240] | 535 | { |
---|
[434] | 536 | vci_addr_t iotlb_paddr; |
---|
[240] | 537 | pte_info_t iotlb_flags; |
---|
| 538 | size_t iotlb_way; |
---|
| 539 | size_t iotlb_set; |
---|
[434] | 540 | vci_addr_t iotlb_nline; |
---|
| 541 | bool iotlb_hit; |
---|
[240] | 542 | |
---|
| 543 | #ifdef INSTRUMENTATION |
---|
| 544 | m_cpt_iotlb_read++; |
---|
| 545 | #endif |
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[434] | 546 | iotlb_hit = r_iotlb.translate(p_vci_tgt_iox.address.read(), |
---|
| 547 | &iotlb_paddr, |
---|
| 548 | &iotlb_flags, |
---|
| 549 | &iotlb_nline, // unused |
---|
| 550 | &iotlb_way, // unused |
---|
| 551 | &iotlb_set ); // unused |
---|
[240] | 552 | |
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[434] | 553 | if ( iotlb_hit ) // tlb hit |
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[240] | 554 | { |
---|
[434] | 555 | if ( not iotlb_flags.w and // access right violation |
---|
| 556 | (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) |
---|
[240] | 557 | { |
---|
[434] | 558 | // put DMA response error into DMA_RSP fifo |
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| 559 | r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; |
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| 560 | r_iommu_bvar = p_vci_tgt_iox.address.read(); |
---|
| 561 | r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); |
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| 562 | r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; |
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[240] | 563 | #if DEBUG_DMA_CMD |
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[434] | 564 | if( m_debug_activated ) |
---|
| 565 | std::cout << " <IOB DMA_CMD_IDLE> TLB HIT but writable violation" << std::endl; |
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[240] | 566 | #endif |
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| 567 | } |
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[434] | 568 | else // no access rights violation |
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| 569 | { |
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| 570 | #if DEBUG_DMA_CMD |
---|
| 571 | if( m_debug_activated ) |
---|
| 572 | std::cout << " <IOB DMA_CMD_IDLE> TLB HIT" << std::endl; |
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| 573 | #endif |
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| 574 | // put DMA transaction into DMA_CMD fifo |
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| 575 | r_dma_cmd_paddr = iotlb_paddr; |
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| 576 | r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; |
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| 577 | } |
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[240] | 578 | } |
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[434] | 579 | else // TLB miss |
---|
[240] | 580 | { |
---|
| 581 | |
---|
| 582 | #ifdef INSTRUMENTATION |
---|
| 583 | m_cpt_iotlb_miss++; |
---|
| 584 | #endif |
---|
[434] | 585 | // register virtual address, and send request to TLB FSM |
---|
| 586 | r_dma_cmd_vaddr = p_vci_tgt_iox.address.read(); |
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[240] | 587 | r_dma_tlb_req = true; |
---|
[434] | 588 | r_dma_cmd_fsm = DMA_CMD_MISS_WAIT; |
---|
[240] | 589 | #if DEBUG_DMA_CMD |
---|
[434] | 590 | if( m_debug_activated ) |
---|
| 591 | std::cout << " <IOB DMA_CMD_IDLE> TLB MISS" << std::endl; |
---|
[240] | 592 | #endif |
---|
| 593 | } // end !hit |
---|
| 594 | } // end if tlb_activated |
---|
| 595 | } // end if cmdval |
---|
| 596 | break; |
---|
| 597 | } |
---|
[434] | 598 | ////////////////////////// |
---|
| 599 | case DMA_CMD_FIFO_PUT_CMD: // put a DMA transaction in DMA_CMD fifo |
---|
| 600 | // if contig, VCI address must be incremented |
---|
[240] | 601 | { |
---|
[434] | 602 | if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) |
---|
[240] | 603 | { |
---|
[434] | 604 | dma_cmd_fifo_put = true; |
---|
| 605 | |
---|
| 606 | if ( p_vci_tgt_iox.contig.read() ) r_dma_cmd_paddr = r_dma_cmd_paddr.read() + |
---|
| 607 | vci_param_ext::B; |
---|
[240] | 608 | |
---|
[434] | 609 | if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_IDLE; |
---|
| 610 | |
---|
[240] | 611 | #if DEBUG_DMA_CMD |
---|
[434] | 612 | if( m_debug_activated ) |
---|
| 613 | std::cout << " <IOB DMA_CMD_FIFO_PUT_CMD> Push into DMA_CMD fifo:" |
---|
| 614 | << " address = " << std::hex << r_dma_cmd_paddr.read() |
---|
| 615 | << " srcid = " << p_vci_tgt_iox.srcid.read() |
---|
| 616 | << " trdid = " << p_vci_tgt_iox.trdid.read() |
---|
| 617 | << " wdata = " << p_vci_tgt_iox.wdata.read() |
---|
| 618 | << " be = " << p_vci_tgt_iox.be.read() |
---|
| 619 | << " contig = " << p_vci_tgt_iox.contig.read() |
---|
| 620 | << " eop = " << std::dec << p_vci_tgt_iox.eop.read() |
---|
| 621 | << " plen = " << std::dec << p_vci_tgt_iox.plen.read() << std::endl; |
---|
[240] | 622 | #endif |
---|
| 623 | } |
---|
| 624 | break; |
---|
| 625 | } |
---|
[434] | 626 | ////////////////////// |
---|
| 627 | case DMA_CMD_WAIT_EOP: // An error has been detected on the VCI DMA command |
---|
| 628 | // consume the VCI packet before sending the error response |
---|
[240] | 629 | { |
---|
[434] | 630 | if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; |
---|
[240] | 631 | break; |
---|
| 632 | } |
---|
[434] | 633 | ////////////////////////// |
---|
| 634 | case DMA_CMD_FIFO_PUT_RSP: // try to put a response error in DMA_RSP fifo |
---|
| 635 | // The FIFO is shared with DMA_RSP FSM |
---|
| 636 | // and we must we wait for allocation... |
---|
[240] | 637 | { |
---|
[434] | 638 | if ( r_alloc_fifo_dma_rsp_local.read() ) |
---|
[240] | 639 | { |
---|
[434] | 640 | dma_rsp_fifo_put = true; |
---|
| 641 | |
---|
| 642 | if( m_dma_rsp_data_fifo.wok() ) |
---|
[240] | 643 | { |
---|
| 644 | |
---|
| 645 | #if DEBUG_DMA_CMD |
---|
[434] | 646 | if( m_debug_activated ) |
---|
| 647 | std::cout << " <IOB DMA_CMD_FIFO_PUT_RSP> Put a response error to a DMA transaction." |
---|
| 648 | << std::endl; |
---|
[240] | 649 | #endif |
---|
[434] | 650 | r_dma_cmd_fsm = DMA_CMD_IDLE; |
---|
| 651 | } |
---|
[240] | 652 | } |
---|
| 653 | break; |
---|
| 654 | } |
---|
[434] | 655 | /////////////////////// |
---|
| 656 | case DMA_CMD_MISS_WAIT: // waiting completion of a TLB miss |
---|
| 657 | // we must test a possible page fault error... |
---|
[240] | 658 | { |
---|
[434] | 659 | if ( not r_dma_tlb_req.read() ) // TLB miss completed |
---|
[240] | 660 | { |
---|
[434] | 661 | if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM |
---|
[240] | 662 | { |
---|
[434] | 663 | r_iommu_etr = MMU_READ_PT2_UNMAPPED; |
---|
| 664 | r_iommu_bvar = r_dma_cmd_vaddr.read(); |
---|
| 665 | r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); |
---|
| 666 | r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; |
---|
[240] | 667 | } |
---|
[434] | 668 | else // No error |
---|
| 669 | { |
---|
| 670 | r_dma_cmd_fsm = DMA_CMD_IDLE; |
---|
| 671 | } |
---|
[240] | 672 | } |
---|
| 673 | break; |
---|
| 674 | } |
---|
[434] | 675 | } // end switch DMA_CMD FSM |
---|
[240] | 676 | |
---|
| 677 | ////////////////////////////////////////////////////////////////////////////// |
---|
[434] | 678 | // The DMA_RSP_FSM handles the RAM responses to peripherals DMA transactions. |
---|
| 679 | ////////////////////////////////////////////////////////////////////////////// |
---|
| 680 | |
---|
[240] | 681 | switch( r_dma_rsp_fsm.read() ) |
---|
| 682 | { |
---|
[434] | 683 | ////////////////// |
---|
| 684 | case DMA_RSP_IDLE: // waiting a response from RAM betwork |
---|
[240] | 685 | { |
---|
[434] | 686 | if ( p_vci_ini_ram.rspval.read() ) |
---|
[240] | 687 | { |
---|
[434] | 688 | r_dma_rsp_fsm = DMA_RSP_FIFO_PUT; |
---|
[240] | 689 | } |
---|
| 690 | break; |
---|
| 691 | } |
---|
[434] | 692 | ////////////////////// |
---|
[240] | 693 | case DMA_RSP_FIFO_PUT: |
---|
| 694 | { |
---|
[434] | 695 | if(p_vci_ini_ram.rspval.read() and not r_alloc_fifo_dma_rsp_local.read() ) |
---|
[240] | 696 | { |
---|
| 697 | dma_rsp_fifo_put = true; |
---|
| 698 | |
---|
[434] | 699 | if(p_vci_ini_ram.reop.read()) r_dma_rsp_fsm = DMA_RSP_IDLE; |
---|
[240] | 700 | |
---|
| 701 | #if DEBUG_DMA_RSP |
---|
[434] | 702 | if( m_debug_activated ) |
---|
| 703 | std::cout << " <IOB DMA_RSP_FIFO_PUT> Push response into DMA_RSP fifo:" |
---|
| 704 | << " / rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() |
---|
| 705 | << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() |
---|
| 706 | << " / rdata = " << std::hex << p_vci_ini_ram.rdata.read() |
---|
| 707 | << " / rerror = " << p_vci_ini_ram.rerror.read() |
---|
| 708 | << " / reop = " << p_vci_ini_ram.reop.read() << std::endl; |
---|
[240] | 709 | #endif |
---|
| 710 | } |
---|
| 711 | break; |
---|
| 712 | } |
---|
| 713 | } // end switch DMA_RSP_FSM |
---|
| 714 | |
---|
[434] | 715 | ////////////////////////////////////////////////////////////////////////////////// |
---|
| 716 | // The TLB FSM handles TLB miss request (from DMA_CMD FSM), |
---|
| 717 | // and the PTE inval request (from CONFIG_CMD FSM). |
---|
| 718 | // PTE inval request have highest priority. In case of TLB miss, |
---|
| 719 | // this fsm searchs the requested PTE on the prefetch buffer. |
---|
| 720 | // In case of buffer miss, it request the MISS_WTI FSM to access the memory. |
---|
[240] | 721 | // It bypass the first level page table access if possible. |
---|
[434] | 722 | // It reset the r_dma_tlb_req flip-flop to signal TLB miss completion. |
---|
| 723 | // An unexpected, but possible page fault is signaled in r_tlb_miss_error flip_flop. |
---|
[240] | 724 | //////////////////////////////////////////////////////////////////////////////////// |
---|
[434] | 725 | |
---|
| 726 | switch (r_tlb_fsm.read()) |
---|
[240] | 727 | { |
---|
[434] | 728 | ////////////// |
---|
| 729 | case TLB_IDLE: // In case of TLB miss request, chek the prefetch buffer first |
---|
| 730 | // PTE inval request are handled as unmaskable interrupts |
---|
[240] | 731 | { |
---|
[434] | 732 | if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation |
---|
[240] | 733 | { |
---|
[434] | 734 | r_config_tlb_req = false; |
---|
[240] | 735 | r_waiting_transaction = false; |
---|
[434] | 736 | r_tlb_fsm = TLB_INVAL_CHECK; |
---|
[240] | 737 | } |
---|
[434] | 738 | |
---|
| 739 | else if ( r_dma_tlb_req.read() ) // request from DMA_CMD for a TLB Miss |
---|
[240] | 740 | { |
---|
[434] | 741 | // Checking prefetch buffer |
---|
| 742 | if( not r_tlb_buf_big_page ) // small page => PTE2 |
---|
[240] | 743 | { |
---|
[434] | 744 | if( r_tlb_buf_valid && // Hit on prefetch buffer |
---|
| 745 | (r_tlb_buf_vaddr.read() == |
---|
| 746 | (r_dma_cmd_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) |
---|
| 747 | { |
---|
| 748 | size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE2_LINE_OFFSET)>>12; |
---|
| 749 | uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; |
---|
| 750 | uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; |
---|
[240] | 751 | |
---|
[434] | 752 | // Bit valid checking |
---|
| 753 | if ( not ( pte_flags & PTE_V_MASK) ) // unmapped |
---|
| 754 | { |
---|
| 755 | std::cout << "VCI_IO_BRIDGE ERROR : " << name() |
---|
| 756 | << " Page Table entry unmapped" << std::endl; |
---|
[240] | 757 | |
---|
[434] | 758 | r_tlb_miss_error = true; |
---|
| 759 | r_dma_tlb_req = false; |
---|
| 760 | #if DEBUG_TLB_MISS |
---|
| 761 | if ( m_debug_activated ) |
---|
| 762 | std::cout << " <IOB TLB_IDLE> PTE2 Unmapped" << std::hex |
---|
| 763 | << " / paddr = " << r_tlb_paddr.read() |
---|
| 764 | << " / PTE_FLAGS = " << pte_flags |
---|
| 765 | << " / PTE_PPN = " << pte_ppn << std::endl; |
---|
[240] | 766 | #endif |
---|
[434] | 767 | break; |
---|
| 768 | } |
---|
[240] | 769 | |
---|
[434] | 770 | // valid PTE2 : we must update the TLB |
---|
| 771 | r_tlb_pte_flags = pte_flags; |
---|
| 772 | r_tlb_pte_ppn = pte_ppn; |
---|
| 773 | r_tlb_fsm = TLB_PTE2_SELECT; |
---|
| 774 | #if DEBUG_TLB_MISS |
---|
| 775 | if ( m_debug_activated ) |
---|
| 776 | std::cout << " <IOB TLB_IDLE> Hit on prefetch buffer: PTE2" << std::hex |
---|
| 777 | << " / PTE_FLAGS = " << pte_flags |
---|
| 778 | << " / PTE_PPN = " << pte_ppn << std::endl; |
---|
[240] | 779 | #endif |
---|
[434] | 780 | break; |
---|
| 781 | } |
---|
[240] | 782 | } |
---|
[434] | 783 | else // big page => PTE1 |
---|
[240] | 784 | { |
---|
[434] | 785 | if( r_tlb_buf_valid && // Hit on prefetch buffer |
---|
| 786 | (r_tlb_buf_vaddr.read() == |
---|
| 787 | (r_dma_cmd_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) |
---|
| 788 | { |
---|
| 789 | size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE1_LINE_OFFSET)>>21; |
---|
| 790 | uint32_t pte_flags = r_tlb_buf_data[pte_offset]; |
---|
[240] | 791 | |
---|
[434] | 792 | // Bit valid checking |
---|
| 793 | if ( not ( pte_flags & PTE_V_MASK) ) // unmapped |
---|
| 794 | { |
---|
| 795 | std::cout << "VCI_IO_BRIDGE ERROR : " << name() |
---|
| 796 | << " Page Table entry unmapped" << std::endl; |
---|
[240] | 797 | |
---|
[434] | 798 | r_tlb_miss_error = true; |
---|
| 799 | r_dma_tlb_req = false; |
---|
| 800 | #if DEBUG_TLB_MISS |
---|
| 801 | if ( m_debug_activated ) |
---|
| 802 | std::cout << " <IOB TLB_IDLE> PTE1 Unmapped" << std::hex |
---|
| 803 | << " / paddr = " << r_tlb_paddr.read() |
---|
| 804 | << " / PTE = " << pte_flags << std::endl; |
---|
[240] | 805 | #endif |
---|
[434] | 806 | break; |
---|
| 807 | } |
---|
[240] | 808 | |
---|
[434] | 809 | // valid PTE1 : we must update the TLB |
---|
| 810 | r_tlb_pte_flags = pte_flags; |
---|
| 811 | r_tlb_fsm = TLB_PTE1_SELECT; |
---|
| 812 | #if DEBUG_TLB_MISS |
---|
| 813 | if ( m_debug_activated ) |
---|
| 814 | std::cout << " <IOB TLB_PTE1_GET> Hit on prefetch buffer: PTE1" << std::hex |
---|
| 815 | << " / paddr = " << r_tlb_paddr.read() |
---|
| 816 | << std::hex << " / PTE1 = " << pte_flags << std::endl; |
---|
[240] | 817 | #endif |
---|
[434] | 818 | break; |
---|
[240] | 819 | } |
---|
| 820 | } |
---|
| 821 | |
---|
[434] | 822 | // prefetch buffer miss |
---|
| 823 | r_tlb_fsm = TLB_MISS; |
---|
[240] | 824 | |
---|
[434] | 825 | #if DEBUG_TLB_MISS |
---|
| 826 | if ( m_debug_activated ) |
---|
| 827 | std::cout << " <IOB TLB_IDLE> Miss on prefetch buffer" |
---|
| 828 | << std::hex << " / vaddr = " << r_dma_cmd_vaddr.read() << std::endl; |
---|
[240] | 829 | #endif |
---|
| 830 | } |
---|
| 831 | break; |
---|
| 832 | } |
---|
[434] | 833 | ////////////// |
---|
| 834 | case TLB_MISS: // handling tlb miss |
---|
[240] | 835 | { |
---|
[434] | 836 | uint32_t ptba = 0; |
---|
[240] | 837 | bool bypass; |
---|
[434] | 838 | vci_addr_t pte_paddr; |
---|
[240] | 839 | |
---|
[434] | 840 | #ifdef INSTRUMENTATION |
---|
| 841 | m_cpt_iotlbmiss_transaction++; |
---|
| 842 | #endif |
---|
[240] | 843 | // evaluate bypass in order to skip first level page table access |
---|
[434] | 844 | bypass = r_iotlb.get_bypass(r_dma_cmd_vaddr.read(), &ptba); |
---|
[240] | 845 | |
---|
[434] | 846 | // Request MISS_WTI_FSM a transaction on INT Network |
---|
[240] | 847 | if ( not bypass ) // Read PTE1/PTD1 in XRAM |
---|
| 848 | { |
---|
[434] | 849 | |
---|
| 850 | #if DEBUG_TLB_MISS |
---|
| 851 | if ( m_debug_activated ) |
---|
| 852 | std::cout << " <IOB TLB_MISS> Read PTE1/PTD1 in memory" << std::endl; |
---|
| 853 | #endif |
---|
| 854 | pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | |
---|
| 855 | (vci_addr_t)((r_dma_cmd_vaddr.read() >> PAGE_M_NBITS) << 2); |
---|
| 856 | r_tlb_paddr = pte_paddr; |
---|
[240] | 857 | |
---|
[434] | 858 | r_tlb_miss_req = true; |
---|
| 859 | r_tlb_miss_type = PTE1_MISS; |
---|
| 860 | r_tlb_fsm = TLB_WAIT; |
---|
[240] | 861 | } |
---|
| 862 | else // Read PTE2 in XRAM |
---|
| 863 | { |
---|
[434] | 864 | |
---|
| 865 | #if DEBUG_TLB_MISS |
---|
| 866 | if ( m_debug_activated ) |
---|
| 867 | std::cout << " <IOB TLB_MISS> Read PTE2 in memory" << std::endl; |
---|
| 868 | #endif |
---|
[240] | 869 | //&PTE2 = PTBA + IX2 * 8 |
---|
[434] | 870 | pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | |
---|
| 871 | (vci_addr_t)(r_dma_cmd_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); |
---|
[240] | 872 | |
---|
[434] | 873 | r_tlb_paddr = pte_paddr; |
---|
[240] | 874 | |
---|
[434] | 875 | r_tlb_miss_req = true; |
---|
| 876 | r_tlb_miss_type = PTE2_MISS; |
---|
| 877 | r_tlb_fsm = TLB_WAIT; |
---|
[240] | 878 | } |
---|
| 879 | |
---|
| 880 | break; |
---|
| 881 | } |
---|
[434] | 882 | ////////////////// |
---|
| 883 | case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer |
---|
[240] | 884 | { |
---|
| 885 | |
---|
| 886 | uint32_t entry; |
---|
| 887 | |
---|
[434] | 888 | vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); |
---|
| 889 | size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); |
---|
[240] | 890 | |
---|
| 891 | // Hit test. Just to verify. |
---|
| 892 | // Hit must happen, since we've just finished its' miss transaction |
---|
[434] | 893 | bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); |
---|
[240] | 894 | assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); |
---|
| 895 | |
---|
[434] | 896 | entry = r_tlb_buf_data[word_position]; |
---|
[240] | 897 | |
---|
| 898 | // Bit valid checking |
---|
| 899 | if ( not ( entry & PTE_V_MASK) ) // unmapped |
---|
| 900 | { |
---|
| 901 | //must not occur! |
---|
[434] | 902 | std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl |
---|
[240] | 903 | << "The Page Table entry ins't valid (unmapped)" << std::endl; |
---|
| 904 | |
---|
[434] | 905 | r_tlb_miss_error = true; |
---|
| 906 | r_dma_tlb_req = false; |
---|
| 907 | r_tlb_fsm = TLB_IDLE; |
---|
| 908 | |
---|
| 909 | #if DEBUG_TLB_MISS |
---|
| 910 | if ( m_debug_activated ) |
---|
[240] | 911 | { |
---|
[434] | 912 | std::cout << " <IOB DMA_PTE1_GET> First level entry Unmapped" |
---|
| 913 | << std::hex << " / paddr = " << r_tlb_paddr.read() |
---|
[240] | 914 | << std::hex << " / PTE = " << entry << std::endl; |
---|
| 915 | } |
---|
| 916 | #endif |
---|
| 917 | break; |
---|
| 918 | } |
---|
| 919 | |
---|
| 920 | if( entry & PTE_T_MASK ) // PTD : me must access PT2 |
---|
| 921 | { |
---|
| 922 | // register bypass |
---|
[434] | 923 | r_iotlb.set_bypass( r_dma_cmd_vaddr.read(), |
---|
| 924 | entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), |
---|
[240] | 925 | 0); //nline, unused |
---|
| 926 | |
---|
| 927 | //&PTE2 = PTBA + IX2 * 8 |
---|
| 928 | // ps: PAGE_K_NBITS corresponds also to the size of a second level page table |
---|
[434] | 929 | r_tlb_paddr = (vci_addr_t)(entry & ((1<<(vci_param_int::N-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | |
---|
| 930 | (vci_addr_t)(((r_dma_cmd_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); |
---|
| 931 | r_tlb_miss_req = true; |
---|
| 932 | r_tlb_miss_type = PTE2_MISS; |
---|
| 933 | r_tlb_fsm = TLB_WAIT; |
---|
| 934 | |
---|
[240] | 935 | #ifdef INSTRUMENTATION |
---|
| 936 | m_cpt_iotlbmiss_transaction++; |
---|
| 937 | #endif |
---|
| 938 | |
---|
[434] | 939 | #if DEBUG_TLB_MISS |
---|
| 940 | if ( m_debug_activated ) |
---|
| 941 | std::cout << " <IOB TLB_PTE1_GET> Success. Search PTE2" << std::hex |
---|
| 942 | << " / PADDR = " << r_tlb_paddr.read() |
---|
| 943 | << " / PTD = " << entry << std::endl; |
---|
[240] | 944 | #endif |
---|
| 945 | } |
---|
| 946 | else // PTE1 : we must update the IOTLB |
---|
| 947 | // Should not occur if working only with small pages |
---|
| 948 | { |
---|
[434] | 949 | r_tlb_pte_flags = entry; |
---|
| 950 | r_tlb_fsm = TLB_PTE1_SELECT; |
---|
[240] | 951 | |
---|
[434] | 952 | #if DEBUG_TLB_MISS |
---|
| 953 | if ( m_debug_activated ) |
---|
| 954 | std::cout << " <IOB TLB_PTE1_GET> Success. Big page" |
---|
| 955 | << std::hex << " / paddr = " << r_tlb_paddr.read() |
---|
| 956 | << std::hex << " / PTE1 = " << entry << std::endl; |
---|
[240] | 957 | #endif |
---|
| 958 | } |
---|
| 959 | break; |
---|
| 960 | } |
---|
[434] | 961 | ///////////////////// |
---|
| 962 | case TLB_PTE1_SELECT: // select a slot for PTE1 |
---|
[240] | 963 | { |
---|
| 964 | size_t way; |
---|
| 965 | size_t set; |
---|
| 966 | |
---|
[434] | 967 | r_iotlb.select( r_dma_cmd_vaddr.read(), |
---|
[240] | 968 | true, // PTE1 |
---|
| 969 | &way, |
---|
| 970 | &set ); |
---|
| 971 | #ifdef INSTRUMENTATION |
---|
| 972 | m_cpt_iotlb_read++; |
---|
| 973 | #endif |
---|
| 974 | |
---|
[434] | 975 | #if DEBUG_TLB_MISS |
---|
| 976 | if ( m_debug_activated ) |
---|
| 977 | std::cout << " <IOB TLB_PTE1_SELECT> Select a slot in TLB" |
---|
| 978 | << " / way = " << std::dec << way |
---|
| 979 | << " / set = " << set << std::endl; |
---|
[240] | 980 | #endif |
---|
[434] | 981 | r_tlb_way = way; |
---|
| 982 | r_tlb_set = set; |
---|
| 983 | r_tlb_fsm = TLB_PTE1_UPDT; |
---|
[240] | 984 | break; |
---|
| 985 | } |
---|
[434] | 986 | /////////////////// |
---|
| 987 | case TLB_PTE1_UPDT: // write a new PTE1 in tlb |
---|
| 988 | // not necessary to treat the L/R bit |
---|
[240] | 989 | { |
---|
[434] | 990 | uint32_t pte = r_tlb_pte_flags.read(); |
---|
[240] | 991 | |
---|
[434] | 992 | r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) |
---|
| 993 | | (r_dma_cmd_vaddr.read()& M_PAGE_OFFSET_MASK) ); |
---|
[240] | 994 | |
---|
| 995 | // update TLB |
---|
| 996 | r_iotlb.write( true, // 2M page |
---|
| 997 | pte, |
---|
| 998 | 0, // argument unused for a PTE1 |
---|
[434] | 999 | r_dma_cmd_vaddr.read(), |
---|
| 1000 | r_tlb_way.read(), |
---|
| 1001 | r_tlb_set.read(), |
---|
[240] | 1002 | 0 ); //we set nline = 0 |
---|
| 1003 | #ifdef INSTRUMENTATION |
---|
| 1004 | m_cpt_iotlb_write++; |
---|
| 1005 | #endif |
---|
| 1006 | |
---|
[434] | 1007 | #if DEBUG_TLB_MISS |
---|
| 1008 | if ( m_debug_activated ) |
---|
[240] | 1009 | { |
---|
[434] | 1010 | std::cout << " <IOB TLB_PTE1_UPDT> write PTE1 in TLB" |
---|
| 1011 | << " / set = " << std::dec << r_tlb_set.read() |
---|
| 1012 | << " / way = " << r_tlb_way.read() << std::endl; |
---|
| 1013 | r_iotlb.printTrace(); |
---|
[240] | 1014 | } |
---|
| 1015 | #endif |
---|
| 1016 | // next state |
---|
[434] | 1017 | r_tlb_fsm = TLB_RETURN; // exit sub-fsm |
---|
[240] | 1018 | break; |
---|
| 1019 | } |
---|
[434] | 1020 | ////////////////// |
---|
| 1021 | case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer |
---|
[240] | 1022 | { |
---|
| 1023 | uint32_t pte_flags; |
---|
| 1024 | uint32_t pte_ppn; |
---|
| 1025 | |
---|
[434] | 1026 | vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); |
---|
| 1027 | size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); |
---|
[240] | 1028 | |
---|
| 1029 | |
---|
| 1030 | // Hit test. Just to verify. |
---|
[434] | 1031 | bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); |
---|
[240] | 1032 | assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); |
---|
[434] | 1033 | pte_flags= r_tlb_buf_data[word_position]; |
---|
| 1034 | pte_ppn= r_tlb_buf_data[word_position+1]; //because PTE2 is 2 words long |
---|
[240] | 1035 | // Bit valid checking |
---|
| 1036 | if ( not ( pte_flags & PTE_V_MASK) ) // unmapped |
---|
| 1037 | { |
---|
| 1038 | //must not occur! |
---|
[434] | 1039 | std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl |
---|
[240] | 1040 | << "The Page Table entry ins't valid (unmapped)" << std::endl; |
---|
| 1041 | |
---|
[434] | 1042 | r_tlb_miss_error = true; |
---|
| 1043 | r_dma_tlb_req = false; |
---|
| 1044 | r_tlb_fsm = TLB_IDLE; |
---|
| 1045 | |
---|
| 1046 | #if DEBUG_TLB_MISS |
---|
| 1047 | if ( m_debug_activated ) |
---|
| 1048 | std::cout << " <IOB TLB_PTE2_GET> PTE2 Unmapped" << std::hex |
---|
| 1049 | << " / PADDR = " << r_tlb_paddr.read() |
---|
| 1050 | << " / PTE = " << pte_flags << std::endl; |
---|
[240] | 1051 | #endif |
---|
[434] | 1052 | break; |
---|
[240] | 1053 | } |
---|
| 1054 | |
---|
[434] | 1055 | r_tlb_pte_flags = pte_flags; |
---|
| 1056 | r_tlb_pte_ppn = pte_ppn; |
---|
| 1057 | r_tlb_fsm = TLB_PTE2_SELECT; |
---|
[240] | 1058 | |
---|
[434] | 1059 | #if DEBUG_TLB_MISS |
---|
| 1060 | if ( m_debug_activated ) |
---|
| 1061 | std::cout << " <IOB TLB_PTE2_GET> Mapped" << std::hex |
---|
| 1062 | << " / PTE_FLAGS = " << pte_flags |
---|
| 1063 | << " / PTE_PPN = " << pte_ppn << std::endl; |
---|
[240] | 1064 | #endif |
---|
| 1065 | break; |
---|
| 1066 | } |
---|
| 1067 | //////////////////////////// |
---|
[434] | 1068 | case TLB_PTE2_SELECT: // select a slot for PTE2 |
---|
[240] | 1069 | { |
---|
| 1070 | size_t way; |
---|
| 1071 | size_t set; |
---|
| 1072 | |
---|
[434] | 1073 | r_iotlb.select( r_dma_cmd_vaddr.read(), |
---|
[240] | 1074 | false, // PTE2 |
---|
| 1075 | &way, |
---|
| 1076 | &set ); |
---|
| 1077 | #ifdef INSTRUMENTATION |
---|
| 1078 | m_cpt_iotlb_read++; |
---|
| 1079 | #endif |
---|
| 1080 | |
---|
[434] | 1081 | #if DEBUG_TLB_MISS |
---|
| 1082 | if ( m_debug_activated ) |
---|
[240] | 1083 | { |
---|
[434] | 1084 | std::cout << " <IOB TLB_PTE2_SELECT> Select a slot in IOTLB:"; |
---|
[240] | 1085 | std::cout << " way = " << std::dec << way |
---|
| 1086 | << " / set = " << set << std::endl; |
---|
| 1087 | } |
---|
| 1088 | #endif |
---|
[434] | 1089 | r_tlb_way = way; |
---|
| 1090 | r_tlb_set = set; |
---|
| 1091 | r_tlb_fsm = TLB_PTE2_UPDT; |
---|
[240] | 1092 | break; |
---|
| 1093 | } |
---|
[434] | 1094 | /////////////////// |
---|
| 1095 | case TLB_PTE2_UPDT: // write a new PTE2 in tlb |
---|
| 1096 | // not necessary to treat the L/R bit |
---|
[240] | 1097 | { |
---|
[434] | 1098 | uint32_t pte_flags = r_tlb_pte_flags.read(); |
---|
| 1099 | uint32_t pte_ppn = r_tlb_pte_ppn.read(); |
---|
[240] | 1100 | |
---|
[434] | 1101 | r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) |
---|
| 1102 | | (r_dma_cmd_vaddr.read()& K_PAGE_OFFSET_MASK) ); |
---|
[240] | 1103 | |
---|
| 1104 | // update TLB for a PTE2 |
---|
| 1105 | r_iotlb.write( false, // 4K page |
---|
| 1106 | pte_flags, |
---|
| 1107 | pte_ppn, |
---|
[434] | 1108 | r_dma_cmd_vaddr.read(), |
---|
| 1109 | r_tlb_way.read(), |
---|
| 1110 | r_tlb_set.read(), |
---|
[240] | 1111 | 0 ); // nline = 0 |
---|
| 1112 | #ifdef INSTRUMENTATION |
---|
| 1113 | m_cpt_iotlb_write++; |
---|
| 1114 | #endif |
---|
| 1115 | |
---|
[434] | 1116 | #if DEBUG_TLB_MISS |
---|
| 1117 | if ( m_debug_activated ) |
---|
[240] | 1118 | { |
---|
[434] | 1119 | std::cout << " <IOB TLB_PTE2_UPDT> write PTE2 in IOTLB"; |
---|
| 1120 | std::cout << " / set = " << std::dec << r_tlb_set.read() |
---|
| 1121 | << " / way = " << r_tlb_way.read() << std::endl; |
---|
[240] | 1122 | r_iotlb.printTrace(); |
---|
| 1123 | } |
---|
| 1124 | #endif |
---|
| 1125 | // next state |
---|
[434] | 1126 | r_tlb_fsm = TLB_RETURN; |
---|
[240] | 1127 | break; |
---|
| 1128 | } |
---|
[434] | 1129 | ////////////// |
---|
| 1130 | case TLB_WAIT: // waiting completion of a miss transaction from MISS_WTI FSM |
---|
| 1131 | // PTE inval request are handled as unmaskable interrupts |
---|
[240] | 1132 | { |
---|
[434] | 1133 | if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation |
---|
[240] | 1134 | { |
---|
| 1135 | r_config_tlb_req = false; |
---|
| 1136 | r_waiting_transaction = true; |
---|
[434] | 1137 | r_tlb_fsm = TLB_INVAL_CHECK; |
---|
[240] | 1138 | } |
---|
| 1139 | |
---|
| 1140 | #ifdef INSTRUMENTATION |
---|
| 1141 | m_cost_iotlbmiss_transaction++; |
---|
| 1142 | #endif |
---|
[434] | 1143 | if ( not r_tlb_miss_req ) // Miss transaction is done |
---|
[240] | 1144 | { |
---|
[434] | 1145 | if ( r_miss_wti_rsp_error.read() ) // bus error |
---|
[240] | 1146 | { |
---|
[434] | 1147 | r_miss_wti_rsp_error = false; |
---|
| 1148 | r_tlb_miss_error = true; |
---|
| 1149 | r_dma_tlb_req = false; |
---|
| 1150 | r_tlb_fsm = TLB_IDLE; |
---|
[240] | 1151 | } |
---|
| 1152 | else if(r_tlb_miss_type == PTE1_MISS) |
---|
| 1153 | { |
---|
[434] | 1154 | r_tlb_fsm = TLB_PTE1_GET; |
---|
[240] | 1155 | } |
---|
| 1156 | else |
---|
| 1157 | { |
---|
[434] | 1158 | r_tlb_fsm = TLB_PTE2_GET; |
---|
[240] | 1159 | } |
---|
| 1160 | } |
---|
| 1161 | break; |
---|
| 1162 | } |
---|
[434] | 1163 | //////////////// |
---|
| 1164 | case TLB_RETURN: // reset r_dma_tlb_req flip-flop to signal TLB miss completion |
---|
| 1165 | // possible errors are signaled through r_tlb_miss_error |
---|
[240] | 1166 | { |
---|
[434] | 1167 | #if DEBUG_TLB_MISS |
---|
| 1168 | if ( m_debug_activated ) |
---|
| 1169 | std::cout << " <IOB TLB_RETURN> IOTLB MISS completed" << std::endl; |
---|
[240] | 1170 | #endif |
---|
[434] | 1171 | r_dma_tlb_req = false; |
---|
| 1172 | r_tlb_fsm = TLB_IDLE; |
---|
[240] | 1173 | break; |
---|
| 1174 | } |
---|
[434] | 1175 | ///////////////////// |
---|
| 1176 | case TLB_INVAL_CHECK: // request from CONFIG_FSM to invalidate all PTE in a given line |
---|
| 1177 | // checks the necessity to invalidate prefetch buffer |
---|
[240] | 1178 | { |
---|
| 1179 | // If a transaction is pending, no need to invalidate the prefetch |
---|
| 1180 | // We can ignore it, since we'll replace the line. |
---|
| 1181 | // The new line is necessarily up-to-date |
---|
[434] | 1182 | if(!r_waiting_transaction.read() && r_tlb_buf_valid) |
---|
[240] | 1183 | { |
---|
[434] | 1184 | if(!r_tlb_buf_big_page) |
---|
[240] | 1185 | { |
---|
[434] | 1186 | if( r_tlb_buf_vaddr.read() == |
---|
| 1187 | (r_config_cmd_inval_vaddr.read()& ~PTE2_LINE_OFFSET) ) |
---|
[240] | 1188 | // The virtual address corresponds to one entry on the buffer line |
---|
| 1189 | { |
---|
[434] | 1190 | r_tlb_buf_valid = false; //change here for individual invalidation |
---|
[240] | 1191 | } |
---|
| 1192 | } |
---|
| 1193 | else // First level entries on buffer. Unused if only small pages |
---|
| 1194 | { |
---|
[434] | 1195 | if( r_tlb_buf_vaddr.read() == |
---|
| 1196 | (r_config_cmd_inval_vaddr.read()& ~PTE1_LINE_OFFSET) ) |
---|
[240] | 1197 | // The virtual address corresponds to one entry on the buffer line |
---|
| 1198 | { |
---|
[434] | 1199 | r_tlb_buf_valid = false; //change here for individual invalidation |
---|
[240] | 1200 | } |
---|
| 1201 | } |
---|
| 1202 | } |
---|
| 1203 | |
---|
| 1204 | // Invalidation on IOTLB |
---|
| 1205 | bool ok; |
---|
[434] | 1206 | ok = r_iotlb.inval(r_config_cmd_inval_vaddr.read()); |
---|
[240] | 1207 | |
---|
[434] | 1208 | if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; |
---|
| 1209 | else r_tlb_fsm = TLB_IDLE; |
---|
[240] | 1210 | break; |
---|
| 1211 | } |
---|
[434] | 1212 | } //end switch r_tlb_fsm |
---|
[240] | 1213 | |
---|
[434] | 1214 | //////////////////////////////////////////////////////////////////////////////// |
---|
| 1215 | // The CONFIG_CMD_FSM handles the VCI commands from the INT network. |
---|
| 1216 | // This FSM is mainly intended to handle single flit config transactions, |
---|
| 1217 | // but it can also handle software driven, multi-flits data transactions. |
---|
[451] | 1218 | // The configuration requests can be local (IO_BRIDGE config registers) |
---|
| 1219 | // or remote (config registers of peripherals on IOX network). |
---|
| 1220 | // - The local configuration segment is identified by the "special" atribute. |
---|
| 1221 | // - All configuration requests are checkeg against segmentation violation. |
---|
| 1222 | // - In case of local config request, or in case of segmentation violation, |
---|
| 1223 | // the FSM put a VCI response request in CONFIG_RSP fifo. |
---|
| 1224 | // - In case of remote transaction, it put the VCI command in CONFIG_CMD fifo. |
---|
[434] | 1225 | /////////////////////////////////////////////////////////////////////////////// |
---|
[240] | 1226 | |
---|
| 1227 | switch( r_config_cmd_fsm.read() ) |
---|
| 1228 | { |
---|
[434] | 1229 | ///////////////////// |
---|
| 1230 | case CONFIG_CMD_IDLE: // waiting VCI command |
---|
[240] | 1231 | { |
---|
[434] | 1232 | if ( p_vci_tgt_int.cmdval.read() ) |
---|
[240] | 1233 | { |
---|
[434] | 1234 | |
---|
[240] | 1235 | #if DEBUG_CONFIG_CMD |
---|
[434] | 1236 | if( m_debug_activated ) |
---|
| 1237 | std::cout << " <IOB CONFIG_CMD_IDLE> Command received" |
---|
| 1238 | << " / address = " << std::hex << p_vci_tgt_int.address.read() |
---|
| 1239 | << " / srcid = " << std::dec << p_vci_tgt_int.srcid.read() |
---|
| 1240 | << " / trdid = " << p_vci_tgt_int.trdid.read() |
---|
| 1241 | << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() |
---|
| 1242 | << " / be = " << p_vci_tgt_int.be.read() |
---|
| 1243 | << " / plen = " << std::dec << p_vci_tgt_int.plen.read() |
---|
| 1244 | << " / eop = " << p_vci_tgt_int.eop.read() << std::endl; |
---|
[240] | 1245 | #endif |
---|
[434] | 1246 | vci_addr_t paddr = p_vci_tgt_int.address.read(); |
---|
| 1247 | bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); |
---|
| 1248 | uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); |
---|
[240] | 1249 | |
---|
[451] | 1250 | // chek segments |
---|
| 1251 | std::list<soclib::common::Segment>::iterator seg; |
---|
[549] | 1252 | bool found = false; |
---|
| 1253 | bool special = false; |
---|
[451] | 1254 | for ( seg = m_int_seglist.begin() ; |
---|
| 1255 | seg != m_int_seglist.end() and not found ; seg++ ) |
---|
| 1256 | { |
---|
[549] | 1257 | if ( seg->contains(paddr) ) |
---|
| 1258 | { |
---|
| 1259 | found = true; |
---|
| 1260 | special = seg->special(); |
---|
| 1261 | } |
---|
[451] | 1262 | } |
---|
[434] | 1263 | |
---|
[549] | 1264 | if ( found and special ) // IO_BRIDGE itself |
---|
[240] | 1265 | { |
---|
[434] | 1266 | uint32_t rdata = 0; |
---|
| 1267 | bool rerror = false; |
---|
| 1268 | |
---|
| 1269 | if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR |
---|
[240] | 1270 | { |
---|
[434] | 1271 | r_iommu_ptpr = (uint32_t)p_vci_tgt_int.wdata.read(); |
---|
| 1272 | } |
---|
| 1273 | else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR |
---|
[240] | 1274 | { |
---|
[434] | 1275 | rdata = r_iommu_ptpr.read(); |
---|
[240] | 1276 | } |
---|
[434] | 1277 | else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE |
---|
[240] | 1278 | { |
---|
[434] | 1279 | r_iommu_wti_enable = p_vci_tgt_int.wdata.read(); |
---|
[240] | 1280 | } |
---|
[434] | 1281 | else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE |
---|
[240] | 1282 | { |
---|
[434] | 1283 | rdata = r_iommu_wti_enable.read(); |
---|
[240] | 1284 | } |
---|
[434] | 1285 | else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR |
---|
[240] | 1286 | { |
---|
[434] | 1287 | rdata = r_iommu_bvar.read(); |
---|
[240] | 1288 | } |
---|
[434] | 1289 | else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR |
---|
[240] | 1290 | { |
---|
[434] | 1291 | rdata = r_iommu_etr.read(); |
---|
[240] | 1292 | } |
---|
[434] | 1293 | else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID |
---|
[240] | 1294 | { |
---|
[434] | 1295 | rdata = r_iommu_bad_id.read(); |
---|
[240] | 1296 | } |
---|
[434] | 1297 | else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE |
---|
[240] | 1298 | { |
---|
[434] | 1299 | r_config_tlb_req = true; |
---|
| 1300 | r_config_cmd_inval_vaddr = (uint32_t)p_vci_tgt_int.wdata.read(); |
---|
[240] | 1301 | } |
---|
[434] | 1302 | else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO |
---|
[240] | 1303 | { |
---|
[434] | 1304 | r_iommu_wti_paddr = (vci_addr_t)p_vci_tgt_int.wdata.read(); |
---|
[240] | 1305 | } |
---|
[434] | 1306 | else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO |
---|
[240] | 1307 | { |
---|
[434] | 1308 | rdata = (uint32_t)r_iommu_wti_paddr.read(); |
---|
[240] | 1309 | } |
---|
[434] | 1310 | else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI |
---|
[240] | 1311 | { |
---|
[434] | 1312 | r_iommu_wti_paddr = (r_iommu_wti_paddr.read() & 0x00000000FFFFFFFFLL) | |
---|
| 1313 | ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; |
---|
[240] | 1314 | } |
---|
[434] | 1315 | else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI |
---|
[240] | 1316 | { |
---|
[434] | 1317 | rdata = (uint32_t)(r_iommu_wti_paddr.read()>>32); |
---|
[240] | 1318 | } |
---|
[434] | 1319 | else if( not read && ((cell >= IOB_PERI_WTI_BEGIN) // WRITE PERI WTI |
---|
| 1320 | && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) |
---|
| 1321 | { |
---|
| 1322 | size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; |
---|
| 1323 | bool high = (cell - IOB_PERI_WTI_BEGIN)%2; |
---|
| 1324 | if ( high ) r_iommu_peri_wti[index] = // set 32 MSB bits |
---|
| 1325 | (r_iommu_peri_wti[index].read() & 0x00000000FFFFFFFFLL) | |
---|
| 1326 | ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; |
---|
| 1327 | else r_iommu_peri_wti[index] = // set 32 LSB bits |
---|
| 1328 | (vci_addr_t)p_vci_tgt_int.wdata.read(); |
---|
| 1329 | } |
---|
| 1330 | else if( read && ((cell >= IOB_PERI_WTI_BEGIN) // READ PERI WTI |
---|
| 1331 | && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) |
---|
| 1332 | { |
---|
| 1333 | size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; |
---|
| 1334 | bool high = (cell - IOB_PERI_WTI_BEGIN)%2; |
---|
| 1335 | if ( high ) rdata = (uint32_t)(r_iommu_peri_wti[index].read()>>32); |
---|
| 1336 | else rdata = (uint32_t)(r_iommu_peri_wti[index].read()); |
---|
| 1337 | } |
---|
| 1338 | else // Error: Wrong address, or invalid operation. |
---|
| 1339 | { |
---|
| 1340 | rerror = true; |
---|
| 1341 | } |
---|
[451] | 1342 | r_config_cmd_rdata = rdata; |
---|
[434] | 1343 | r_config_cmd_error = rerror; |
---|
[451] | 1344 | r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_RSP; |
---|
[240] | 1345 | } |
---|
[451] | 1346 | else if ( found ) // remote peripheral |
---|
[240] | 1347 | { |
---|
[434] | 1348 | r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_CMD; |
---|
[240] | 1349 | } |
---|
[451] | 1350 | else // out of segment |
---|
| 1351 | { |
---|
| 1352 | r_config_cmd_rdata = 0; |
---|
| 1353 | r_config_cmd_error = true; |
---|
| 1354 | r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_RSP; |
---|
| 1355 | } |
---|
[434] | 1356 | } // end if cmdval |
---|
[240] | 1357 | break; |
---|
| 1358 | } |
---|
[434] | 1359 | ///////////////////////////// |
---|
| 1360 | case CONFIG_CMD_FIFO_PUT_CMD: // transmit VCI command from the INT network |
---|
| 1361 | // to the CONFIG_CMD fifo to IOX network |
---|
[240] | 1362 | { |
---|
[434] | 1363 | config_cmd_fifo_put = true; |
---|
| 1364 | |
---|
| 1365 | if ( p_vci_tgt_int.cmdval.read() and m_config_cmd_addr_fifo.wok() ) |
---|
[240] | 1366 | { |
---|
[434] | 1367 | |
---|
| 1368 | #if DEBUG_CONFIG_CMD |
---|
| 1369 | if( m_debug_activated ) |
---|
| 1370 | std::cout << " <IOB CONFIG_CMD_FIFO_PUT_CMD> Transmit VCI command to IOX network" |
---|
| 1371 | << " : address = " << std::hex << p_vci_tgt_int.address.read() |
---|
| 1372 | << " / srcid = " << p_vci_tgt_int.srcid.read() |
---|
| 1373 | << std::endl; |
---|
| 1374 | #endif |
---|
| 1375 | if( p_vci_tgt_int.eop.read() ) r_config_cmd_fsm = CONFIG_CMD_IDLE; |
---|
| 1376 | } |
---|
| 1377 | break; |
---|
[240] | 1378 | } |
---|
[434] | 1379 | ///////////////////////////// |
---|
| 1380 | case CONFIG_CMD_FIFO_PUT_RSP: // Try to put a response in CONFIG_RSP fifo, |
---|
| 1381 | // for a local configuration transaction. |
---|
| 1382 | // The FIFO is shared with CONFIG_RSP FSM |
---|
| 1383 | // and must we wait for allocation... |
---|
[240] | 1384 | { |
---|
[434] | 1385 | if ( p_vci_tgt_int.cmdval.read() and r_alloc_fifo_config_rsp_local.read() ) |
---|
[240] | 1386 | { |
---|
[434] | 1387 | config_rsp_fifo_put = true; |
---|
| 1388 | |
---|
| 1389 | if ( m_config_rsp_data_fifo.wok() ) |
---|
| 1390 | { |
---|
| 1391 | |
---|
| 1392 | #if DEBUG_CONFIG_CMD |
---|
| 1393 | if( m_debug_activated ) |
---|
| 1394 | std::cout << " <IOB CONFIG_CMD_FIFO_PUT_RSP> Response to a local configuration request" |
---|
| 1395 | << std::endl; |
---|
| 1396 | #endif |
---|
| 1397 | if( p_vci_tgt_int.eop.read() ) r_config_cmd_fsm = CONFIG_CMD_IDLE; |
---|
| 1398 | } |
---|
[240] | 1399 | } |
---|
| 1400 | break; |
---|
| 1401 | } |
---|
| 1402 | } // end switch CONFIG_CMD FSM |
---|
| 1403 | |
---|
| 1404 | ////////////////////////////////////////////////////////////////////////////// |
---|
[434] | 1405 | // The CONFIG_RSP_FSM handles the VCI responses from the periherals |
---|
| 1406 | // on the IOX network and writes the responses in the CONFIG_RSP fifo. |
---|
| 1407 | // The VCI response flit is only consumed in the FIFO_PUT state. |
---|
| 1408 | // This FSM is mainly intended to handle single flit config transactions, |
---|
| 1409 | // but it can also handle software driven, multi-flits data transactions. |
---|
| 1410 | ////////////////////////////////////////////////////////////////////////////// |
---|
| 1411 | |
---|
[240] | 1412 | switch( r_config_rsp_fsm.read() ) |
---|
| 1413 | { |
---|
| 1414 | ///////////////////// |
---|
[434] | 1415 | case CONFIG_RSP_IDLE: // waiting a VCI response from IOX network |
---|
[240] | 1416 | { |
---|
[434] | 1417 | if ( p_vci_ini_iox.rspval.read() ) |
---|
[240] | 1418 | { |
---|
[434] | 1419 | r_config_rsp_fsm = CONFIG_RSP_FIFO_PUT; |
---|
[240] | 1420 | } |
---|
| 1421 | break; |
---|
| 1422 | } |
---|
[434] | 1423 | ///////////////////////// |
---|
| 1424 | case CONFIG_RSP_FIFO_PUT: // try to write into CONFIG_RSP fifo |
---|
| 1425 | // as soon as it is allocated |
---|
[240] | 1426 | { |
---|
[434] | 1427 | if ( p_vci_ini_iox.rspval.read() and not r_alloc_fifo_config_rsp_local.read() ) |
---|
[240] | 1428 | { |
---|
| 1429 | config_rsp_fifo_put = true; |
---|
| 1430 | |
---|
[434] | 1431 | if ( m_config_rsp_data_fifo.wok() ) |
---|
| 1432 | { |
---|
| 1433 | if ( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE; |
---|
| 1434 | |
---|
[240] | 1435 | #if DEBUG_CONFIG_RSP |
---|
[434] | 1436 | if( m_debug_activated ) |
---|
| 1437 | std::cout << " <IOB CONFIG_RSP_FIFO_PUT> Push response into CONFIG_RSP fifo:" |
---|
| 1438 | << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() |
---|
| 1439 | << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() |
---|
| 1440 | << " / rdata = " << p_vci_ini_iox.rdata.read() |
---|
| 1441 | << " / reop = " << p_vci_ini_iox.reop.read() |
---|
| 1442 | << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; |
---|
[240] | 1443 | #endif |
---|
[434] | 1444 | } |
---|
[240] | 1445 | |
---|
| 1446 | } |
---|
| 1447 | break; |
---|
| 1448 | } |
---|
| 1449 | } // end switch CONFIG_RSP FSM |
---|
| 1450 | |
---|
[434] | 1451 | ///////////////////////////////////////////////////////////////////////////////// |
---|
| 1452 | // If the IOB component has IRQ ports, the IRQ FSM detects all changes |
---|
| 1453 | // on the 32 p_irq[i] ports and request a VCI write transaction to the |
---|
| 1454 | // MISS_INIT FSM, using the 64 r_irq_request[i] and r_irq_pending[i] flip-flops. |
---|
| 1455 | ///////////////////////////////////////////////////////////////////////////////// |
---|
[240] | 1456 | |
---|
[434] | 1457 | if ( m_has_irqs ) |
---|
[240] | 1458 | { |
---|
[434] | 1459 | for ( size_t i = 0; i<32; ++i ) |
---|
[240] | 1460 | { |
---|
[434] | 1461 | r_irq_request[i] = ( p_irq[i]->read() == not r_irq_pending[i].read() ); |
---|
| 1462 | r_irq_pending[i] = p_irq[i]->read(); |
---|
[240] | 1463 | } |
---|
| 1464 | } |
---|
[434] | 1465 | |
---|
| 1466 | /////////////////////////////////////////////////////////////////////////////////// |
---|
| 1467 | // The MISS_WTI_CMD FSM send VCI commands on the Internal Network. |
---|
| 1468 | // It handles PTE MISS requests from TLB_MISS FSM and software IRQs. |
---|
| 1469 | // It supports several simultaneous VCI transactions. |
---|
[240] | 1470 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1471 | |
---|
[434] | 1472 | switch ( r_miss_wti_cmd_fsm.read() ) |
---|
[240] | 1473 | { |
---|
[434] | 1474 | /////////////////////// |
---|
| 1475 | case MISS_WTI_CMD_IDLE: // TLB MISS have highest priority |
---|
[240] | 1476 | { |
---|
[434] | 1477 | if ( r_tlb_miss_req.read() ) |
---|
[240] | 1478 | { |
---|
[434] | 1479 | r_miss_wti_cmd_fsm = MISS_WTI_CMD_MISS; |
---|
[240] | 1480 | } |
---|
[434] | 1481 | else if ( r_iommu_wti_enable.read() ) |
---|
| 1482 | { |
---|
| 1483 | // checking if there is a new pending interrupt |
---|
[240] | 1484 | bool found = false; |
---|
[434] | 1485 | size_t n; |
---|
| 1486 | for ( n = 0 ; (n < 32) and not found ; n++ ) |
---|
[240] | 1487 | { |
---|
[434] | 1488 | if ( r_irq_request[n] ) found = true; |
---|
[240] | 1489 | } |
---|
[434] | 1490 | if ( found ) |
---|
| 1491 | { |
---|
| 1492 | r_miss_wti_cmd_index = n; |
---|
| 1493 | r_miss_wti_cmd_fsm = MISS_WTI_CMD_WTI; |
---|
| 1494 | } |
---|
[240] | 1495 | } |
---|
| 1496 | break; |
---|
| 1497 | } |
---|
[434] | 1498 | ////////////////////// |
---|
| 1499 | case MISS_WTI_CMD_WTI: // send a single flit IRQ WRITE on INT Network |
---|
| 1500 | // address is defined by IRQ_VECTOR[r_miss_wti_index] |
---|
| 1501 | // data is defined by r_irq_pending[r_miss_wti_index] |
---|
[240] | 1502 | { |
---|
[434] | 1503 | if ( p_vci_ini_int.cmdack ) |
---|
| 1504 | { |
---|
| 1505 | // reset the request |
---|
| 1506 | r_irq_request[r_miss_wti_cmd_index.read()] = false; |
---|
| 1507 | r_miss_wti_cmd_fsm = MISS_WTI_RSP_WTI; |
---|
[240] | 1508 | |
---|
[434] | 1509 | #if DEBUG_MISS_WTI |
---|
| 1510 | if( m_debug_activated ) |
---|
| 1511 | std::cout << " <IOB MISS_WTI_CMD_WTI> Send WTI write command on Internal Network" |
---|
| 1512 | << " / IRQID = " << std::dec << r_miss_wti_cmd_index.read() << std::endl; |
---|
| 1513 | #endif |
---|
[240] | 1514 | } |
---|
[434] | 1515 | break; |
---|
[240] | 1516 | } |
---|
[434] | 1517 | /////////////////////// |
---|
| 1518 | case MISS_WTI_CMD_MISS: // send a TLB MISS request on INT Network |
---|
[240] | 1519 | { |
---|
[434] | 1520 | if ( p_vci_ini_int.cmdack ) |
---|
| 1521 | { |
---|
| 1522 | r_tlb_buf_tag = ( (r_tlb_paddr.read()) & CACHE_LINE_MASK ); |
---|
| 1523 | r_tlb_buf_valid = true; |
---|
| 1524 | |
---|
| 1525 | if( r_tlb_miss_type.read() == PTE1_MISS ) |
---|
| 1526 | r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & |
---|
| 1527 | ~M_PAGE_OFFSET_MASK & ~PTE1_LINE_OFFSET); |
---|
| 1528 | else |
---|
| 1529 | r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & |
---|
| 1530 | ~K_PAGE_OFFSET_MASK & ~PTE2_LINE_OFFSET); |
---|
| 1531 | |
---|
| 1532 | r_miss_wti_cmd_fsm = MISS_WTI_RSP_MISS; |
---|
[240] | 1533 | |
---|
[434] | 1534 | #if DEBUG_MISS_WTI |
---|
| 1535 | if( m_debug_activated ) |
---|
| 1536 | std::cout << " <IOB MISS_WTI_CMD_MISS> Send TLB MISS command on Internal Network" << std::hex |
---|
| 1537 | << " / address = " <<(vci_addr_t)((r_tlb_paddr.read())& CACHE_LINE_MASK) << std::endl; |
---|
[240] | 1538 | #endif |
---|
[434] | 1539 | } |
---|
[240] | 1540 | break; |
---|
| 1541 | } |
---|
[434] | 1542 | } // end switch r_miss_wti_cmd_fsm |
---|
| 1543 | |
---|
| 1544 | /////////////////////////////////////////////////////////////////////////////////// |
---|
| 1545 | // The MISS_WTI_RSP FSM handles VCI responses on the Internal Network. |
---|
| 1546 | // it can be response to TLB MISS (read transaction) or WTI (write transaction). |
---|
| 1547 | // It supports several simultaneous VCI transactions. |
---|
| 1548 | //////////////////////////////////////////////////////////////////////////////////// |
---|
| 1549 | |
---|
| 1550 | switch ( r_miss_wti_rsp_fsm.read() ) |
---|
| 1551 | { |
---|
| 1552 | case MISS_WTI_RSP_IDLE: // waiting a VCI response |
---|
[240] | 1553 | { |
---|
[434] | 1554 | if ( p_vci_ini_int.rspval.read() ) |
---|
[240] | 1555 | { |
---|
[434] | 1556 | if ( p_vci_ini_int.rpktid.read() == PKTID_READ ) // it's a TLB MISS response |
---|
[240] | 1557 | { |
---|
[434] | 1558 | r_miss_wti_rsp_fsm = MISS_WTI_RSP_MISS; |
---|
| 1559 | r_miss_wti_rsp_count = 0; |
---|
[240] | 1560 | } |
---|
[434] | 1561 | else // it's a WTI WRITE response |
---|
| 1562 | { |
---|
| 1563 | r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI; |
---|
| 1564 | |
---|
| 1565 | } |
---|
[240] | 1566 | } |
---|
| 1567 | break; |
---|
| 1568 | } |
---|
[434] | 1569 | ////////////////////// |
---|
| 1570 | case MISS_WTI_RSP_WTI: // Handling response to a WTI transaction |
---|
[240] | 1571 | { |
---|
[434] | 1572 | assert( p_vci_ini_int.reop.read() and |
---|
| 1573 | "VCI_IO_BRIDGE ERROR: IRQ Write response should have one single flit" ); |
---|
[240] | 1574 | |
---|
[434] | 1575 | assert( ( (p_vci_ini_int.rerror.read()&0x1) == 0 ) and |
---|
| 1576 | "VCI_IO_BRIDGE ERROR: IRQ Write response error !!!" ); |
---|
| 1577 | // TODO traiter error using the IOMMU IRQ |
---|
| 1578 | |
---|
| 1579 | #if DEBUG_MISS_WTI |
---|
| 1580 | if( m_debug_activated ) |
---|
| 1581 | std::cout << " <IOB MISS_WTI_RSP_WTI> Response to WTI write" << std::endl; |
---|
[240] | 1582 | #endif |
---|
[434] | 1583 | r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; |
---|
[240] | 1584 | break; |
---|
| 1585 | } |
---|
[434] | 1586 | /////////////////////// |
---|
| 1587 | case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS transaction |
---|
[240] | 1588 | { |
---|
[434] | 1589 | if ( p_vci_ini_int.rspval.read() ) |
---|
[240] | 1590 | { |
---|
[434] | 1591 | if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported |
---|
[240] | 1592 | { |
---|
[434] | 1593 | r_miss_wti_rsp_error = true; |
---|
| 1594 | if ( p_vci_ini_int.reop.read() ) |
---|
[240] | 1595 | { |
---|
[434] | 1596 | r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; |
---|
| 1597 | r_tlb_miss_req = false; |
---|
[240] | 1598 | } |
---|
[434] | 1599 | #if DEBUG_MISS_WTI |
---|
| 1600 | if( m_debug_activated ) |
---|
| 1601 | std::cout << " <IOB MISS_WTI_RSP_MISS> ERROR " << std::endl; |
---|
[240] | 1602 | #endif |
---|
| 1603 | } |
---|
[434] | 1604 | else // no error |
---|
[240] | 1605 | { |
---|
[434] | 1606 | bool eop = p_vci_ini_int.reop.read(); |
---|
[240] | 1607 | |
---|
[434] | 1608 | #if DEBUG_MISS_WTI |
---|
| 1609 | if( m_debug_activated ) |
---|
| 1610 | std::cout << " <IOB MISS_WTI_RSP_MISS> Response to a tlb miss transaction" |
---|
| 1611 | << " / Count = " << r_miss_wti_rsp_count.read() |
---|
| 1612 | << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; |
---|
[240] | 1613 | #endif |
---|
[434] | 1614 | assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and |
---|
| 1615 | "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); |
---|
[240] | 1616 | |
---|
[434] | 1617 | r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); |
---|
| 1618 | r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; |
---|
[240] | 1619 | |
---|
| 1620 | if ( eop ) |
---|
| 1621 | { |
---|
[434] | 1622 | r_tlb_miss_req = false; //reset the request flip-flop |
---|
| 1623 | r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; |
---|
[240] | 1624 | } |
---|
| 1625 | } |
---|
| 1626 | } |
---|
| 1627 | break; |
---|
| 1628 | } |
---|
[434] | 1629 | } // end switch r_miss_wti_rsp_fsm |
---|
[240] | 1630 | |
---|
[434] | 1631 | ///////////////////////////////////////////////////////////////////////// |
---|
| 1632 | // This flip-flop allocates the access to the CONFIG_RSP fifo |
---|
| 1633 | // with a round robin priority between 2 clients FSMs : |
---|
| 1634 | // - CONFIG_CMD : to put a response to a local config command. |
---|
| 1635 | // - CONFIG_RSP : to put a response to a peripheral config command. |
---|
| 1636 | // The ressource is always allocated. |
---|
| 1637 | // A new allocation occurs when the owner FSM is not using it, |
---|
| 1638 | // and the other FSM is requiring it. |
---|
| 1639 | ///////////////////////////////////////////////////////////////////////// |
---|
[240] | 1640 | |
---|
[434] | 1641 | if ( r_alloc_fifo_config_rsp_local.read() ) |
---|
[240] | 1642 | { |
---|
[434] | 1643 | if ( (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and |
---|
| 1644 | (r_config_cmd_fsm.read() != CONFIG_CMD_FIFO_PUT_RSP) ) |
---|
| 1645 | r_alloc_fifo_config_rsp_local = false; |
---|
[240] | 1646 | } |
---|
[434] | 1647 | else |
---|
[240] | 1648 | { |
---|
[434] | 1649 | if ( (r_config_cmd_fsm.read() == CONFIG_CMD_FIFO_PUT_RSP) and |
---|
| 1650 | (r_config_rsp_fsm.read() != CONFIG_RSP_FIFO_PUT) ) |
---|
| 1651 | r_alloc_fifo_config_rsp_local = true; |
---|
[240] | 1652 | } |
---|
[434] | 1653 | |
---|
| 1654 | ///////////////////////////////////////////////////////////////////////// |
---|
| 1655 | // This flip-flop allocates the access to the DMA_RSP fifo |
---|
| 1656 | // with a round robin priority between 2 clients FSMs : |
---|
| 1657 | // - DMA_CMD : to put a error response in case of bad address translation |
---|
| 1658 | // - DMA_RSP : to put a normal response to a DMA transaction. |
---|
| 1659 | // The ressource is always allocated. |
---|
| 1660 | // A new allocation occurs when the owner FSM is not using it, |
---|
| 1661 | // and the other FSM is requiring it. |
---|
| 1662 | ///////////////////////////////////////////////////////////////////////// |
---|
| 1663 | |
---|
| 1664 | if ( r_alloc_fifo_dma_rsp_local.read() ) |
---|
[240] | 1665 | { |
---|
[434] | 1666 | if ( (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and |
---|
| 1667 | (r_dma_cmd_fsm.read() != DMA_CMD_FIFO_PUT_RSP) ) |
---|
| 1668 | r_alloc_fifo_dma_rsp_local = false; |
---|
[240] | 1669 | } |
---|
| 1670 | else |
---|
| 1671 | { |
---|
[434] | 1672 | if ( (r_dma_cmd_fsm.read() == DMA_CMD_FIFO_PUT_RSP) and |
---|
| 1673 | (r_dma_rsp_fsm.read() != DMA_RSP_FIFO_PUT) ) |
---|
| 1674 | r_alloc_fifo_dma_rsp_local = true; |
---|
[240] | 1675 | } |
---|
| 1676 | |
---|
[434] | 1677 | // Define GET signals for all output FIFOs |
---|
| 1678 | dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); |
---|
| 1679 | dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); |
---|
| 1680 | config_cmd_fifo_get = p_vci_ini_iox.cmdack.read(); |
---|
| 1681 | config_rsp_fifo_get = p_vci_tgt_int.rspack.read(); |
---|
| 1682 | |
---|
| 1683 | /////////////////////////////////////////////////////////// |
---|
| 1684 | // DMA_CMD fifo update |
---|
| 1685 | // One writer : DMA_CMD FSM |
---|
| 1686 | /////////////////////////////////////////////////////////// |
---|
| 1687 | |
---|
| 1688 | m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get, |
---|
| 1689 | dma_cmd_fifo_put, |
---|
| 1690 | r_dma_cmd_paddr.read() ); // address translation |
---|
| 1691 | m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get, |
---|
| 1692 | dma_cmd_fifo_put, |
---|
| 1693 | p_vci_tgt_iox.cmd.read() ); |
---|
| 1694 | m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get, |
---|
| 1695 | dma_cmd_fifo_put, |
---|
| 1696 | p_vci_tgt_iox.contig.read() ); |
---|
| 1697 | m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get, |
---|
| 1698 | dma_cmd_fifo_put, |
---|
| 1699 | p_vci_tgt_iox.cons.read() ); |
---|
| 1700 | m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get, |
---|
| 1701 | dma_cmd_fifo_put, |
---|
| 1702 | p_vci_tgt_iox.plen.read() ); |
---|
| 1703 | m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get, |
---|
| 1704 | dma_cmd_fifo_put, |
---|
| 1705 | p_vci_tgt_iox.wrap.read() ); |
---|
| 1706 | m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get, |
---|
| 1707 | dma_cmd_fifo_put, |
---|
| 1708 | p_vci_tgt_iox.cfixed.read() ); |
---|
| 1709 | m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get, |
---|
| 1710 | dma_cmd_fifo_put, |
---|
| 1711 | p_vci_tgt_iox.clen.read() ); |
---|
| 1712 | m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, |
---|
| 1713 | dma_cmd_fifo_put, |
---|
| 1714 | p_vci_tgt_iox.srcid.read() ); |
---|
| 1715 | m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, |
---|
| 1716 | dma_cmd_fifo_put, |
---|
| 1717 | p_vci_tgt_iox.trdid.read() ); |
---|
| 1718 | m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get, |
---|
| 1719 | dma_cmd_fifo_put, |
---|
| 1720 | p_vci_tgt_iox.pktid.read() ); |
---|
| 1721 | m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, |
---|
| 1722 | dma_cmd_fifo_put, |
---|
| 1723 | p_vci_tgt_iox.wdata.read() ); |
---|
| 1724 | m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, |
---|
| 1725 | dma_cmd_fifo_put, |
---|
| 1726 | p_vci_tgt_iox.be.read() ); |
---|
| 1727 | m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, |
---|
| 1728 | dma_cmd_fifo_put, |
---|
| 1729 | p_vci_tgt_iox.eop.read() ); |
---|
| 1730 | |
---|
| 1731 | ////////////////////////////////////////////////////////////// |
---|
| 1732 | // DMA_RSP fifo update |
---|
| 1733 | // Two writers : DMA_CMD FSM & DMA_RSP FSM |
---|
| 1734 | ////////////////////////////////////////////////////////////// |
---|
| 1735 | |
---|
| 1736 | if (r_alloc_fifo_dma_rsp_local.read() ) // owner is DMA_CMD FSM |
---|
| 1737 | // local response for a translation error |
---|
[240] | 1738 | { |
---|
[434] | 1739 | m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, |
---|
| 1740 | dma_rsp_fifo_put, |
---|
| 1741 | 0 ); // no data if error |
---|
[240] | 1742 | m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1743 | dma_rsp_fifo_put, |
---|
| 1744 | p_vci_tgt_iox.rsrcid.read() ); |
---|
[240] | 1745 | m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1746 | dma_rsp_fifo_put, |
---|
| 1747 | p_vci_tgt_iox.rtrdid.read() ); |
---|
[240] | 1748 | m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1749 | dma_rsp_fifo_put, |
---|
| 1750 | p_vci_tgt_iox.rpktid.read() ); |
---|
| 1751 | m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, |
---|
| 1752 | dma_rsp_fifo_put, |
---|
| 1753 | true ); // single flit response |
---|
[240] | 1754 | m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, |
---|
| 1755 | dma_rsp_fifo_put, |
---|
[434] | 1756 | 1 ); // error |
---|
[240] | 1757 | } |
---|
[434] | 1758 | else // owner is DMA_RSP FSM |
---|
| 1759 | // normal response to a DMA transaction |
---|
[240] | 1760 | { |
---|
[434] | 1761 | m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, |
---|
| 1762 | dma_rsp_fifo_put, |
---|
| 1763 | p_vci_ini_ram.rdata.read() ); |
---|
[240] | 1764 | m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1765 | dma_rsp_fifo_put, |
---|
| 1766 | p_vci_ini_ram.rsrcid.read() ); |
---|
[240] | 1767 | m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1768 | dma_rsp_fifo_put, |
---|
| 1769 | p_vci_ini_ram.rtrdid.read() ); |
---|
[240] | 1770 | m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, |
---|
[434] | 1771 | dma_rsp_fifo_put, |
---|
| 1772 | p_vci_ini_ram.rpktid.read() ); |
---|
| 1773 | m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, |
---|
| 1774 | dma_rsp_fifo_put, |
---|
| 1775 | p_vci_ini_ram.reop.read() ); |
---|
[240] | 1776 | m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, |
---|
| 1777 | dma_rsp_fifo_put, |
---|
[434] | 1778 | p_vci_ini_ram.rerror.read() ); |
---|
[240] | 1779 | } |
---|
| 1780 | |
---|
[434] | 1781 | //////////////////////////////////////////////////////////////// |
---|
| 1782 | // CONFIG_CMD fifo update |
---|
| 1783 | // One writer : CONFIG_CMD FSM |
---|
| 1784 | //////////////////////////////////////////////////////////////// |
---|
| 1785 | |
---|
| 1786 | m_config_cmd_addr_fifo.update( config_cmd_fifo_get, |
---|
| 1787 | config_cmd_fifo_put, |
---|
| 1788 | p_vci_tgt_int.address.read() ); |
---|
| 1789 | m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, |
---|
| 1790 | config_cmd_fifo_put, |
---|
| 1791 | p_vci_tgt_int.cmd.read() ); |
---|
[240] | 1792 | m_config_cmd_contig_fifo.update( config_cmd_fifo_get, |
---|
[434] | 1793 | config_cmd_fifo_put, |
---|
| 1794 | p_vci_tgt_int.contig.read() ); |
---|
| 1795 | m_config_cmd_cons_fifo.update( config_cmd_fifo_get, |
---|
| 1796 | config_cmd_fifo_put, |
---|
| 1797 | p_vci_tgt_int.cons.read() ); |
---|
| 1798 | m_config_cmd_plen_fifo.update( config_cmd_fifo_get, |
---|
| 1799 | config_cmd_fifo_put, |
---|
| 1800 | p_vci_tgt_int.plen.read() ); |
---|
| 1801 | m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, |
---|
| 1802 | config_cmd_fifo_put, |
---|
| 1803 | p_vci_tgt_int.wrap.read() ); |
---|
[240] | 1804 | m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, |
---|
[434] | 1805 | config_cmd_fifo_put, |
---|
| 1806 | p_vci_tgt_int.cfixed.read() ); |
---|
| 1807 | m_config_cmd_clen_fifo.update( config_cmd_fifo_get, |
---|
| 1808 | config_cmd_fifo_put, |
---|
| 1809 | p_vci_tgt_int.clen.read() ); |
---|
| 1810 | m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, |
---|
| 1811 | config_cmd_fifo_put, |
---|
| 1812 | p_vci_tgt_int.srcid.read() ); |
---|
| 1813 | m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, |
---|
| 1814 | config_cmd_fifo_put, |
---|
| 1815 | p_vci_tgt_int.trdid.read() ); |
---|
| 1816 | m_config_cmd_pktid_fifo.update( config_cmd_fifo_get, |
---|
| 1817 | config_cmd_fifo_put, |
---|
| 1818 | p_vci_tgt_int.pktid.read() ); |
---|
| 1819 | m_config_cmd_data_fifo.update( config_cmd_fifo_get, |
---|
| 1820 | config_cmd_fifo_put, |
---|
| 1821 | (ext_data_t)p_vci_tgt_int.wdata.read() ); |
---|
| 1822 | m_config_cmd_be_fifo.update( config_cmd_fifo_get, |
---|
| 1823 | config_cmd_fifo_put, |
---|
| 1824 | p_vci_tgt_int.be.read() ); |
---|
| 1825 | m_config_cmd_eop_fifo.update( config_cmd_fifo_get, |
---|
| 1826 | config_cmd_fifo_put, |
---|
| 1827 | p_vci_tgt_int.eop.read() ); |
---|
[240] | 1828 | |
---|
[434] | 1829 | ////////////////////////////////////////////////////////////////////////// |
---|
| 1830 | // CONFIG_RSP fifo update |
---|
| 1831 | // There is two writers : CONFIG_CMD FSM & CONFIG_RSP FSM |
---|
| 1832 | ////////////////////////////////////////////////////////////////////////// |
---|
| 1833 | |
---|
| 1834 | if ( r_alloc_fifo_config_rsp_local.read() ) // owner is CONFIG_CMD FSM |
---|
| 1835 | // response for a local config transaction |
---|
[240] | 1836 | { |
---|
[434] | 1837 | m_config_rsp_data_fifo.update( config_rsp_fifo_get, |
---|
| 1838 | config_rsp_fifo_put, |
---|
| 1839 | (int_data_t)r_config_cmd_rdata.read() ); |
---|
| 1840 | m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, |
---|
| 1841 | config_rsp_fifo_put, |
---|
| 1842 | p_vci_tgt_int.srcid.read() ); |
---|
| 1843 | m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, |
---|
| 1844 | config_rsp_fifo_put, |
---|
| 1845 | p_vci_tgt_int.trdid.read() ); |
---|
| 1846 | m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, |
---|
| 1847 | config_rsp_fifo_put, |
---|
| 1848 | p_vci_tgt_int.pktid.read() ); |
---|
| 1849 | m_config_rsp_reop_fifo.update( config_rsp_fifo_get, |
---|
| 1850 | config_rsp_fifo_put, |
---|
| 1851 | true ); // local config are one flit |
---|
| 1852 | m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, |
---|
| 1853 | config_rsp_fifo_put, |
---|
| 1854 | r_config_cmd_error.read() ); |
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[240] | 1855 | } |
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[434] | 1856 | else // owner is CONFIG_RSP FSM |
---|
| 1857 | // response for a remote transaction |
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| 1858 | { |
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| 1859 | m_config_rsp_data_fifo.update( config_rsp_fifo_get, |
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| 1860 | config_rsp_fifo_put, |
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| 1861 | (int_data_t)p_vci_ini_iox.rdata.read() ); |
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| 1862 | m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, |
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| 1863 | config_rsp_fifo_put, |
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| 1864 | p_vci_ini_iox.rsrcid.read() ); |
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| 1865 | m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, |
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| 1866 | config_rsp_fifo_put, |
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| 1867 | p_vci_ini_iox.rtrdid.read() ); |
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| 1868 | m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, |
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| 1869 | config_rsp_fifo_put, |
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| 1870 | p_vci_ini_iox.rpktid.read() ); |
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| 1871 | m_config_rsp_reop_fifo.update( config_rsp_fifo_get, |
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| 1872 | config_rsp_fifo_put, |
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| 1873 | p_vci_ini_iox.reop.read() ); |
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| 1874 | m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, |
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| 1875 | config_rsp_fifo_put, |
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| 1876 | p_vci_ini_iox.rerror.read() ); |
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| 1877 | } |
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| 1878 | |
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[240] | 1879 | } // end transition() |
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| 1880 | |
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| 1881 | /////////////////////// |
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| 1882 | tmpl(void)::genMoore() |
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| 1883 | /////////////////////// |
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| 1884 | { |
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[434] | 1885 | // VCI initiator command on RAM network |
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| 1886 | // directly the content of the dma_cmd FIFO |
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| 1887 | |
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| 1888 | p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); |
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| 1889 | p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); |
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| 1890 | p_vci_ini_ram.be = m_dma_cmd_be_fifo.read(); |
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| 1891 | p_vci_ini_ram.cmd = m_dma_cmd_cmd_fifo.read(); |
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| 1892 | p_vci_ini_ram.contig = m_dma_cmd_contig_fifo.read(); |
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| 1893 | p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); |
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| 1894 | p_vci_ini_ram.eop = m_dma_cmd_eop_fifo.read(); |
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| 1895 | p_vci_ini_ram.cons = m_dma_cmd_cons_fifo.read(); |
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| 1896 | p_vci_ini_ram.plen = m_dma_cmd_plen_fifo.read(); |
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| 1897 | p_vci_ini_ram.wrap = m_dma_cmd_wrap_fifo.read(); |
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| 1898 | p_vci_ini_ram.cfixed = m_dma_cmd_cfixed_fifo.read(); |
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| 1899 | p_vci_ini_ram.clen = m_dma_cmd_clen_fifo.read(); |
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| 1900 | p_vci_ini_ram.trdid = m_dma_cmd_trdid_fifo.read(); |
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| 1901 | p_vci_ini_ram.pktid = m_dma_cmd_pktid_fifo.read(); |
---|
| 1902 | p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); |
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[240] | 1903 | |
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[434] | 1904 | // VCI target command ack on IOX network |
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| 1905 | // depends on the DMA_CMD FSM state |
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[240] | 1906 | |
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| 1907 | switch ( r_dma_cmd_fsm.read() ) |
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| 1908 | { |
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| 1909 | case DMA_CMD_IDLE: |
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[434] | 1910 | case DMA_CMD_MISS_WAIT: |
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| 1911 | p_vci_tgt_iox.cmdack = false; |
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[240] | 1912 | break; |
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[434] | 1913 | case DMA_CMD_WAIT_EOP: |
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| 1914 | p_vci_tgt_iox.cmdack = true; |
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[240] | 1915 | break; |
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[434] | 1916 | case DMA_CMD_FIFO_PUT_CMD: |
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| 1917 | p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); |
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[240] | 1918 | break; |
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[434] | 1919 | case DMA_CMD_FIFO_PUT_RSP: |
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| 1920 | p_vci_tgt_iox.cmdack = m_dma_rsp_data_fifo.wok(); |
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[240] | 1921 | break; |
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| 1922 | }// end switch r_dma_cmd_fsm |
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| 1923 | |
---|
[434] | 1924 | // VCI target response on IOX network |
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| 1925 | // directly the content of the DMA_RSP FIFO |
---|
[240] | 1926 | |
---|
[434] | 1927 | p_vci_tgt_iox.rspval = m_dma_rsp_data_fifo.rok(); |
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| 1928 | p_vci_tgt_iox.rsrcid = m_dma_rsp_rsrcid_fifo.read(); |
---|
| 1929 | p_vci_tgt_iox.rtrdid = m_dma_rsp_rtrdid_fifo.read(); |
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| 1930 | p_vci_tgt_iox.rpktid = m_dma_rsp_rpktid_fifo.read(); |
---|
| 1931 | p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); |
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| 1932 | p_vci_tgt_iox.rerror = m_dma_rsp_rerror_fifo.read(); |
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| 1933 | p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); |
---|
[240] | 1934 | |
---|
[434] | 1935 | // VCI initiator response on the RAM Network |
---|
| 1936 | // depends on the DMA_RSP FSM state |
---|
[240] | 1937 | |
---|
[434] | 1938 | p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and |
---|
| 1939 | (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and |
---|
| 1940 | not r_alloc_fifo_dma_rsp_local.read(); |
---|
[240] | 1941 | |
---|
[434] | 1942 | // VCI initiator command on IOX network |
---|
| 1943 | // directly the content of the CONFIG_CMD FIFO |
---|
| 1944 | |
---|
| 1945 | p_vci_ini_iox.cmdval = m_config_cmd_addr_fifo.rok(); |
---|
| 1946 | p_vci_ini_iox.address = m_config_cmd_addr_fifo.read(); |
---|
| 1947 | p_vci_ini_iox.be = m_config_cmd_be_fifo.read(); |
---|
| 1948 | p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); |
---|
| 1949 | p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); |
---|
| 1950 | p_vci_ini_iox.wdata = (ext_data_t)m_config_cmd_data_fifo.read(); |
---|
| 1951 | p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); |
---|
| 1952 | p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); |
---|
| 1953 | p_vci_ini_iox.plen = m_config_cmd_plen_fifo.read(); |
---|
| 1954 | p_vci_ini_iox.wrap = m_config_cmd_wrap_fifo.read(); |
---|
| 1955 | p_vci_ini_iox.cfixed = m_config_cmd_cfixed_fifo.read(); |
---|
| 1956 | p_vci_ini_iox.clen = m_config_cmd_clen_fifo.read(); |
---|
| 1957 | p_vci_ini_iox.trdid = m_config_cmd_trdid_fifo.read(); |
---|
| 1958 | p_vci_ini_iox.pktid = m_config_cmd_pktid_fifo.read(); |
---|
| 1959 | p_vci_ini_iox.srcid = m_config_cmd_srcid_fifo.read(); |
---|
[240] | 1960 | |
---|
[434] | 1961 | // VCI target command ack on INT network |
---|
[240] | 1962 | // it depends on the CONFIG_CMD FSM state |
---|
| 1963 | |
---|
| 1964 | switch ( r_config_cmd_fsm.read() ) |
---|
| 1965 | { |
---|
| 1966 | case CONFIG_CMD_IDLE: |
---|
[434] | 1967 | p_vci_tgt_int.cmdack = false; |
---|
[240] | 1968 | break; |
---|
[434] | 1969 | case CONFIG_CMD_FIFO_PUT_CMD: |
---|
| 1970 | p_vci_tgt_int.cmdack = m_config_cmd_addr_fifo.wok(); |
---|
[240] | 1971 | break; |
---|
[434] | 1972 | case CONFIG_CMD_FIFO_PUT_RSP: |
---|
| 1973 | p_vci_tgt_int.cmdack = m_config_rsp_data_fifo.wok() and |
---|
| 1974 | r_alloc_fifo_config_rsp_local.read(); |
---|
[240] | 1975 | break; |
---|
| 1976 | }// end switch r_config_cmd_fsm |
---|
| 1977 | |
---|
[434] | 1978 | // VCI target response on INT network |
---|
| 1979 | // directly the content of the CONFIG_RSP FIFO |
---|
[240] | 1980 | |
---|
[434] | 1981 | p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); |
---|
| 1982 | p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); |
---|
| 1983 | p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); |
---|
| 1984 | p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); |
---|
| 1985 | p_vci_tgt_int.rdata = m_config_rsp_data_fifo.read(); |
---|
| 1986 | p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); |
---|
| 1987 | p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); |
---|
[240] | 1988 | |
---|
[434] | 1989 | // VCI initiator response on IOX Network |
---|
[240] | 1990 | // it depends on the CONFIG_RSP FSM state |
---|
| 1991 | |
---|
[434] | 1992 | p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and |
---|
| 1993 | (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and |
---|
| 1994 | not r_alloc_fifo_config_rsp_local.read(); |
---|
| 1995 | |
---|
| 1996 | // VCI initiator command on INT network |
---|
[549] | 1997 | // it depends on the MISS_WTI_CMD FSM state |
---|
| 1998 | // - WTI : single flit WRITE |
---|
| 1999 | // - MISS TLB : multi-flit READ for a complete cache line |
---|
[434] | 2000 | |
---|
| 2001 | // default values |
---|
| 2002 | p_vci_ini_int.srcid = m_int_srcid; |
---|
| 2003 | p_vci_ini_int.trdid = 0; |
---|
| 2004 | p_vci_ini_int.cfixed = false; |
---|
| 2005 | p_vci_ini_int.eop = true; |
---|
| 2006 | p_vci_ini_int.wrap = false; |
---|
| 2007 | p_vci_ini_int.clen = 0; |
---|
[549] | 2008 | p_vci_ini_int.contig = true; |
---|
| 2009 | p_vci_ini_int.cons = false; |
---|
| 2010 | p_vci_ini_int.be = 0xF; |
---|
[240] | 2011 | |
---|
[434] | 2012 | switch ( r_miss_wti_cmd_fsm.read() ) |
---|
[240] | 2013 | { |
---|
[434] | 2014 | case MISS_WTI_CMD_IDLE: |
---|
| 2015 | p_vci_ini_int.cmdval = false; |
---|
| 2016 | p_vci_ini_int.address = 0; |
---|
| 2017 | p_vci_ini_int.cmd = vci_param_int::CMD_NOP; |
---|
| 2018 | p_vci_ini_int.pktid = PKTID_READ; |
---|
| 2019 | p_vci_ini_int.wdata = 0; |
---|
| 2020 | p_vci_ini_int.plen = 0; |
---|
[240] | 2021 | break; |
---|
| 2022 | |
---|
[434] | 2023 | case MISS_WTI_CMD_WTI: |
---|
| 2024 | p_vci_ini_int.cmdval = true; |
---|
| 2025 | p_vci_ini_int.address = r_iommu_peri_wti[r_miss_wti_cmd_index.read()].read(); |
---|
| 2026 | p_vci_ini_int.cmd = vci_param_int::CMD_WRITE; |
---|
| 2027 | p_vci_ini_int.pktid = PKTID_WRITE; |
---|
| 2028 | p_vci_ini_int.wdata = (int_data_t)r_irq_pending[r_miss_wti_cmd_index.read()].read(); |
---|
| 2029 | p_vci_ini_int.plen = vci_param_int::B; |
---|
[240] | 2030 | break; |
---|
| 2031 | |
---|
[434] | 2032 | case MISS_WTI_CMD_MISS: |
---|
| 2033 | p_vci_ini_int.cmdval = true; |
---|
| 2034 | p_vci_ini_int.address = r_tlb_paddr.read() & CACHE_LINE_MASK; |
---|
| 2035 | p_vci_ini_int.cmd = vci_param_int::CMD_READ; |
---|
| 2036 | p_vci_ini_int.pktid = PKTID_READ; |
---|
| 2037 | p_vci_ini_int.wdata = 0; |
---|
| 2038 | p_vci_ini_int.plen = m_words*(vci_param_int::B); |
---|
[240] | 2039 | break; |
---|
[434] | 2040 | } |
---|
[240] | 2041 | |
---|
[434] | 2042 | // VCI initiator response on INT network |
---|
| 2043 | // It depends on the MISS_WTI_RSP FSM state |
---|
| 2044 | |
---|
| 2045 | if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_IDLE ) p_vci_ini_int.rspack = false; |
---|
| 2046 | else p_vci_ini_int.rspack = true; |
---|
| 2047 | |
---|
[240] | 2048 | } // end genMoore |
---|
| 2049 | |
---|
| 2050 | }} |
---|
| 2051 | |
---|
| 2052 | // Local Variables: |
---|
| 2053 | // tab-width: 4 |
---|
| 2054 | // c-basic-offset: 4 |
---|
| 2055 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 2056 | // indent-tabs-mode: nil |
---|
| 2057 | // End: |
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| 2058 | |
---|
| 2059 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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