| 1 | /* | 
|---|
| 2 |  * SOCLIB_LGPL_HEADER_BEGIN | 
|---|
| 3 |  *  | 
|---|
| 4 |  * This file is part of SoCLib, GNU LGPLv2.1. | 
|---|
| 5 |  *  | 
|---|
| 6 |  * SoCLib is free software; you can redistribute it and/or modify it | 
|---|
| 7 |  * under the terms of the GNU Lesser General Public License as published | 
|---|
| 8 |  * by the Free Software Foundation; version 2.1 of the License. | 
|---|
| 9 |  *  | 
|---|
| 10 |  * SoCLib is distributed in the hope that it will be useful, but | 
|---|
| 11 |  * WITHOUT ANY WARRANTY; without even the implied warranty of | 
|---|
| 12 |  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU | 
|---|
| 13 |  * Lesser General Public License for more details. | 
|---|
| 14 |  *  | 
|---|
| 15 |  * You should have received a copy of the GNU Lesser General Public | 
|---|
| 16 |  * License along with SoCLib; if not, write to the Free Software | 
|---|
| 17 |  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | 
|---|
| 18 |  * 02110-1301 USA | 
|---|
| 19 |  *  | 
|---|
| 20 |  * SOCLIB_LGPL_HEADER_END | 
|---|
| 21 |  * | 
|---|
| 22 |  * Copyright (c) UPMC, Lip6, Asim | 
|---|
| 23 |  *         alain greiner | 
|---|
| 24 |  * | 
|---|
| 25 |  * Maintainers: alain | 
|---|
| 26 |  */ | 
|---|
| 27 | #ifndef IO_BRIDGE_REGS_H | 
|---|
| 28 | #define IO_BRIDGE_REGS_H | 
|---|
| 29 |  | 
|---|
| 30 | // IOB Configuration registers | 
|---|
| 31 | // Minimal required segment size = 64 bytes (16 words) | 
|---|
| 32 | enum  | 
|---|
| 33 | { | 
|---|
| 34 |     IOB_IOMMU_PTPR       = 0,     // R/W  : Page Table Pointer Register | 
|---|
| 35 |     IOB_IOMMU_ACTIVE     = 1,     // R/W  : IOMMU activated if not 0 | 
|---|
| 36 |     IOB_IOMMU_BVAR       = 2,     // R    : Bad Virtual Address | 
|---|
| 37 |     IOB_IOMMU_ETR        = 3,     // R    : Error type | 
|---|
| 38 |     IOB_IOMMU_BAD_ID     = 4,     // R    : Faulty peripheral Index (SRCID) | 
|---|
| 39 |     IOB_INVAL_PTE        = 5,     // W    : Invalidate PTE (using virtual address) | 
|---|
| 40 |     IOB_WTI_ENABLE       = 6,     // R/W  : Enable WTI (both IOB and external IRQs) | 
|---|
| 41 |     IOB_WTI_ADDR_LO      = 7,     // R/W  : IOB WTI address (32 LSB bits) | 
|---|
| 42 |     IOB_WTI_ADDR_HI      = 8,     // R/W  : IOB WTI address (32 MSB bits) | 
|---|
| 43 |     /**/ | 
|---|
| 44 |     IOB_SPAN             = 16,                                 | 
|---|
| 45 | }; | 
|---|
| 46 |  | 
|---|
| 47 |      | 
|---|
| 48 | // IOMMU Error Type | 
|---|
| 49 | enum mmu_error_type_e  | 
|---|
| 50 | { | 
|---|
| 51 |     MMU_NONE                      = 0x0000, // None | 
|---|
| 52 |     MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access to non writable page  | 
|---|
| 53 |     MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write Bus Error accessing Table 1 | 
|---|
| 54 |     MMU_READ_PT1_UNMAPPED             = 0x1001, // Read  Page fault on Page Table 1  | 
|---|
| 55 |     MMU_READ_PT2_UNMAPPED             = 0x1002, // Read  Page fault on Page Table 2  | 
|---|
| 56 |     MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read  Bus Error in Table1 access  | 
|---|
| 57 |     MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read  Bus Error in Table2 access | 
|---|
| 58 |     MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read  Bus Error in cache access  | 
|---|
| 59 | }; | 
|---|
| 60 |  | 
|---|
| 61 | #endif /* IO_BRIDGE_REGS_H */ | 
|---|
| 62 |  | 
|---|
| 63 | // Local Variables: | 
|---|
| 64 | // tab-width: 4 | 
|---|
| 65 | // c-basic-offset: 4 | 
|---|
| 66 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) | 
|---|
| 67 | // indent-tabs-mode: nil | 
|---|
| 68 | // End: | 
|---|
| 69 |  | 
|---|
| 70 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 | 
|---|
| 71 |  | 
|---|