[331] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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| 28 | * cesar.fuguet-tortolero@lip6.fr |
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| 29 | * alexandre.joannou@lip6.fr |
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| 30 | */ |
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| 31 | |
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| 32 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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| 33 | #define SOCLIB_CABA_MEM_CACHE_H |
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| 34 | |
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| 35 | #include <inttypes.h> |
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| 36 | #include <systemc> |
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| 37 | #include <list> |
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| 38 | #include <cassert> |
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| 39 | #include "arithmetics.h" |
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| 40 | #include "alloc_elems.h" |
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| 41 | #include "caba_base_module.h" |
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| 42 | #include "vci_target.h" |
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| 43 | #include "vci_initiator.h" |
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| 44 | #include "generic_fifo.h" |
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| 45 | #include "mapping_table.h" |
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| 46 | #include "int_tab.h" |
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| 47 | #include "generic_llsc_global_table.h" |
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| 48 | #include "mem_cache_directory.h" |
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| 49 | #include "xram_transaction.h" |
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| 50 | #include "update_tab.h" |
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| 51 | #include "dspin_interface.h" |
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| 52 | #include "dspin_dhccp_param.h" |
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| 53 | |
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[395] | 54 | #define TRT_ENTRIES 4 // Number of entries in TRT |
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| 55 | #define UPT_ENTRIES 4 // Number of entries in UPT |
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| 56 | #define HEAP_ENTRIES 1024 // Number of entries in HEAP |
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[331] | 57 | |
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| 58 | namespace soclib { namespace caba { |
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[395] | 59 | |
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[331] | 60 | using namespace sc_core; |
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| 61 | |
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[385] | 62 | template<typename vci_param_int, |
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| 63 | typename vci_param_ext, |
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| 64 | size_t dspin_in_width, |
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| 65 | size_t dspin_out_width> |
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[331] | 66 | class VciMemCache |
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| 67 | : public soclib::caba::BaseModule |
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| 68 | { |
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[385] | 69 | typedef typename vci_param_int::fast_addr_t addr_t; |
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| 70 | typedef typename sc_dt::sc_uint<64> wide_data_t; |
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[449] | 71 | typedef uint32_t data_t; |
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| 72 | typedef uint32_t tag_t; |
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| 73 | typedef uint32_t be_t; |
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| 74 | typedef uint32_t copy_t; |
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[385] | 75 | |
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[331] | 76 | /* States of the TGT_CMD fsm */ |
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[434] | 77 | enum tgt_cmd_fsm_state_e |
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| 78 | { |
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[331] | 79 | TGT_CMD_IDLE, |
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[430] | 80 | TGT_CMD_ERROR, |
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[331] | 81 | TGT_CMD_READ, |
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| 82 | TGT_CMD_WRITE, |
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[434] | 83 | TGT_CMD_CAS, |
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| 84 | TGT_CMD_CONFIG |
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[331] | 85 | }; |
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| 86 | |
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| 87 | /* States of the TGT_RSP fsm */ |
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[395] | 88 | enum tgt_rsp_fsm_state_e |
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| 89 | { |
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[439] | 90 | TGT_RSP_CONFIG_IDLE, |
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[430] | 91 | TGT_RSP_TGT_CMD_IDLE, |
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[331] | 92 | TGT_RSP_READ_IDLE, |
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| 93 | TGT_RSP_WRITE_IDLE, |
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| 94 | TGT_RSP_CAS_IDLE, |
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| 95 | TGT_RSP_XRAM_IDLE, |
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[430] | 96 | TGT_RSP_MULTI_ACK_IDLE, |
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[331] | 97 | TGT_RSP_CLEANUP_IDLE, |
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[439] | 98 | TGT_RSP_CONFIG, |
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[430] | 99 | TGT_RSP_TGT_CMD, |
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[331] | 100 | TGT_RSP_READ, |
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| 101 | TGT_RSP_WRITE, |
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| 102 | TGT_RSP_CAS, |
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| 103 | TGT_RSP_XRAM, |
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[430] | 104 | TGT_RSP_MULTI_ACK, |
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[331] | 105 | TGT_RSP_CLEANUP |
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| 106 | }; |
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| 107 | |
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| 108 | /* States of the DSPIN_TGT fsm */ |
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[395] | 109 | enum cc_receive_fsm_state_e |
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| 110 | { |
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[331] | 111 | CC_RECEIVE_IDLE, |
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| 112 | CC_RECEIVE_CLEANUP, |
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[403] | 113 | CC_RECEIVE_CLEANUP_EOP, |
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[331] | 114 | CC_RECEIVE_MULTI_ACK |
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| 115 | }; |
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| 116 | |
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| 117 | /* States of the CC_SEND fsm */ |
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[395] | 118 | enum cc_send_fsm_state_e |
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| 119 | { |
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[439] | 120 | CC_SEND_CONFIG_IDLE, |
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[331] | 121 | CC_SEND_XRAM_RSP_IDLE, |
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| 122 | CC_SEND_WRITE_IDLE, |
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| 123 | CC_SEND_CAS_IDLE, |
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| 124 | CC_SEND_CLEANUP_IDLE, |
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[439] | 125 | CC_SEND_CONFIG_INVAL_HEADER, |
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| 126 | CC_SEND_CONFIG_INVAL_NLINE, |
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| 127 | CC_SEND_CONFIG_BRDCAST_HEADER, |
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| 128 | CC_SEND_CONFIG_BRDCAST_NLINE, |
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[331] | 129 | CC_SEND_CLEANUP_ACK, |
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| 130 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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| 131 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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| 132 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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| 133 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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| 134 | CC_SEND_WRITE_BRDCAST_HEADER, |
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| 135 | CC_SEND_WRITE_BRDCAST_NLINE, |
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| 136 | CC_SEND_WRITE_UPDT_HEADER, |
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| 137 | CC_SEND_WRITE_UPDT_NLINE, |
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| 138 | CC_SEND_WRITE_UPDT_DATA, |
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| 139 | CC_SEND_CAS_BRDCAST_HEADER, |
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| 140 | CC_SEND_CAS_BRDCAST_NLINE, |
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| 141 | CC_SEND_CAS_UPDT_HEADER, |
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| 142 | CC_SEND_CAS_UPDT_NLINE, |
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| 143 | CC_SEND_CAS_UPDT_DATA, |
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| 144 | CC_SEND_CAS_UPDT_DATA_HIGH |
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| 145 | }; |
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| 146 | |
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| 147 | /* States of the MULTI_ACK fsm */ |
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[395] | 148 | enum multi_ack_fsm_state_e |
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| 149 | { |
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[331] | 150 | MULTI_ACK_IDLE, |
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| 151 | MULTI_ACK_UPT_LOCK, |
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| 152 | MULTI_ACK_UPT_CLEAR, |
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[434] | 153 | MULTI_ACK_WRITE_RSP, |
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| 154 | MULTI_ACK_CONFIG_ACK |
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[331] | 155 | }; |
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| 156 | |
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[434] | 157 | /* States of the CONFIG fsm */ |
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| 158 | enum config_fsm_state_e |
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| 159 | { |
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| 160 | CONFIG_IDLE, |
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| 161 | CONFIG_LOOP, |
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| 162 | CONFIG_RSP, |
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| 163 | CONFIG_DIR_REQ, |
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| 164 | CONFIG_DIR_ACCESS, |
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[439] | 165 | CONFIG_DIR_UPT_LOCK, |
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[434] | 166 | CONFIG_BC_SEND, |
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| 167 | CONFIG_BC_WAIT, |
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[439] | 168 | CONFIG_INV_SEND, |
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| 169 | CONFIG_HEAP_REQ, |
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| 170 | CONFIG_HEAP_SCAN, |
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| 171 | CONFIG_HEAP_LAST, |
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| 172 | CONFIG_INV_WAIT |
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[434] | 173 | }; |
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| 174 | |
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[331] | 175 | /* States of the READ fsm */ |
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[395] | 176 | enum read_fsm_state_e |
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| 177 | { |
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[331] | 178 | READ_IDLE, |
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| 179 | READ_DIR_REQ, |
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| 180 | READ_DIR_LOCK, |
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| 181 | READ_DIR_HIT, |
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| 182 | READ_HEAP_REQ, |
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| 183 | READ_HEAP_LOCK, |
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| 184 | READ_HEAP_WRITE, |
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| 185 | READ_HEAP_ERASE, |
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| 186 | READ_HEAP_LAST, |
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| 187 | READ_RSP, |
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| 188 | READ_TRT_LOCK, |
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| 189 | READ_TRT_SET, |
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| 190 | READ_TRT_REQ |
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| 191 | }; |
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| 192 | |
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| 193 | /* States of the WRITE fsm */ |
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[395] | 194 | enum write_fsm_state_e |
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| 195 | { |
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[331] | 196 | WRITE_IDLE, |
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| 197 | WRITE_NEXT, |
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| 198 | WRITE_DIR_REQ, |
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| 199 | WRITE_DIR_LOCK, |
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| 200 | WRITE_DIR_READ, |
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| 201 | WRITE_DIR_HIT, |
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| 202 | WRITE_UPT_LOCK, |
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| 203 | WRITE_UPT_HEAP_LOCK, |
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| 204 | WRITE_UPT_REQ, |
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| 205 | WRITE_UPT_NEXT, |
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| 206 | WRITE_UPT_DEC, |
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| 207 | WRITE_RSP, |
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| 208 | WRITE_MISS_TRT_LOCK, |
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| 209 | WRITE_MISS_TRT_DATA, |
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| 210 | WRITE_MISS_TRT_SET, |
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| 211 | WRITE_MISS_XRAM_REQ, |
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| 212 | WRITE_BC_TRT_LOCK, |
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| 213 | WRITE_BC_UPT_LOCK, |
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| 214 | WRITE_BC_DIR_INVAL, |
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| 215 | WRITE_BC_CC_SEND, |
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| 216 | WRITE_BC_XRAM_REQ, |
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| 217 | WRITE_WAIT |
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| 218 | }; |
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| 219 | |
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| 220 | /* States of the IXR_RSP fsm */ |
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[395] | 221 | enum ixr_rsp_fsm_state_e |
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| 222 | { |
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[331] | 223 | IXR_RSP_IDLE, |
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| 224 | IXR_RSP_ACK, |
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| 225 | IXR_RSP_TRT_ERASE, |
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| 226 | IXR_RSP_TRT_READ |
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| 227 | }; |
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| 228 | |
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| 229 | /* States of the XRAM_RSP fsm */ |
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[395] | 230 | enum xram_rsp_fsm_state_e |
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| 231 | { |
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[331] | 232 | XRAM_RSP_IDLE, |
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| 233 | XRAM_RSP_TRT_COPY, |
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| 234 | XRAM_RSP_TRT_DIRTY, |
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| 235 | XRAM_RSP_DIR_LOCK, |
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| 236 | XRAM_RSP_DIR_UPDT, |
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| 237 | XRAM_RSP_DIR_RSP, |
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| 238 | XRAM_RSP_INVAL_LOCK, |
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| 239 | XRAM_RSP_INVAL_WAIT, |
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| 240 | XRAM_RSP_INVAL, |
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| 241 | XRAM_RSP_WRITE_DIRTY, |
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| 242 | XRAM_RSP_HEAP_REQ, |
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| 243 | XRAM_RSP_HEAP_ERASE, |
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| 244 | XRAM_RSP_HEAP_LAST, |
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| 245 | XRAM_RSP_ERROR_ERASE, |
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| 246 | XRAM_RSP_ERROR_RSP |
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| 247 | }; |
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| 248 | |
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| 249 | /* States of the IXR_CMD fsm */ |
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[395] | 250 | enum ixr_cmd_fsm_state_e |
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| 251 | { |
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[331] | 252 | IXR_CMD_READ_IDLE, |
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| 253 | IXR_CMD_WRITE_IDLE, |
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| 254 | IXR_CMD_CAS_IDLE, |
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| 255 | IXR_CMD_XRAM_IDLE, |
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[395] | 256 | IXR_CMD_READ, |
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| 257 | IXR_CMD_WRITE, |
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| 258 | IXR_CMD_CAS, |
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| 259 | IXR_CMD_XRAM |
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[331] | 260 | }; |
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| 261 | |
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| 262 | /* States of the CAS fsm */ |
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[395] | 263 | enum cas_fsm_state_e |
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| 264 | { |
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[331] | 265 | CAS_IDLE, |
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| 266 | CAS_DIR_REQ, |
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| 267 | CAS_DIR_LOCK, |
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| 268 | CAS_DIR_HIT_READ, |
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| 269 | CAS_DIR_HIT_COMPARE, |
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| 270 | CAS_DIR_HIT_WRITE, |
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| 271 | CAS_UPT_LOCK, |
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| 272 | CAS_UPT_HEAP_LOCK, |
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| 273 | CAS_UPT_REQ, |
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| 274 | CAS_UPT_NEXT, |
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| 275 | CAS_BC_TRT_LOCK, |
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| 276 | CAS_BC_UPT_LOCK, |
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| 277 | CAS_BC_DIR_INVAL, |
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| 278 | CAS_BC_CC_SEND, |
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| 279 | CAS_BC_XRAM_REQ, |
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| 280 | CAS_RSP_FAIL, |
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| 281 | CAS_RSP_SUCCESS, |
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| 282 | CAS_MISS_TRT_LOCK, |
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| 283 | CAS_MISS_TRT_SET, |
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| 284 | CAS_MISS_XRAM_REQ, |
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| 285 | CAS_WAIT |
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| 286 | }; |
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| 287 | |
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| 288 | /* States of the CLEANUP fsm */ |
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[395] | 289 | enum cleanup_fsm_state_e |
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| 290 | { |
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[331] | 291 | CLEANUP_IDLE, |
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| 292 | CLEANUP_GET_NLINE, |
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| 293 | CLEANUP_DIR_REQ, |
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| 294 | CLEANUP_DIR_LOCK, |
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| 295 | CLEANUP_DIR_WRITE, |
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| 296 | CLEANUP_HEAP_REQ, |
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| 297 | CLEANUP_HEAP_LOCK, |
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| 298 | CLEANUP_HEAP_SEARCH, |
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| 299 | CLEANUP_HEAP_CLEAN, |
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| 300 | CLEANUP_HEAP_FREE, |
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| 301 | CLEANUP_UPT_LOCK, |
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| 302 | CLEANUP_UPT_DECREMENT, |
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| 303 | CLEANUP_UPT_CLEAR, |
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| 304 | CLEANUP_WRITE_RSP, |
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[434] | 305 | CLEANUP_CONFIG_ACK, |
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| 306 | CLEANUP_SEND_CLACK |
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[331] | 307 | }; |
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| 308 | |
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| 309 | /* States of the ALLOC_DIR fsm */ |
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[395] | 310 | enum alloc_dir_fsm_state_e |
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| 311 | { |
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[331] | 312 | ALLOC_DIR_RESET, |
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[434] | 313 | ALLOC_DIR_CONFIG, |
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[331] | 314 | ALLOC_DIR_READ, |
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| 315 | ALLOC_DIR_WRITE, |
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| 316 | ALLOC_DIR_CAS, |
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| 317 | ALLOC_DIR_CLEANUP, |
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| 318 | ALLOC_DIR_XRAM_RSP |
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| 319 | }; |
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| 320 | |
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| 321 | /* States of the ALLOC_TRT fsm */ |
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[395] | 322 | enum alloc_trt_fsm_state_e |
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| 323 | { |
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[331] | 324 | ALLOC_TRT_READ, |
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| 325 | ALLOC_TRT_WRITE, |
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| 326 | ALLOC_TRT_CAS, |
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| 327 | ALLOC_TRT_XRAM_RSP, |
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| 328 | ALLOC_TRT_IXR_RSP |
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| 329 | }; |
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| 330 | |
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| 331 | /* States of the ALLOC_UPT fsm */ |
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[395] | 332 | enum alloc_upt_fsm_state_e |
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| 333 | { |
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[434] | 334 | ALLOC_UPT_CONFIG, |
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[331] | 335 | ALLOC_UPT_WRITE, |
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| 336 | ALLOC_UPT_XRAM_RSP, |
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| 337 | ALLOC_UPT_MULTI_ACK, |
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| 338 | ALLOC_UPT_CLEANUP, |
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| 339 | ALLOC_UPT_CAS |
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| 340 | }; |
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| 341 | |
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| 342 | /* States of the ALLOC_HEAP fsm */ |
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[395] | 343 | enum alloc_heap_fsm_state_e |
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| 344 | { |
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[331] | 345 | ALLOC_HEAP_RESET, |
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| 346 | ALLOC_HEAP_READ, |
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| 347 | ALLOC_HEAP_WRITE, |
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| 348 | ALLOC_HEAP_CAS, |
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| 349 | ALLOC_HEAP_CLEANUP, |
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[439] | 350 | ALLOC_HEAP_XRAM_RSP, |
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| 351 | ALLOC_HEAP_CONFIG |
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[331] | 352 | }; |
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| 353 | |
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| 354 | /* transaction type, pktid field */ |
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| 355 | enum transaction_type_e |
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| 356 | { |
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| 357 | // b3 unused |
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| 358 | // b2 READ / NOT READ |
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| 359 | // Si READ |
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| 360 | // b1 DATA / INS |
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| 361 | // b0 UNC / MISS |
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| 362 | // Si NOT READ |
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| 363 | // b1 accÚs table llsc type SW / other |
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| 364 | // b2 WRITE/CAS/LL/SC |
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| 365 | TYPE_READ_DATA_UNC = 0x0, |
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| 366 | TYPE_READ_DATA_MISS = 0x1, |
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| 367 | TYPE_READ_INS_UNC = 0x2, |
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| 368 | TYPE_READ_INS_MISS = 0x3, |
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| 369 | TYPE_WRITE = 0x4, |
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| 370 | TYPE_CAS = 0x5, |
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| 371 | TYPE_LL = 0x6, |
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| 372 | TYPE_SC = 0x7 |
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| 373 | }; |
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| 374 | |
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| 375 | /* SC return values */ |
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| 376 | enum sc_status_type_e |
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| 377 | { |
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| 378 | SC_SUCCESS = 0x00000000, |
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| 379 | SC_FAIL = 0x00000001 |
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| 380 | }; |
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| 381 | |
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[434] | 382 | /* Configuration commands */ |
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| 383 | enum cmd_config_type_e |
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| 384 | { |
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| 385 | CMD_CONFIG_INVAL = 0, |
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| 386 | CMD_CONFIG_SYNC = 1 |
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| 387 | }; |
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| 388 | |
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[331] | 389 | // debug variables (for each FSM) |
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[449] | 390 | bool m_debug; |
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| 391 | bool m_debug_previous_valid; |
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| 392 | size_t m_debug_previous_count; |
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| 393 | bool m_debug_previous_dirty; |
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| 394 | sc_signal<data_t>* m_debug_previous_data; |
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| 395 | sc_signal<data_t>* m_debug_data; |
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[331] | 396 | |
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| 397 | bool m_monitor_ok; |
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[385] | 398 | addr_t m_monitor_base; |
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| 399 | addr_t m_monitor_length; |
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[331] | 400 | |
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| 401 | // instrumentation counters |
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| 402 | uint32_t m_cpt_cycles; // Counter of cycles |
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[434] | 403 | |
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[331] | 404 | uint32_t m_cpt_read; // Number of READ transactions |
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[434] | 405 | uint32_t m_cpt_read_remote; // number of remote READ transactions |
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| 406 | uint32_t m_cpt_read_flits; // number of flits for READs |
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| 407 | uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs |
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| 408 | |
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[331] | 409 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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[434] | 410 | |
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[331] | 411 | uint32_t m_cpt_write; // Number of WRITE transactions |
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[434] | 412 | uint32_t m_cpt_write_remote; // number of remote WRITE transactions |
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| 413 | uint32_t m_cpt_write_flits; // number of flits for WRITEs |
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| 414 | uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs |
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| 415 | |
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[331] | 416 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 417 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 418 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 419 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 420 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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| 421 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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| 422 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 423 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 424 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 425 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 426 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 427 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 428 | uint32_t m_cpt_sc; // Number of SC transactions |
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| 429 | uint32_t m_cpt_cas; // Number of CAS transactions |
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| 430 | |
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[434] | 431 | uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs |
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| 432 | |
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| 433 | uint32_t m_cpt_update_flits; // Number of flits for UPDATEs |
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| 434 | uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs |
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| 435 | |
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| 436 | uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs |
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| 437 | |
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| 438 | uint32_t m_cpt_get; |
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| 439 | |
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| 440 | uint32_t m_cpt_put; |
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| 441 | |
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[331] | 442 | size_t m_prev_count; |
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| 443 | |
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| 444 | protected: |
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| 445 | |
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| 446 | SC_HAS_PROCESS(VciMemCache); |
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| 447 | |
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| 448 | public: |
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[385] | 449 | sc_in<bool> p_clk; |
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| 450 | sc_in<bool> p_resetn; |
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| 451 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt; |
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| 452 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; |
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| 453 | soclib::caba::DspinInput<dspin_in_width> p_dspin_in; |
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| 454 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; |
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[331] | 455 | |
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| 456 | VciMemCache( |
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| 457 | sc_module_name name, // Instance Name |
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[434] | 458 | const soclib::common::MappingTable &mtp, // Mapping table INT network |
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| 459 | const soclib::common::MappingTable &mtx, // Mapping table RAM network |
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| 460 | const soclib::common::IntTab &srcid_x, // global index RAM network |
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| 461 | const soclib::common::IntTab &tgtid_d, // global index INT network |
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| 462 | const size_t cc_global_id, // global index CC network |
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[346] | 463 | const size_t nways, // Number of ways per set |
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| 464 | const size_t nsets, // Number of sets |
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| 465 | const size_t nwords, // Number of words per line |
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[434] | 466 | const size_t max_copies, // max number of copies |
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[395] | 467 | const size_t heap_size=HEAP_ENTRIES, |
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| 468 | const size_t trt_lines=TRT_ENTRIES, |
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| 469 | const size_t upt_lines=UPT_ENTRIES, |
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[346] | 470 | const size_t debug_start_cycle=0, |
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| 471 | const bool debug_ok=false ); |
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[331] | 472 | |
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| 473 | ~VciMemCache(); |
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| 474 | |
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| 475 | void print_stats(); |
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| 476 | void print_trace(); |
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[449] | 477 | void cache_monitor(addr_t addr); |
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[385] | 478 | void start_monitor(addr_t addr, addr_t length); |
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[331] | 479 | void stop_monitor(); |
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| 480 | |
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| 481 | private: |
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| 482 | |
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| 483 | void transition(); |
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| 484 | void genMoore(); |
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[449] | 485 | void check_monitor(addr_t addr, data_t data, bool read); |
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[331] | 486 | |
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| 487 | // Component attributes |
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[434] | 488 | std::list<soclib::common::Segment> m_seglist; // segments allocated |
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[346] | 489 | size_t m_nseg; // number of segments |
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| 490 | soclib::common::Segment **m_seg; // array of segments pointers |
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[434] | 491 | size_t m_seg_config; // config segment index |
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| 492 | const size_t m_srcid_x; // global index on RAM network |
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[346] | 493 | const size_t m_initiators; // Number of initiators |
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| 494 | const size_t m_heap_size; // Size of the heap |
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| 495 | const size_t m_ways; // Number of ways in a set |
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| 496 | const size_t m_sets; // Number of cache sets |
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| 497 | const size_t m_words; // Number of words in a line |
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| 498 | const size_t m_cc_global_id; // global_index on cc network |
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| 499 | size_t m_debug_start_cycle; |
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| 500 | bool m_debug_ok; |
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| 501 | uint32_t m_trt_lines; |
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| 502 | TransactionTab m_trt; // xram transaction table |
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| 503 | uint32_t m_upt_lines; |
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| 504 | UpdateTab m_upt; // pending update & invalidate |
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| 505 | CacheDirectory m_cache_directory; // data cache directory |
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| 506 | CacheData m_cache_data; // data array[set][way][word] |
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| 507 | HeapDirectory m_heap; // heap for copies |
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| 508 | size_t m_max_copies; // max number of copies in heap |
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[331] | 509 | GenericLLSCGlobalTable |
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[434] | 510 | < 32 , // number of slots |
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| 511 | 4096, // number of processors in the system |
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| 512 | 8000, // registration life (# of LL operations) |
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| 513 | addr_t > m_llsc_table; // ll/sc registration table |
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[331] | 514 | |
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| 515 | // adress masks |
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[385] | 516 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
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| 517 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
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| 518 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
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| 519 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
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[331] | 520 | |
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| 521 | // broadcast address |
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[395] | 522 | uint32_t m_broadcast_boundaries; |
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[331] | 523 | |
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| 524 | ////////////////////////////////////////////////// |
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| 525 | // Registers controlled by the TGT_CMD fsm |
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| 526 | ////////////////////////////////////////////////// |
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| 527 | |
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[430] | 528 | sc_signal<int> r_tgt_cmd_fsm; |
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| 529 | |
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[331] | 530 | // Fifo between TGT_CMD fsm and READ fsm |
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[385] | 531 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
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[331] | 532 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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| 533 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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| 534 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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| 535 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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| 536 | |
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| 537 | // Fifo between TGT_CMD fsm and WRITE fsm |
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[385] | 538 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
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[331] | 539 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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| 540 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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| 541 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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| 542 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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| 543 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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| 544 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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| 545 | |
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| 546 | // Fifo between TGT_CMD fsm and CAS fsm |
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[385] | 547 | GenericFifo<addr_t> m_cmd_cas_addr_fifo; |
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[331] | 548 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
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| 549 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
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| 550 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
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| 551 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
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| 552 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
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| 553 | |
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[403] | 554 | // Fifo between CC_RECEIVE fsm and CLEANUP fsm |
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[331] | 555 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
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| 556 | |
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[403] | 557 | // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm |
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[331] | 558 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
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| 559 | |
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[430] | 560 | // Buffer between TGT_CMD fsm and TGT_RSP fsm |
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| 561 | // (segmentation violation response request) |
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| 562 | sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req; |
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[434] | 563 | |
---|
| 564 | sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata; |
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| 565 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error; |
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[430] | 566 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid; |
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| 567 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid; |
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| 568 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid; |
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[331] | 569 | |
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[434] | 570 | sc_signal<addr_t> r_tgt_cmd_config_addr; |
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| 571 | sc_signal<size_t> r_tgt_cmd_config_cmd; |
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| 572 | |
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[331] | 573 | /////////////////////////////////////////////////////// |
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[434] | 574 | // Registers controlled by the CONFIG fsm |
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| 575 | /////////////////////////////////////////////////////// |
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| 576 | |
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[439] | 577 | sc_signal<int> r_config_fsm; // FSM state |
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| 578 | sc_signal<bool> r_config_lock; // lock protecting exclusive access |
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| 579 | sc_signal<int> r_config_cmd; // config request status |
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| 580 | sc_signal<addr_t> r_config_address; // target buffer physical address |
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| 581 | sc_signal<size_t> r_config_srcid; // config request srcid |
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| 582 | sc_signal<size_t> r_config_trdid; // config request trdid |
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| 583 | sc_signal<size_t> r_config_pktid; // config request pktid |
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| 584 | sc_signal<size_t> r_config_nlines; // number of lines covering the buffer |
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| 585 | sc_signal<size_t> r_config_dir_way; // DIR: selected way |
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| 586 | sc_signal<size_t> r_config_dir_count; // DIR: number of copies |
---|
| 587 | sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required) |
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| 588 | sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID |
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| 589 | sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type |
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| 590 | sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP |
---|
| 591 | sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP |
---|
| 592 | |
---|
[434] | 593 | sc_signal<size_t> r_config_upt_index; // UPT index |
---|
| 594 | |
---|
| 595 | // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) |
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| 596 | sc_signal<bool> r_config_to_tgt_rsp_req; // valid request |
---|
| 597 | sc_signal<bool> r_config_to_tgt_rsp_error; // error response |
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| 598 | sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid |
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| 599 | sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid |
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| 600 | sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 601 | |
---|
| 602 | // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) |
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| 603 | sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request |
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| 604 | sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request |
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[439] | 605 | sc_signal<addr_t> r_config_to_cc_send_nline; // line index |
---|
[434] | 606 | sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index |
---|
[439] | 607 | GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 608 | GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid |
---|
[434] | 609 | |
---|
[439] | 610 | #if L1_MULTI_CACHE |
---|
| 611 | GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id |
---|
| 612 | #endif |
---|
| 613 | |
---|
[434] | 614 | /////////////////////////////////////////////////////// |
---|
[331] | 615 | // Registers controlled by the READ fsm |
---|
| 616 | /////////////////////////////////////////////////////// |
---|
| 617 | |
---|
[434] | 618 | sc_signal<int> r_read_fsm; // FSM state |
---|
| 619 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
| 620 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
| 621 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
| 622 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
| 623 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
| 624 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
| 625 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
| 626 | sc_signal<size_t> r_read_count; // number of copies |
---|
| 627 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
| 628 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
| 629 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 630 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 631 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 632 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
| 633 | sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table |
---|
[331] | 634 | |
---|
| 635 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 636 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 637 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
---|
| 638 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 639 | |
---|
| 640 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
| 641 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 642 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 643 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 644 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 645 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 646 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 647 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
[385] | 648 | sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table |
---|
[331] | 649 | |
---|
| 650 | /////////////////////////////////////////////////////////////// |
---|
| 651 | // Registers controlled by the WRITE fsm |
---|
| 652 | /////////////////////////////////////////////////////////////// |
---|
| 653 | |
---|
| 654 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 655 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 656 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 657 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 658 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 659 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 660 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 661 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
| 662 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
| 663 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
| 664 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 665 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 666 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 667 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 668 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
| 669 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 670 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 671 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 672 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 673 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 674 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 675 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 676 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 677 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
[336] | 678 | sc_signal<bool> r_write_pending_sc; // sc command pending |
---|
[331] | 679 | |
---|
| 680 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 681 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 682 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 683 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 684 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 685 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
| 686 | |
---|
| 687 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 688 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 689 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
| 690 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
| 691 | sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data |
---|
| 692 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 693 | |
---|
| 694 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 695 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
| 696 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
| 697 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
| 698 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
| 699 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
| 700 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
| 701 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
| 702 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
| 703 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 704 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 705 | |
---|
[331] | 706 | #if L1_MULTI_CACHE |
---|
| 707 | GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
| 708 | #endif |
---|
| 709 | |
---|
| 710 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
| 711 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
| 712 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
| 713 | |
---|
| 714 | ///////////////////////////////////////////////////////// |
---|
| 715 | // Registers controlled by MULTI_ACK fsm |
---|
| 716 | ////////////////////////////////////////////////////////// |
---|
| 717 | |
---|
| 718 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
| 719 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
| 720 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
| 721 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
---|
| 722 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
| 723 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
| 724 | |
---|
[434] | 725 | // signaling completion of multi-inval to CONFIG fsm |
---|
| 726 | sc_signal<bool> r_multi_ack_to_config_ack; |
---|
| 727 | |
---|
[331] | 728 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
| 729 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
| 730 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 731 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 732 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 733 | |
---|
| 734 | /////////////////////////////////////////////////////// |
---|
| 735 | // Registers controlled by CLEANUP fsm |
---|
| 736 | /////////////////////////////////////////////////////// |
---|
| 737 | |
---|
| 738 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 739 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 740 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
| 741 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
| 742 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 743 | |
---|
| 744 | #if L1_MULTI_CACHE |
---|
| 745 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
| 746 | #endif |
---|
| 747 | |
---|
| 748 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 749 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
| 750 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 751 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 752 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 753 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 754 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 755 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
| 756 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 757 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 758 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 759 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 760 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 761 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 762 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 763 | |
---|
[434] | 764 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp |
---|
[331] | 765 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 766 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 767 | |
---|
[434] | 768 | sc_signal<bool> r_cleanup_need_rsp; // write response required |
---|
| 769 | sc_signal<bool> r_cleanup_need_ack; // config acknowledge required |
---|
| 770 | |
---|
[331] | 771 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 772 | |
---|
[434] | 773 | // signaling completion of broadcast-inval to CONFIG fsm |
---|
| 774 | sc_signal<bool> r_cleanup_to_config_ack; |
---|
| 775 | |
---|
[331] | 776 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 777 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 778 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 779 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 780 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
| 781 | |
---|
| 782 | // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1) |
---|
| 783 | sc_signal<bool> r_cleanup_to_cc_send_req; // valid request |
---|
| 784 | sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid |
---|
| 785 | sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index |
---|
| 786 | sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index |
---|
| 787 | sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack |
---|
| 788 | |
---|
| 789 | /////////////////////////////////////////////////////// |
---|
| 790 | // Registers controlled by CAS fsm |
---|
| 791 | /////////////////////////////////////////////////////// |
---|
| 792 | |
---|
| 793 | sc_signal<int> r_cas_fsm; // FSM state |
---|
| 794 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
| 795 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
| 796 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
| 797 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
| 798 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
| 799 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
| 800 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
| 801 | sc_signal<size_t> r_cas_count; // number of copies |
---|
| 802 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
| 803 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
| 804 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
| 805 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
| 806 | sc_signal<size_t> r_cas_way; // way in directory |
---|
| 807 | sc_signal<size_t> r_cas_set; // set in directory |
---|
| 808 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
| 809 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
| 810 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
| 811 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
| 812 | |
---|
| 813 | // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) |
---|
| 814 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
| 815 | sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index |
---|
| 816 | sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 817 | sc_signal<bool> r_cas_to_ixr_cmd_write; // write request |
---|
| 818 | sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data |
---|
| 819 | |
---|
| 820 | |
---|
| 821 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
| 822 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
| 823 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
| 824 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 825 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 826 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 827 | |
---|
| 828 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 829 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
| 830 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
| 831 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
| 832 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
| 833 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
| 834 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
| 835 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
| 836 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
| 837 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 838 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 839 | |
---|
[331] | 840 | #if L1_MULTI_CACHE |
---|
| 841 | GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
| 842 | #endif |
---|
| 843 | |
---|
| 844 | //////////////////////////////////////////////////// |
---|
| 845 | // Registers controlled by the IXR_RSP fsm |
---|
| 846 | //////////////////////////////////////////////////// |
---|
| 847 | |
---|
| 848 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 849 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 850 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
| 851 | |
---|
| 852 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
| 853 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
| 854 | |
---|
| 855 | //////////////////////////////////////////////////// |
---|
| 856 | // Registers controlled by the XRAM_RSP fsm |
---|
| 857 | //////////////////////////////////////////////////// |
---|
| 858 | |
---|
| 859 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 860 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 861 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 862 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 863 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 864 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 865 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 866 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 867 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 868 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 869 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
| 870 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 871 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 872 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 873 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
| 874 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
| 875 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
| 876 | |
---|
| 877 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
| 878 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 879 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 880 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 881 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 882 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 883 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 884 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
| 885 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
[385] | 886 | sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
[331] | 887 | |
---|
| 888 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
---|
| 889 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
---|
| 890 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
---|
| 891 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
---|
| 892 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
---|
| 893 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 894 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 895 | |
---|
[331] | 896 | #if L1_MULTI_CACHE |
---|
| 897 | GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids |
---|
| 898 | #endif |
---|
| 899 | |
---|
| 900 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
---|
| 901 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
| 902 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
---|
| 903 | sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data |
---|
| 904 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
---|
| 905 | |
---|
| 906 | //////////////////////////////////////////////////// |
---|
| 907 | // Registers controlled by the IXR_CMD fsm |
---|
| 908 | //////////////////////////////////////////////////// |
---|
| 909 | |
---|
| 910 | sc_signal<int> r_ixr_cmd_fsm; |
---|
| 911 | sc_signal<size_t> r_ixr_cmd_cpt; |
---|
| 912 | |
---|
| 913 | //////////////////////////////////////////////////// |
---|
| 914 | // Registers controlled by TGT_RSP fsm |
---|
| 915 | //////////////////////////////////////////////////// |
---|
| 916 | |
---|
| 917 | sc_signal<int> r_tgt_rsp_fsm; |
---|
| 918 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
[362] | 919 | sc_signal<bool> r_tgt_rsp_key_sent; |
---|
[331] | 920 | |
---|
| 921 | //////////////////////////////////////////////////// |
---|
| 922 | // Registers controlled by CC_SEND fsm |
---|
| 923 | //////////////////////////////////////////////////// |
---|
| 924 | |
---|
| 925 | sc_signal<int> r_cc_send_fsm; |
---|
| 926 | sc_signal<size_t> r_cc_send_cpt; |
---|
| 927 | sc_signal<bool> r_cc_send_inst; |
---|
| 928 | |
---|
| 929 | //////////////////////////////////////////////////// |
---|
| 930 | // Registers controlled by CC_RECEIVE fsm |
---|
| 931 | //////////////////////////////////////////////////// |
---|
| 932 | |
---|
| 933 | sc_signal<int> r_cc_receive_fsm; |
---|
| 934 | |
---|
| 935 | //////////////////////////////////////////////////// |
---|
| 936 | // Registers controlled by ALLOC_DIR fsm |
---|
| 937 | //////////////////////////////////////////////////// |
---|
| 938 | |
---|
| 939 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 940 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
| 941 | |
---|
| 942 | //////////////////////////////////////////////////// |
---|
| 943 | // Registers controlled by ALLOC_TRT fsm |
---|
| 944 | //////////////////////////////////////////////////// |
---|
| 945 | |
---|
| 946 | sc_signal<int> r_alloc_trt_fsm; |
---|
| 947 | |
---|
| 948 | //////////////////////////////////////////////////// |
---|
| 949 | // Registers controlled by ALLOC_UPT fsm |
---|
| 950 | //////////////////////////////////////////////////// |
---|
| 951 | |
---|
| 952 | sc_signal<int> r_alloc_upt_fsm; |
---|
| 953 | |
---|
| 954 | //////////////////////////////////////////////////// |
---|
| 955 | // Registers controlled by ALLOC_HEAP fsm |
---|
| 956 | //////////////////////////////////////////////////// |
---|
| 957 | |
---|
| 958 | sc_signal<int> r_alloc_heap_fsm; |
---|
| 959 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
---|
| 960 | }; // end class VciMemCache |
---|
| 961 | |
---|
| 962 | }} |
---|
| 963 | |
---|
| 964 | #endif |
---|
| 965 | |
---|
| 966 | // Local Variables: |
---|
| 967 | // tab-width: 2 |
---|
| 968 | // c-basic-offset: 2 |
---|
| 969 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 970 | // indent-tabs-mode: nil |
---|
| 971 | // End: |
---|
| 972 | |
---|
| 973 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
---|
| 974 | |
---|