[331] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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[489] | 27 | * Maintainers: alain.greiner@lip6.fr |
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| 28 | * eric.guthmuller@polytechnique.edu |
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[331] | 29 | * cesar.fuguet-tortolero@lip6.fr |
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| 30 | * alexandre.joannou@lip6.fr |
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| 31 | */ |
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| 32 | |
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| 33 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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| 34 | #define SOCLIB_CABA_MEM_CACHE_H |
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| 35 | |
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| 36 | #include <inttypes.h> |
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| 37 | #include <systemc> |
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| 38 | #include <list> |
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| 39 | #include <cassert> |
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| 40 | #include "arithmetics.h" |
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| 41 | #include "alloc_elems.h" |
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| 42 | #include "caba_base_module.h" |
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| 43 | #include "vci_target.h" |
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| 44 | #include "vci_initiator.h" |
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| 45 | #include "generic_fifo.h" |
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| 46 | #include "mapping_table.h" |
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| 47 | #include "int_tab.h" |
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| 48 | #include "generic_llsc_global_table.h" |
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| 49 | #include "mem_cache_directory.h" |
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| 50 | #include "xram_transaction.h" |
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| 51 | #include "update_tab.h" |
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| 52 | #include "dspin_interface.h" |
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| 53 | #include "dspin_dhccp_param.h" |
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| 54 | |
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[395] | 55 | #define TRT_ENTRIES 4 // Number of entries in TRT |
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| 56 | #define UPT_ENTRIES 4 // Number of entries in UPT |
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[468] | 57 | #define IVT_ENTRIES 4 // Number of entries in IVT |
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[395] | 58 | #define HEAP_ENTRIES 1024 // Number of entries in HEAP |
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[331] | 59 | |
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| 60 | namespace soclib { namespace caba { |
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[395] | 61 | |
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[331] | 62 | using namespace sc_core; |
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| 63 | |
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[385] | 64 | template<typename vci_param_int, |
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| 65 | typename vci_param_ext, |
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| 66 | size_t dspin_in_width, |
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| 67 | size_t dspin_out_width> |
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[331] | 68 | class VciMemCache |
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| 69 | : public soclib::caba::BaseModule |
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| 70 | { |
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[385] | 71 | typedef typename vci_param_int::fast_addr_t addr_t; |
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| 72 | typedef typename sc_dt::sc_uint<64> wide_data_t; |
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[449] | 73 | typedef uint32_t data_t; |
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| 74 | typedef uint32_t tag_t; |
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| 75 | typedef uint32_t be_t; |
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| 76 | typedef uint32_t copy_t; |
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[385] | 77 | |
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[331] | 78 | /* States of the TGT_CMD fsm */ |
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[434] | 79 | enum tgt_cmd_fsm_state_e |
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| 80 | { |
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[331] | 81 | TGT_CMD_IDLE, |
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[430] | 82 | TGT_CMD_ERROR, |
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[331] | 83 | TGT_CMD_READ, |
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| 84 | TGT_CMD_WRITE, |
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[434] | 85 | TGT_CMD_CAS, |
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| 86 | TGT_CMD_CONFIG |
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[331] | 87 | }; |
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| 88 | |
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| 89 | /* States of the TGT_RSP fsm */ |
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[395] | 90 | enum tgt_rsp_fsm_state_e |
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| 91 | { |
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[439] | 92 | TGT_RSP_CONFIG_IDLE, |
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[430] | 93 | TGT_RSP_TGT_CMD_IDLE, |
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[331] | 94 | TGT_RSP_READ_IDLE, |
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| 95 | TGT_RSP_WRITE_IDLE, |
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| 96 | TGT_RSP_CAS_IDLE, |
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| 97 | TGT_RSP_XRAM_IDLE, |
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[430] | 98 | TGT_RSP_MULTI_ACK_IDLE, |
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[331] | 99 | TGT_RSP_CLEANUP_IDLE, |
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[439] | 100 | TGT_RSP_CONFIG, |
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[430] | 101 | TGT_RSP_TGT_CMD, |
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[331] | 102 | TGT_RSP_READ, |
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| 103 | TGT_RSP_WRITE, |
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| 104 | TGT_RSP_CAS, |
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| 105 | TGT_RSP_XRAM, |
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[430] | 106 | TGT_RSP_MULTI_ACK, |
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[483] | 107 | TGT_RSP_CLEANUP |
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[331] | 108 | }; |
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| 109 | |
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| 110 | /* States of the DSPIN_TGT fsm */ |
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[395] | 111 | enum cc_receive_fsm_state_e |
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| 112 | { |
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[331] | 113 | CC_RECEIVE_IDLE, |
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| 114 | CC_RECEIVE_CLEANUP, |
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[403] | 115 | CC_RECEIVE_CLEANUP_EOP, |
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[331] | 116 | CC_RECEIVE_MULTI_ACK |
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| 117 | }; |
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| 118 | |
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| 119 | /* States of the CC_SEND fsm */ |
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[395] | 120 | enum cc_send_fsm_state_e |
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| 121 | { |
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[439] | 122 | CC_SEND_CONFIG_IDLE, |
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[331] | 123 | CC_SEND_XRAM_RSP_IDLE, |
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| 124 | CC_SEND_WRITE_IDLE, |
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| 125 | CC_SEND_CAS_IDLE, |
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[439] | 126 | CC_SEND_CONFIG_INVAL_HEADER, |
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| 127 | CC_SEND_CONFIG_INVAL_NLINE, |
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| 128 | CC_SEND_CONFIG_BRDCAST_HEADER, |
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| 129 | CC_SEND_CONFIG_BRDCAST_NLINE, |
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[331] | 130 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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| 131 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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| 132 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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| 133 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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| 134 | CC_SEND_WRITE_BRDCAST_HEADER, |
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| 135 | CC_SEND_WRITE_BRDCAST_NLINE, |
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| 136 | CC_SEND_WRITE_UPDT_HEADER, |
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| 137 | CC_SEND_WRITE_UPDT_NLINE, |
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| 138 | CC_SEND_WRITE_UPDT_DATA, |
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| 139 | CC_SEND_CAS_BRDCAST_HEADER, |
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| 140 | CC_SEND_CAS_BRDCAST_NLINE, |
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| 141 | CC_SEND_CAS_UPDT_HEADER, |
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| 142 | CC_SEND_CAS_UPDT_NLINE, |
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| 143 | CC_SEND_CAS_UPDT_DATA, |
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| 144 | CC_SEND_CAS_UPDT_DATA_HIGH |
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| 145 | }; |
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| 146 | |
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| 147 | /* States of the MULTI_ACK fsm */ |
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[395] | 148 | enum multi_ack_fsm_state_e |
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| 149 | { |
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[331] | 150 | MULTI_ACK_IDLE, |
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| 151 | MULTI_ACK_UPT_LOCK, |
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| 152 | MULTI_ACK_UPT_CLEAR, |
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[489] | 153 | MULTI_ACK_WRITE_RSP |
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[331] | 154 | }; |
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| 155 | |
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[434] | 156 | /* States of the CONFIG fsm */ |
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| 157 | enum config_fsm_state_e |
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| 158 | { |
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| 159 | CONFIG_IDLE, |
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| 160 | CONFIG_LOOP, |
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[489] | 161 | CONFIG_WAIT, |
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[434] | 162 | CONFIG_RSP, |
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| 163 | CONFIG_DIR_REQ, |
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| 164 | CONFIG_DIR_ACCESS, |
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[489] | 165 | CONFIG_IVT_LOCK, |
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[434] | 166 | CONFIG_BC_SEND, |
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[489] | 167 | CONFIG_INVAL_SEND, |
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[439] | 168 | CONFIG_HEAP_REQ, |
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| 169 | CONFIG_HEAP_SCAN, |
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| 170 | CONFIG_HEAP_LAST, |
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[489] | 171 | CONFIG_TRT_LOCK, |
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| 172 | CONFIG_TRT_SET, |
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| 173 | CONFIG_PUT_REQ |
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[434] | 174 | }; |
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| 175 | |
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[331] | 176 | /* States of the READ fsm */ |
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[395] | 177 | enum read_fsm_state_e |
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| 178 | { |
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[331] | 179 | READ_IDLE, |
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| 180 | READ_DIR_REQ, |
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| 181 | READ_DIR_LOCK, |
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| 182 | READ_DIR_HIT, |
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| 183 | READ_HEAP_REQ, |
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| 184 | READ_HEAP_LOCK, |
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| 185 | READ_HEAP_WRITE, |
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| 186 | READ_HEAP_ERASE, |
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| 187 | READ_HEAP_LAST, |
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| 188 | READ_RSP, |
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| 189 | READ_TRT_LOCK, |
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| 190 | READ_TRT_SET, |
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| 191 | READ_TRT_REQ |
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| 192 | }; |
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| 193 | |
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| 194 | /* States of the WRITE fsm */ |
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[395] | 195 | enum write_fsm_state_e |
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| 196 | { |
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[331] | 197 | WRITE_IDLE, |
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| 198 | WRITE_NEXT, |
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| 199 | WRITE_DIR_REQ, |
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| 200 | WRITE_DIR_LOCK, |
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| 201 | WRITE_DIR_HIT, |
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| 202 | WRITE_UPT_LOCK, |
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| 203 | WRITE_UPT_HEAP_LOCK, |
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| 204 | WRITE_UPT_REQ, |
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| 205 | WRITE_UPT_NEXT, |
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| 206 | WRITE_UPT_DEC, |
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| 207 | WRITE_RSP, |
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| 208 | WRITE_MISS_TRT_LOCK, |
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| 209 | WRITE_MISS_TRT_DATA, |
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| 210 | WRITE_MISS_TRT_SET, |
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| 211 | WRITE_MISS_XRAM_REQ, |
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[489] | 212 | WRITE_BC_DIR_READ, |
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[331] | 213 | WRITE_BC_TRT_LOCK, |
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[468] | 214 | WRITE_BC_IVT_LOCK, |
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[331] | 215 | WRITE_BC_DIR_INVAL, |
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| 216 | WRITE_BC_CC_SEND, |
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| 217 | WRITE_BC_XRAM_REQ, |
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| 218 | WRITE_WAIT |
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| 219 | }; |
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| 220 | |
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| 221 | /* States of the IXR_RSP fsm */ |
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[395] | 222 | enum ixr_rsp_fsm_state_e |
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| 223 | { |
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[331] | 224 | IXR_RSP_IDLE, |
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| 225 | IXR_RSP_TRT_ERASE, |
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| 226 | IXR_RSP_TRT_READ |
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| 227 | }; |
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| 228 | |
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| 229 | /* States of the XRAM_RSP fsm */ |
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[395] | 230 | enum xram_rsp_fsm_state_e |
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| 231 | { |
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[331] | 232 | XRAM_RSP_IDLE, |
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| 233 | XRAM_RSP_TRT_COPY, |
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| 234 | XRAM_RSP_TRT_DIRTY, |
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| 235 | XRAM_RSP_DIR_LOCK, |
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| 236 | XRAM_RSP_DIR_UPDT, |
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| 237 | XRAM_RSP_DIR_RSP, |
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[489] | 238 | XRAM_RSP_IVT_LOCK, |
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[331] | 239 | XRAM_RSP_INVAL_WAIT, |
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| 240 | XRAM_RSP_INVAL, |
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| 241 | XRAM_RSP_WRITE_DIRTY, |
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| 242 | XRAM_RSP_HEAP_REQ, |
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| 243 | XRAM_RSP_HEAP_ERASE, |
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| 244 | XRAM_RSP_HEAP_LAST, |
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| 245 | XRAM_RSP_ERROR_ERASE, |
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| 246 | XRAM_RSP_ERROR_RSP |
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| 247 | }; |
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| 248 | |
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| 249 | /* States of the IXR_CMD fsm */ |
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[395] | 250 | enum ixr_cmd_fsm_state_e |
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| 251 | { |
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[331] | 252 | IXR_CMD_READ_IDLE, |
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| 253 | IXR_CMD_WRITE_IDLE, |
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| 254 | IXR_CMD_CAS_IDLE, |
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| 255 | IXR_CMD_XRAM_IDLE, |
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[489] | 256 | IXR_CMD_CONFIG_IDLE, |
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| 257 | IXR_CMD_READ_TRT, |
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| 258 | IXR_CMD_WRITE_TRT, |
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| 259 | IXR_CMD_CAS_TRT, |
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| 260 | IXR_CMD_XRAM_TRT, |
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| 261 | IXR_CMD_CONFIG_TRT, |
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| 262 | IXR_CMD_READ_SEND, |
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| 263 | IXR_CMD_WRITE_SEND, |
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| 264 | IXR_CMD_CAS_SEND, |
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| 265 | IXR_CMD_XRAM_SEND, |
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| 266 | IXR_CMD_CONFIG_SEND |
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[331] | 267 | }; |
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| 268 | |
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| 269 | /* States of the CAS fsm */ |
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[395] | 270 | enum cas_fsm_state_e |
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| 271 | { |
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[331] | 272 | CAS_IDLE, |
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| 273 | CAS_DIR_REQ, |
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| 274 | CAS_DIR_LOCK, |
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| 275 | CAS_DIR_HIT_READ, |
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| 276 | CAS_DIR_HIT_COMPARE, |
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| 277 | CAS_DIR_HIT_WRITE, |
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| 278 | CAS_UPT_LOCK, |
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| 279 | CAS_UPT_HEAP_LOCK, |
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| 280 | CAS_UPT_REQ, |
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| 281 | CAS_UPT_NEXT, |
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| 282 | CAS_BC_TRT_LOCK, |
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[468] | 283 | CAS_BC_IVT_LOCK, |
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[331] | 284 | CAS_BC_DIR_INVAL, |
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| 285 | CAS_BC_CC_SEND, |
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| 286 | CAS_BC_XRAM_REQ, |
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| 287 | CAS_RSP_FAIL, |
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| 288 | CAS_RSP_SUCCESS, |
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| 289 | CAS_MISS_TRT_LOCK, |
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| 290 | CAS_MISS_TRT_SET, |
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| 291 | CAS_MISS_XRAM_REQ, |
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| 292 | CAS_WAIT |
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| 293 | }; |
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| 294 | |
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| 295 | /* States of the CLEANUP fsm */ |
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[395] | 296 | enum cleanup_fsm_state_e |
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| 297 | { |
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[331] | 298 | CLEANUP_IDLE, |
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| 299 | CLEANUP_GET_NLINE, |
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| 300 | CLEANUP_DIR_REQ, |
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| 301 | CLEANUP_DIR_LOCK, |
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| 302 | CLEANUP_DIR_WRITE, |
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| 303 | CLEANUP_HEAP_REQ, |
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| 304 | CLEANUP_HEAP_LOCK, |
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| 305 | CLEANUP_HEAP_SEARCH, |
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| 306 | CLEANUP_HEAP_CLEAN, |
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| 307 | CLEANUP_HEAP_FREE, |
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[468] | 308 | CLEANUP_IVT_LOCK, |
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| 309 | CLEANUP_IVT_DECREMENT, |
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| 310 | CLEANUP_IVT_CLEAR, |
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[331] | 311 | CLEANUP_WRITE_RSP, |
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[434] | 312 | CLEANUP_SEND_CLACK |
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[331] | 313 | }; |
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| 314 | |
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| 315 | /* States of the ALLOC_DIR fsm */ |
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[395] | 316 | enum alloc_dir_fsm_state_e |
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| 317 | { |
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[331] | 318 | ALLOC_DIR_RESET, |
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[434] | 319 | ALLOC_DIR_CONFIG, |
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[331] | 320 | ALLOC_DIR_READ, |
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| 321 | ALLOC_DIR_WRITE, |
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| 322 | ALLOC_DIR_CAS, |
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| 323 | ALLOC_DIR_CLEANUP, |
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| 324 | ALLOC_DIR_XRAM_RSP |
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| 325 | }; |
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| 326 | |
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| 327 | /* States of the ALLOC_TRT fsm */ |
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[395] | 328 | enum alloc_trt_fsm_state_e |
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| 329 | { |
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[331] | 330 | ALLOC_TRT_READ, |
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| 331 | ALLOC_TRT_WRITE, |
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| 332 | ALLOC_TRT_CAS, |
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| 333 | ALLOC_TRT_XRAM_RSP, |
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[489] | 334 | ALLOC_TRT_IXR_RSP, |
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| 335 | ALLOC_TRT_CONFIG, |
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| 336 | ALLOC_TRT_IXR_CMD |
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[331] | 337 | }; |
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| 338 | |
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| 339 | /* States of the ALLOC_UPT fsm */ |
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[395] | 340 | enum alloc_upt_fsm_state_e |
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| 341 | { |
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[331] | 342 | ALLOC_UPT_WRITE, |
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[468] | 343 | ALLOC_UPT_CAS, |
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[483] | 344 | ALLOC_UPT_MULTI_ACK |
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[331] | 345 | }; |
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| 346 | |
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[468] | 347 | /* States of the ALLOC_IVT fsm */ |
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| 348 | enum alloc_ivt_fsm_state_e |
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| 349 | { |
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| 350 | ALLOC_IVT_WRITE, |
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| 351 | ALLOC_IVT_XRAM_RSP, |
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| 352 | ALLOC_IVT_CLEANUP, |
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| 353 | ALLOC_IVT_CAS, |
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[483] | 354 | ALLOC_IVT_CONFIG |
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[468] | 355 | }; |
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| 356 | |
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[331] | 357 | /* States of the ALLOC_HEAP fsm */ |
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[395] | 358 | enum alloc_heap_fsm_state_e |
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| 359 | { |
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[331] | 360 | ALLOC_HEAP_RESET, |
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| 361 | ALLOC_HEAP_READ, |
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| 362 | ALLOC_HEAP_WRITE, |
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| 363 | ALLOC_HEAP_CAS, |
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| 364 | ALLOC_HEAP_CLEANUP, |
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[439] | 365 | ALLOC_HEAP_XRAM_RSP, |
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| 366 | ALLOC_HEAP_CONFIG |
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[331] | 367 | }; |
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| 368 | |
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| 369 | /* transaction type, pktid field */ |
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| 370 | enum transaction_type_e |
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| 371 | { |
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| 372 | // b3 unused |
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| 373 | // b2 READ / NOT READ |
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| 374 | // Si READ |
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| 375 | // b1 DATA / INS |
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| 376 | // b0 UNC / MISS |
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| 377 | // Si NOT READ |
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| 378 | // b1 accÚs table llsc type SW / other |
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| 379 | // b2 WRITE/CAS/LL/SC |
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| 380 | TYPE_READ_DATA_UNC = 0x0, |
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| 381 | TYPE_READ_DATA_MISS = 0x1, |
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| 382 | TYPE_READ_INS_UNC = 0x2, |
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| 383 | TYPE_READ_INS_MISS = 0x3, |
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| 384 | TYPE_WRITE = 0x4, |
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| 385 | TYPE_CAS = 0x5, |
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| 386 | TYPE_LL = 0x6, |
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| 387 | TYPE_SC = 0x7 |
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| 388 | }; |
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| 389 | |
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| 390 | /* SC return values */ |
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| 391 | enum sc_status_type_e |
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| 392 | { |
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| 393 | SC_SUCCESS = 0x00000000, |
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| 394 | SC_FAIL = 0x00000001 |
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| 395 | }; |
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| 396 | |
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[489] | 397 | // debug variables |
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[449] | 398 | bool m_debug; |
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| 399 | bool m_debug_previous_valid; |
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| 400 | size_t m_debug_previous_count; |
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| 401 | bool m_debug_previous_dirty; |
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[489] | 402 | data_t * m_debug_previous_data; |
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| 403 | data_t * m_debug_data; |
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[331] | 404 | |
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| 405 | // instrumentation counters |
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[504] | 406 | uint32_t m_cpt_cycles; // Counter of cycles |
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[434] | 407 | |
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[504] | 408 | // Counters accessible in software (not yet but eventually) |
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| 409 | uint32_t m_cpt_read_local; // Number of local READ transactions |
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| 410 | uint32_t m_cpt_read_remote; // number of remote READ transactions |
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| 411 | uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs |
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[434] | 412 | |
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[504] | 413 | uint32_t m_cpt_write_local; // Number of local WRITE transactions |
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| 414 | uint32_t m_cpt_write_remote; // number of remote WRITE transactions |
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| 415 | uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs |
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| 416 | uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs |
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| 417 | uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs |
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[434] | 418 | |
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[504] | 419 | uint32_t m_cpt_ll_local; // Number of local LL transactions |
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| 420 | uint32_t m_cpt_ll_remote; // number of remote LL transactions |
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| 421 | uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs |
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[434] | 422 | |
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[504] | 423 | uint32_t m_cpt_sc_local; // Number of local SC transactions |
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| 424 | uint32_t m_cpt_sc_remote; // number of remote SC transactions |
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| 425 | uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs |
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[331] | 426 | |
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[504] | 427 | uint32_t m_cpt_cas_local; // Number of local SC transactions |
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| 428 | uint32_t m_cpt_cas_remote; // number of remote SC transactions |
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| 429 | uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs |
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[434] | 430 | |
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[504] | 431 | uint32_t m_cpt_update; // Number of requests causing an UPDATE |
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| 432 | uint32_t m_cpt_update_local; // Number of local UPDATE transactions |
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| 433 | uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions |
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| 434 | uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT |
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[434] | 435 | |
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[504] | 436 | uint32_t m_cpt_m_inval; // Number of requests causing M_INV |
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| 437 | uint32_t m_cpt_m_inval_local; // Number of local M_INV transactions |
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| 438 | uint32_t m_cpt_m_inval_remote; // Number of remote M_INV transactions |
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| 439 | uint32_t m_cpt_m_inval_cost; // Number of (flits * distance) for M_INV |
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[434] | 440 | |
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[504] | 441 | uint32_t m_cpt_br_inval; // Number of BROADCAST INVAL |
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| 442 | |
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| 443 | uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions |
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| 444 | uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions |
---|
| 445 | uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs |
---|
| 446 | |
---|
| 447 | // Counters not accessible by software |
---|
| 448 | uint32_t m_cpt_read_miss; // Number of MISS READ |
---|
| 449 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
---|
| 450 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
---|
| 451 | |
---|
| 452 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
---|
| 453 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
---|
| 454 | |
---|
[434] | 455 | uint32_t m_cpt_get; |
---|
| 456 | uint32_t m_cpt_put; |
---|
| 457 | |
---|
[331] | 458 | size_t m_prev_count; |
---|
| 459 | |
---|
| 460 | protected: |
---|
| 461 | |
---|
| 462 | SC_HAS_PROCESS(VciMemCache); |
---|
| 463 | |
---|
| 464 | public: |
---|
[385] | 465 | sc_in<bool> p_clk; |
---|
| 466 | sc_in<bool> p_resetn; |
---|
| 467 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt; |
---|
| 468 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; |
---|
[468] | 469 | soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; |
---|
| 470 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; |
---|
| 471 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; |
---|
[331] | 472 | |
---|
| 473 | VciMemCache( |
---|
| 474 | sc_module_name name, // Instance Name |
---|
[434] | 475 | const soclib::common::MappingTable &mtp, // Mapping table INT network |
---|
| 476 | const soclib::common::MappingTable &mtx, // Mapping table RAM network |
---|
| 477 | const soclib::common::IntTab &srcid_x, // global index RAM network |
---|
| 478 | const soclib::common::IntTab &tgtid_d, // global index INT network |
---|
| 479 | const size_t cc_global_id, // global index CC network |
---|
[504] | 480 | const size_t x_width, // X width in platform |
---|
| 481 | const size_t y_width, // Y width in platform |
---|
[346] | 482 | const size_t nways, // Number of ways per set |
---|
| 483 | const size_t nsets, // Number of sets |
---|
| 484 | const size_t nwords, // Number of words per line |
---|
[434] | 485 | const size_t max_copies, // max number of copies |
---|
[395] | 486 | const size_t heap_size=HEAP_ENTRIES, |
---|
| 487 | const size_t trt_lines=TRT_ENTRIES, |
---|
| 488 | const size_t upt_lines=UPT_ENTRIES, |
---|
[468] | 489 | const size_t ivt_lines=IVT_ENTRIES, |
---|
[346] | 490 | const size_t debug_start_cycle=0, |
---|
| 491 | const bool debug_ok=false ); |
---|
[331] | 492 | |
---|
| 493 | ~VciMemCache(); |
---|
| 494 | |
---|
[504] | 495 | void print_stats(bool activity_counters, bool stats); |
---|
[331] | 496 | void print_trace(); |
---|
[449] | 497 | void cache_monitor(addr_t addr); |
---|
[385] | 498 | void start_monitor(addr_t addr, addr_t length); |
---|
[331] | 499 | void stop_monitor(); |
---|
| 500 | |
---|
| 501 | private: |
---|
| 502 | |
---|
| 503 | void transition(); |
---|
| 504 | void genMoore(); |
---|
[449] | 505 | void check_monitor(addr_t addr, data_t data, bool read); |
---|
[504] | 506 | uint32_t req_distance(uint32_t req_srcid); |
---|
| 507 | bool is_local_req(uint32_t req_srcid); |
---|
[331] | 508 | |
---|
| 509 | // Component attributes |
---|
[434] | 510 | std::list<soclib::common::Segment> m_seglist; // segments allocated |
---|
[346] | 511 | size_t m_nseg; // number of segments |
---|
| 512 | soclib::common::Segment **m_seg; // array of segments pointers |
---|
[434] | 513 | size_t m_seg_config; // config segment index |
---|
| 514 | const size_t m_srcid_x; // global index on RAM network |
---|
[346] | 515 | const size_t m_initiators; // Number of initiators |
---|
| 516 | const size_t m_heap_size; // Size of the heap |
---|
| 517 | const size_t m_ways; // Number of ways in a set |
---|
| 518 | const size_t m_sets; // Number of cache sets |
---|
| 519 | const size_t m_words; // Number of words in a line |
---|
| 520 | const size_t m_cc_global_id; // global_index on cc network |
---|
[504] | 521 | const size_t m_xwidth; // number of x bits in platform |
---|
| 522 | const size_t m_ywidth; // number of y bits in platform |
---|
[346] | 523 | size_t m_debug_start_cycle; |
---|
| 524 | bool m_debug_ok; |
---|
| 525 | uint32_t m_trt_lines; |
---|
| 526 | TransactionTab m_trt; // xram transaction table |
---|
| 527 | uint32_t m_upt_lines; |
---|
[468] | 528 | UpdateTab m_upt; // pending update |
---|
| 529 | UpdateTab m_ivt; // pending invalidate |
---|
[346] | 530 | CacheDirectory m_cache_directory; // data cache directory |
---|
| 531 | CacheData m_cache_data; // data array[set][way][word] |
---|
| 532 | HeapDirectory m_heap; // heap for copies |
---|
| 533 | size_t m_max_copies; // max number of copies in heap |
---|
[331] | 534 | GenericLLSCGlobalTable |
---|
[434] | 535 | < 32 , // number of slots |
---|
| 536 | 4096, // number of processors in the system |
---|
| 537 | 8000, // registration life (# of LL operations) |
---|
| 538 | addr_t > m_llsc_table; // ll/sc registration table |
---|
[331] | 539 | |
---|
| 540 | // adress masks |
---|
[385] | 541 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
---|
| 542 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
---|
| 543 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
---|
| 544 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
---|
[331] | 545 | |
---|
| 546 | // broadcast address |
---|
[395] | 547 | uint32_t m_broadcast_boundaries; |
---|
[331] | 548 | |
---|
| 549 | // Fifo between TGT_CMD fsm and READ fsm |
---|
[385] | 550 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
---|
[331] | 551 | GenericFifo<size_t> m_cmd_read_length_fifo; |
---|
| 552 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
---|
| 553 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
---|
| 554 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
---|
| 555 | |
---|
| 556 | // Fifo between TGT_CMD fsm and WRITE fsm |
---|
[385] | 557 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
---|
[331] | 558 | GenericFifo<bool> m_cmd_write_eop_fifo; |
---|
| 559 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
---|
| 560 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
---|
| 561 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
---|
| 562 | GenericFifo<data_t> m_cmd_write_data_fifo; |
---|
| 563 | GenericFifo<be_t> m_cmd_write_be_fifo; |
---|
| 564 | |
---|
| 565 | // Fifo between TGT_CMD fsm and CAS fsm |
---|
[385] | 566 | GenericFifo<addr_t> m_cmd_cas_addr_fifo; |
---|
[331] | 567 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
---|
| 568 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
---|
| 569 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
---|
| 570 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
---|
| 571 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
---|
| 572 | |
---|
[403] | 573 | // Fifo between CC_RECEIVE fsm and CLEANUP fsm |
---|
[331] | 574 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
---|
| 575 | |
---|
[403] | 576 | // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm |
---|
[331] | 577 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
---|
| 578 | |
---|
[430] | 579 | // Buffer between TGT_CMD fsm and TGT_RSP fsm |
---|
| 580 | // (segmentation violation response request) |
---|
| 581 | sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req; |
---|
[434] | 582 | |
---|
| 583 | sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata; |
---|
| 584 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error; |
---|
[430] | 585 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid; |
---|
| 586 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid; |
---|
| 587 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid; |
---|
[331] | 588 | |
---|
[434] | 589 | sc_signal<addr_t> r_tgt_cmd_config_addr; |
---|
| 590 | sc_signal<size_t> r_tgt_cmd_config_cmd; |
---|
| 591 | |
---|
[489] | 592 | ////////////////////////////////////////////////// |
---|
| 593 | // Registers controlled by the TGT_CMD fsm |
---|
| 594 | ////////////////////////////////////////////////// |
---|
| 595 | |
---|
| 596 | sc_signal<int> r_tgt_cmd_fsm; |
---|
| 597 | |
---|
[331] | 598 | /////////////////////////////////////////////////////// |
---|
[434] | 599 | // Registers controlled by the CONFIG fsm |
---|
| 600 | /////////////////////////////////////////////////////// |
---|
| 601 | |
---|
[489] | 602 | sc_signal<int> r_config_fsm; // FSM state |
---|
| 603 | sc_signal<bool> r_config_lock; // lock protecting exclusive access |
---|
| 604 | sc_signal<int> r_config_cmd; // config request type |
---|
| 605 | sc_signal<addr_t> r_config_address; // target buffer physical address |
---|
| 606 | sc_signal<size_t> r_config_srcid; // config request srcid |
---|
| 607 | sc_signal<size_t> r_config_trdid; // config request trdid |
---|
| 608 | sc_signal<size_t> r_config_pktid; // config request pktid |
---|
| 609 | sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled |
---|
| 610 | sc_signal<size_t> r_config_rsp_lines; // number of lines not completed |
---|
| 611 | sc_signal<size_t> r_config_dir_way; // DIR: selected way |
---|
| 612 | sc_signal<bool> r_config_dir_lock; // DIR: locked entry |
---|
| 613 | sc_signal<size_t> r_config_dir_count; // DIR: number of copies |
---|
| 614 | sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) |
---|
| 615 | sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID |
---|
| 616 | sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type |
---|
| 617 | sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP |
---|
| 618 | sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP |
---|
| 619 | sc_signal<size_t> r_config_trt_index; // selected entry in TRT |
---|
| 620 | sc_signal<size_t> r_config_ivt_index; // selected entry in IVT |
---|
[439] | 621 | |
---|
[489] | 622 | // Buffer between CONFIG fsm and IXR_CMD fsm |
---|
| 623 | sc_signal<bool> r_config_to_ixr_cmd_req; // valid request |
---|
| 624 | sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index |
---|
[434] | 625 | |
---|
| 626 | // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) |
---|
| 627 | sc_signal<bool> r_config_to_tgt_rsp_req; // valid request |
---|
| 628 | sc_signal<bool> r_config_to_tgt_rsp_error; // error response |
---|
| 629 | sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 630 | sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 631 | sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 632 | |
---|
| 633 | // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) |
---|
| 634 | sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request |
---|
| 635 | sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request |
---|
[439] | 636 | sc_signal<addr_t> r_config_to_cc_send_nline; // line index |
---|
[434] | 637 | sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index |
---|
[439] | 638 | GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 639 | GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid |
---|
[434] | 640 | |
---|
| 641 | /////////////////////////////////////////////////////// |
---|
[331] | 642 | // Registers controlled by the READ fsm |
---|
| 643 | /////////////////////////////////////////////////////// |
---|
| 644 | |
---|
[489] | 645 | sc_signal<int> r_read_fsm; // FSM state |
---|
| 646 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
| 647 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
| 648 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
| 649 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
| 650 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
| 651 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
| 652 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
| 653 | sc_signal<size_t> r_read_count; // number of copies |
---|
| 654 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
| 655 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
| 656 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 657 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 658 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 659 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
| 660 | sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table |
---|
[331] | 661 | |
---|
[489] | 662 | // Buffer between READ fsm and IXR_CMD fsm |
---|
| 663 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 664 | sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index |
---|
[331] | 665 | |
---|
| 666 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
[489] | 667 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 668 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 669 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 670 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 671 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 672 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 673 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
| 674 | sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
[331] | 675 | |
---|
| 676 | /////////////////////////////////////////////////////////////// |
---|
| 677 | // Registers controlled by the WRITE fsm |
---|
| 678 | /////////////////////////////////////////////////////////////// |
---|
| 679 | |
---|
[489] | 680 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 681 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 682 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 683 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 684 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 685 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 686 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 687 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
| 688 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
| 689 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
| 690 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 691 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 692 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 693 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 694 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
| 695 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 696 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 697 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 698 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 699 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 700 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 701 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 702 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 703 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
[527] | 704 | sc_signal<data_t> r_write_sc_key; // sc command key |
---|
[331] | 705 | |
---|
| 706 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 707 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 708 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 709 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 710 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 711 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
| 712 | |
---|
[489] | 713 | // Buffer between WRITE fsm and IXR_CMD fsm |
---|
| 714 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 715 | sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index |
---|
[331] | 716 | |
---|
| 717 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 718 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
| 719 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
| 720 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
| 721 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
| 722 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
| 723 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
| 724 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
| 725 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
| 726 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 727 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 728 | |
---|
[331] | 729 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
| 730 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
| 731 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
| 732 | |
---|
| 733 | ///////////////////////////////////////////////////////// |
---|
| 734 | // Registers controlled by MULTI_ACK fsm |
---|
| 735 | ////////////////////////////////////////////////////////// |
---|
| 736 | |
---|
| 737 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
| 738 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
| 739 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
| 740 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
---|
| 741 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
| 742 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
| 743 | |
---|
| 744 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
[483] | 745 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
[331] | 746 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 747 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 748 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 749 | |
---|
| 750 | /////////////////////////////////////////////////////// |
---|
| 751 | // Registers controlled by CLEANUP fsm |
---|
| 752 | /////////////////////////////////////////////////////// |
---|
| 753 | |
---|
| 754 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 755 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 756 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
| 757 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
| 758 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 759 | |
---|
| 760 | |
---|
| 761 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 762 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
| 763 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 764 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 765 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 766 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 767 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 768 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
| 769 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 770 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 771 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 772 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 773 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 774 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 775 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 776 | |
---|
[434] | 777 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp |
---|
[331] | 778 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 779 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 780 | |
---|
[434] | 781 | sc_signal<bool> r_cleanup_need_rsp; // write response required |
---|
| 782 | sc_signal<bool> r_cleanup_need_ack; // config acknowledge required |
---|
| 783 | |
---|
[331] | 784 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 785 | |
---|
| 786 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
[483] | 787 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
[331] | 788 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 789 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 790 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
| 791 | |
---|
| 792 | /////////////////////////////////////////////////////// |
---|
| 793 | // Registers controlled by CAS fsm |
---|
| 794 | /////////////////////////////////////////////////////// |
---|
| 795 | |
---|
[489] | 796 | sc_signal<int> r_cas_fsm; // FSM state |
---|
| 797 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
| 798 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
| 799 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
| 800 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
| 801 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
| 802 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
| 803 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
| 804 | sc_signal<size_t> r_cas_count; // number of copies |
---|
| 805 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
| 806 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
| 807 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
| 808 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
| 809 | sc_signal<size_t> r_cas_way; // way in directory |
---|
| 810 | sc_signal<size_t> r_cas_set; // set in directory |
---|
| 811 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
| 812 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
| 813 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
| 814 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
[331] | 815 | |
---|
[489] | 816 | // Buffer between CAS fsm and IXR_CMD fsm |
---|
[331] | 817 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
[489] | 818 | sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index |
---|
[331] | 819 | |
---|
| 820 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
| 821 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
| 822 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
| 823 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 824 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 825 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 826 | |
---|
| 827 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
| 828 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
| 829 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
| 830 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
| 831 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
| 832 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
| 833 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
| 834 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
| 835 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
| 836 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 837 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 838 | |
---|
[331] | 839 | //////////////////////////////////////////////////// |
---|
| 840 | // Registers controlled by the IXR_RSP fsm |
---|
| 841 | //////////////////////////////////////////////////// |
---|
| 842 | |
---|
[489] | 843 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 844 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 845 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
[331] | 846 | |
---|
[489] | 847 | // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) |
---|
| 848 | sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit |
---|
| 849 | |
---|
[331] | 850 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
[489] | 851 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry |
---|
[331] | 852 | |
---|
| 853 | //////////////////////////////////////////////////// |
---|
| 854 | // Registers controlled by the XRAM_RSP fsm |
---|
| 855 | //////////////////////////////////////////////////// |
---|
| 856 | |
---|
| 857 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 858 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 859 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 860 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 861 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 862 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 863 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 864 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 865 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 866 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 867 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
| 868 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 869 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 870 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 871 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
[468] | 872 | sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index |
---|
[331] | 873 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
| 874 | |
---|
| 875 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
| 876 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 877 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 878 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 879 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 880 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 881 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 882 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
| 883 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
[385] | 884 | sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
[331] | 885 | |
---|
| 886 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
---|
| 887 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
---|
| 888 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
---|
| 889 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
---|
| 890 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
---|
| 891 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
| 892 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
---|
[385] | 893 | |
---|
[489] | 894 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm |
---|
[331] | 895 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
[489] | 896 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index |
---|
[331] | 897 | |
---|
| 898 | //////////////////////////////////////////////////// |
---|
| 899 | // Registers controlled by the IXR_CMD fsm |
---|
| 900 | //////////////////////////////////////////////////// |
---|
| 901 | |
---|
| 902 | sc_signal<int> r_ixr_cmd_fsm; |
---|
[489] | 903 | sc_signal<size_t> r_ixr_cmd_word; // word index for a put |
---|
| 904 | sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value |
---|
| 905 | sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM |
---|
| 906 | sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer |
---|
| 907 | sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) |
---|
[331] | 908 | |
---|
| 909 | //////////////////////////////////////////////////// |
---|
| 910 | // Registers controlled by TGT_RSP fsm |
---|
| 911 | //////////////////////////////////////////////////// |
---|
| 912 | |
---|
| 913 | sc_signal<int> r_tgt_rsp_fsm; |
---|
| 914 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
[362] | 915 | sc_signal<bool> r_tgt_rsp_key_sent; |
---|
[331] | 916 | |
---|
| 917 | //////////////////////////////////////////////////// |
---|
| 918 | // Registers controlled by CC_SEND fsm |
---|
| 919 | //////////////////////////////////////////////////// |
---|
| 920 | |
---|
| 921 | sc_signal<int> r_cc_send_fsm; |
---|
| 922 | sc_signal<size_t> r_cc_send_cpt; |
---|
| 923 | sc_signal<bool> r_cc_send_inst; |
---|
| 924 | |
---|
| 925 | //////////////////////////////////////////////////// |
---|
| 926 | // Registers controlled by CC_RECEIVE fsm |
---|
| 927 | //////////////////////////////////////////////////// |
---|
| 928 | |
---|
| 929 | sc_signal<int> r_cc_receive_fsm; |
---|
| 930 | |
---|
| 931 | //////////////////////////////////////////////////// |
---|
| 932 | // Registers controlled by ALLOC_DIR fsm |
---|
| 933 | //////////////////////////////////////////////////// |
---|
| 934 | |
---|
| 935 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 936 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
| 937 | |
---|
| 938 | //////////////////////////////////////////////////// |
---|
| 939 | // Registers controlled by ALLOC_TRT fsm |
---|
| 940 | //////////////////////////////////////////////////// |
---|
| 941 | |
---|
| 942 | sc_signal<int> r_alloc_trt_fsm; |
---|
| 943 | |
---|
| 944 | //////////////////////////////////////////////////// |
---|
| 945 | // Registers controlled by ALLOC_UPT fsm |
---|
| 946 | //////////////////////////////////////////////////// |
---|
| 947 | |
---|
| 948 | sc_signal<int> r_alloc_upt_fsm; |
---|
| 949 | |
---|
| 950 | //////////////////////////////////////////////////// |
---|
[468] | 951 | // Registers controlled by ALLOC_IVT fsm |
---|
| 952 | //////////////////////////////////////////////////// |
---|
| 953 | |
---|
| 954 | sc_signal<int> r_alloc_ivt_fsm; |
---|
| 955 | |
---|
| 956 | //////////////////////////////////////////////////// |
---|
[331] | 957 | // Registers controlled by ALLOC_HEAP fsm |
---|
| 958 | //////////////////////////////////////////////////// |
---|
| 959 | |
---|
| 960 | sc_signal<int> r_alloc_heap_fsm; |
---|
| 961 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
---|
| 962 | }; // end class VciMemCache |
---|
| 963 | |
---|
| 964 | }} |
---|
| 965 | |
---|
| 966 | #endif |
---|
| 967 | |
---|
| 968 | // Local Variables: |
---|
| 969 | // tab-width: 2 |
---|
| 970 | // c-basic-offset: 2 |
---|
| 971 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 972 | // indent-tabs-mode: nil |
---|
| 973 | // End: |
---|
| 974 | |
---|
| 975 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
---|
| 976 | |
---|