1 | /* -*- c++ -*- |
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2 | * File : vci_mem_cache.h |
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3 | * Date : 26/10/2008 |
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4 | * Copyright : UPMC / LIP6 |
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5 | * Authors : Alain Greiner / Eric Guthmuller |
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6 | * |
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7 | * SOCLIB_LGPL_HEADER_BEGIN |
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8 | * |
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9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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10 | * |
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11 | * SoCLib is free software; you can redistribute it and/or modify it |
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12 | * under the terms of the GNU Lesser General Public License as published |
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13 | * by the Free Software Foundation; version 2.1 of the License. |
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14 | * |
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15 | * SoCLib is distributed in the hope that it will be useful, but |
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16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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18 | * Lesser General Public License for more details. |
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19 | * |
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20 | * You should have received a copy of the GNU Lesser General Public |
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21 | * License along with SoCLib; if not, write to the Free Software |
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22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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23 | * 02110-1301 USA |
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24 | * |
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25 | * SOCLIB_LGPL_HEADER_END |
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26 | * |
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27 | * Maintainers: alain.greiner@lip6.fr |
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28 | * eric.guthmuller@polytechnique.edu |
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29 | * cesar.fuguet-tortolero@lip6.fr |
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30 | * alexandre.joannou@lip6.fr |
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31 | */ |
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32 | |
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33 | #ifndef SOCLIB_CABA_MEM_CACHE_H |
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34 | #define SOCLIB_CABA_MEM_CACHE_H |
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35 | |
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36 | #include <inttypes.h> |
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37 | #include <systemc> |
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38 | #include <list> |
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39 | #include <cassert> |
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40 | #include "arithmetics.h" |
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41 | #include "alloc_elems.h" |
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42 | #include "caba_base_module.h" |
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43 | #include "vci_target.h" |
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44 | #include "vci_initiator.h" |
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45 | #include "generic_fifo.h" |
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46 | #include "mapping_table.h" |
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47 | #include "int_tab.h" |
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48 | #include "generic_llsc_global_table.h" |
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49 | #include "mem_cache_directory.h" |
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50 | #include "xram_transaction.h" |
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51 | #include "update_tab.h" |
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52 | #include "dspin_interface.h" |
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53 | #include "dspin_dhccp_param.h" |
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54 | |
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55 | #define TRT_ENTRIES 4 // Number of entries in TRT |
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56 | #define UPT_ENTRIES 4 // Number of entries in UPT |
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57 | #define IVT_ENTRIES 4 // Number of entries in IVT |
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58 | #define HEAP_ENTRIES 1024 // Number of entries in HEAP |
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59 | |
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60 | namespace soclib { namespace caba { |
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61 | |
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62 | using namespace sc_core; |
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63 | |
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64 | template<typename vci_param_int, |
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65 | typename vci_param_ext, |
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66 | size_t dspin_in_width, |
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67 | size_t dspin_out_width> |
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68 | class VciMemCache |
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69 | : public soclib::caba::BaseModule |
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70 | { |
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71 | typedef typename vci_param_int::fast_addr_t addr_t; |
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72 | typedef typename sc_dt::sc_uint<64> wide_data_t; |
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73 | typedef uint32_t data_t; |
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74 | typedef uint32_t tag_t; |
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75 | typedef uint32_t be_t; |
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76 | typedef uint32_t copy_t; |
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77 | |
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78 | /* States of the TGT_CMD fsm */ |
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79 | enum tgt_cmd_fsm_state_e |
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80 | { |
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81 | TGT_CMD_IDLE, |
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82 | TGT_CMD_ERROR, |
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83 | TGT_CMD_READ, |
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84 | TGT_CMD_WRITE, |
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85 | TGT_CMD_CAS, |
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86 | TGT_CMD_CONFIG |
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87 | }; |
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88 | |
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89 | /* States of the TGT_RSP fsm */ |
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90 | enum tgt_rsp_fsm_state_e |
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91 | { |
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92 | TGT_RSP_CONFIG_IDLE, |
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93 | TGT_RSP_TGT_CMD_IDLE, |
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94 | TGT_RSP_READ_IDLE, |
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95 | TGT_RSP_WRITE_IDLE, |
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96 | TGT_RSP_CAS_IDLE, |
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97 | TGT_RSP_XRAM_IDLE, |
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98 | TGT_RSP_MULTI_ACK_IDLE, |
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99 | TGT_RSP_CLEANUP_IDLE, |
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100 | TGT_RSP_CONFIG, |
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101 | TGT_RSP_TGT_CMD, |
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102 | TGT_RSP_READ, |
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103 | TGT_RSP_WRITE, |
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104 | TGT_RSP_CAS, |
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105 | TGT_RSP_XRAM, |
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106 | TGT_RSP_MULTI_ACK, |
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107 | TGT_RSP_CLEANUP |
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108 | }; |
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109 | |
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110 | /* States of the DSPIN_TGT fsm */ |
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111 | enum cc_receive_fsm_state_e |
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112 | { |
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113 | CC_RECEIVE_IDLE, |
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114 | CC_RECEIVE_CLEANUP, |
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115 | CC_RECEIVE_CLEANUP_EOP, |
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116 | CC_RECEIVE_MULTI_ACK |
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117 | }; |
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118 | |
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119 | /* States of the CC_SEND fsm */ |
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120 | enum cc_send_fsm_state_e |
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121 | { |
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122 | CC_SEND_CONFIG_IDLE, |
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123 | CC_SEND_XRAM_RSP_IDLE, |
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124 | CC_SEND_WRITE_IDLE, |
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125 | CC_SEND_CAS_IDLE, |
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126 | CC_SEND_CONFIG_INVAL_HEADER, |
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127 | CC_SEND_CONFIG_INVAL_NLINE, |
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128 | CC_SEND_CONFIG_BRDCAST_HEADER, |
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129 | CC_SEND_CONFIG_BRDCAST_NLINE, |
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130 | CC_SEND_XRAM_RSP_BRDCAST_HEADER, |
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131 | CC_SEND_XRAM_RSP_BRDCAST_NLINE, |
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132 | CC_SEND_XRAM_RSP_INVAL_HEADER, |
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133 | CC_SEND_XRAM_RSP_INVAL_NLINE, |
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134 | CC_SEND_WRITE_BRDCAST_HEADER, |
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135 | CC_SEND_WRITE_BRDCAST_NLINE, |
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136 | CC_SEND_WRITE_UPDT_HEADER, |
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137 | CC_SEND_WRITE_UPDT_NLINE, |
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138 | CC_SEND_WRITE_UPDT_DATA, |
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139 | CC_SEND_CAS_BRDCAST_HEADER, |
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140 | CC_SEND_CAS_BRDCAST_NLINE, |
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141 | CC_SEND_CAS_UPDT_HEADER, |
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142 | CC_SEND_CAS_UPDT_NLINE, |
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143 | CC_SEND_CAS_UPDT_DATA, |
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144 | CC_SEND_CAS_UPDT_DATA_HIGH |
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145 | }; |
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146 | |
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147 | /* States of the MULTI_ACK fsm */ |
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148 | enum multi_ack_fsm_state_e |
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149 | { |
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150 | MULTI_ACK_IDLE, |
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151 | MULTI_ACK_UPT_LOCK, |
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152 | MULTI_ACK_UPT_CLEAR, |
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153 | MULTI_ACK_WRITE_RSP |
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154 | }; |
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155 | |
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156 | /* States of the CONFIG fsm */ |
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157 | enum config_fsm_state_e |
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158 | { |
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159 | CONFIG_IDLE, |
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160 | CONFIG_LOOP, |
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161 | CONFIG_WAIT, |
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162 | CONFIG_RSP, |
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163 | CONFIG_DIR_REQ, |
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164 | CONFIG_DIR_ACCESS, |
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165 | CONFIG_IVT_LOCK, |
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166 | CONFIG_BC_SEND, |
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167 | CONFIG_INVAL_SEND, |
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168 | CONFIG_HEAP_REQ, |
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169 | CONFIG_HEAP_SCAN, |
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170 | CONFIG_HEAP_LAST, |
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171 | CONFIG_TRT_LOCK, |
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172 | CONFIG_TRT_SET, |
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173 | CONFIG_PUT_REQ |
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174 | }; |
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175 | |
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176 | /* States of the READ fsm */ |
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177 | enum read_fsm_state_e |
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178 | { |
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179 | READ_IDLE, |
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180 | READ_DIR_REQ, |
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181 | READ_DIR_LOCK, |
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182 | READ_DIR_HIT, |
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183 | READ_HEAP_REQ, |
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184 | READ_HEAP_LOCK, |
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185 | READ_HEAP_WRITE, |
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186 | READ_HEAP_ERASE, |
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187 | READ_HEAP_LAST, |
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188 | READ_RSP, |
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189 | READ_TRT_LOCK, |
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190 | READ_TRT_SET, |
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191 | READ_TRT_REQ |
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192 | }; |
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193 | |
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194 | /* States of the WRITE fsm */ |
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195 | enum write_fsm_state_e |
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196 | { |
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197 | WRITE_IDLE, |
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198 | WRITE_NEXT, |
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199 | WRITE_DIR_REQ, |
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200 | WRITE_DIR_LOCK, |
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201 | WRITE_DIR_HIT, |
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202 | WRITE_UPT_LOCK, |
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203 | WRITE_UPT_HEAP_LOCK, |
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204 | WRITE_UPT_REQ, |
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205 | WRITE_UPT_NEXT, |
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206 | WRITE_UPT_DEC, |
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207 | WRITE_RSP, |
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208 | WRITE_MISS_TRT_LOCK, |
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209 | WRITE_MISS_TRT_DATA, |
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210 | WRITE_MISS_TRT_SET, |
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211 | WRITE_MISS_XRAM_REQ, |
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212 | WRITE_BC_DIR_READ, |
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213 | WRITE_BC_TRT_LOCK, |
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214 | WRITE_BC_IVT_LOCK, |
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215 | WRITE_BC_DIR_INVAL, |
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216 | WRITE_BC_CC_SEND, |
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217 | WRITE_BC_XRAM_REQ, |
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218 | WRITE_WAIT |
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219 | }; |
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220 | |
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221 | /* States of the IXR_RSP fsm */ |
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222 | enum ixr_rsp_fsm_state_e |
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223 | { |
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224 | IXR_RSP_IDLE, |
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225 | IXR_RSP_TRT_ERASE, |
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226 | IXR_RSP_TRT_READ |
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227 | }; |
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228 | |
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229 | /* States of the XRAM_RSP fsm */ |
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230 | enum xram_rsp_fsm_state_e |
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231 | { |
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232 | XRAM_RSP_IDLE, |
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233 | XRAM_RSP_TRT_COPY, |
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234 | XRAM_RSP_TRT_DIRTY, |
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235 | XRAM_RSP_DIR_LOCK, |
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236 | XRAM_RSP_DIR_UPDT, |
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237 | XRAM_RSP_DIR_RSP, |
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238 | XRAM_RSP_IVT_LOCK, |
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239 | XRAM_RSP_INVAL_WAIT, |
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240 | XRAM_RSP_INVAL, |
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241 | XRAM_RSP_WRITE_DIRTY, |
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242 | XRAM_RSP_HEAP_REQ, |
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243 | XRAM_RSP_HEAP_ERASE, |
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244 | XRAM_RSP_HEAP_LAST, |
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245 | XRAM_RSP_ERROR_ERASE, |
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246 | XRAM_RSP_ERROR_RSP |
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247 | }; |
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248 | |
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249 | /* States of the IXR_CMD fsm */ |
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250 | enum ixr_cmd_fsm_state_e |
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251 | { |
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252 | IXR_CMD_READ_IDLE, |
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253 | IXR_CMD_WRITE_IDLE, |
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254 | IXR_CMD_CAS_IDLE, |
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255 | IXR_CMD_XRAM_IDLE, |
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256 | IXR_CMD_CONFIG_IDLE, |
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257 | IXR_CMD_READ_TRT, |
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258 | IXR_CMD_WRITE_TRT, |
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259 | IXR_CMD_CAS_TRT, |
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260 | IXR_CMD_XRAM_TRT, |
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261 | IXR_CMD_CONFIG_TRT, |
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262 | IXR_CMD_READ_SEND, |
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263 | IXR_CMD_WRITE_SEND, |
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264 | IXR_CMD_CAS_SEND, |
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265 | IXR_CMD_XRAM_SEND, |
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266 | IXR_CMD_CONFIG_SEND |
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267 | }; |
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268 | |
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269 | /* States of the CAS fsm */ |
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270 | enum cas_fsm_state_e |
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271 | { |
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272 | CAS_IDLE, |
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273 | CAS_DIR_REQ, |
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274 | CAS_DIR_LOCK, |
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275 | CAS_DIR_HIT_READ, |
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276 | CAS_DIR_HIT_COMPARE, |
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277 | CAS_DIR_HIT_WRITE, |
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278 | CAS_UPT_LOCK, |
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279 | CAS_UPT_HEAP_LOCK, |
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280 | CAS_UPT_REQ, |
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281 | CAS_UPT_NEXT, |
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282 | CAS_BC_TRT_LOCK, |
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283 | CAS_BC_IVT_LOCK, |
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284 | CAS_BC_DIR_INVAL, |
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285 | CAS_BC_CC_SEND, |
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286 | CAS_BC_XRAM_REQ, |
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287 | CAS_RSP_FAIL, |
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288 | CAS_RSP_SUCCESS, |
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289 | CAS_MISS_TRT_LOCK, |
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290 | CAS_MISS_TRT_SET, |
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291 | CAS_MISS_XRAM_REQ, |
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292 | CAS_WAIT |
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293 | }; |
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294 | |
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295 | /* States of the CLEANUP fsm */ |
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296 | enum cleanup_fsm_state_e |
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297 | { |
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298 | CLEANUP_IDLE, |
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299 | CLEANUP_GET_NLINE, |
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300 | CLEANUP_DIR_REQ, |
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301 | CLEANUP_DIR_LOCK, |
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302 | CLEANUP_DIR_WRITE, |
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303 | CLEANUP_HEAP_REQ, |
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304 | CLEANUP_HEAP_LOCK, |
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305 | CLEANUP_HEAP_SEARCH, |
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306 | CLEANUP_HEAP_CLEAN, |
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307 | CLEANUP_HEAP_FREE, |
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308 | CLEANUP_IVT_LOCK, |
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309 | CLEANUP_IVT_DECREMENT, |
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310 | CLEANUP_IVT_CLEAR, |
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311 | CLEANUP_WRITE_RSP, |
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312 | CLEANUP_SEND_CLACK |
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313 | }; |
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314 | |
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315 | /* States of the ALLOC_DIR fsm */ |
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316 | enum alloc_dir_fsm_state_e |
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317 | { |
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318 | ALLOC_DIR_RESET, |
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319 | ALLOC_DIR_CONFIG, |
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320 | ALLOC_DIR_READ, |
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321 | ALLOC_DIR_WRITE, |
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322 | ALLOC_DIR_CAS, |
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323 | ALLOC_DIR_CLEANUP, |
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324 | ALLOC_DIR_XRAM_RSP |
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325 | }; |
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326 | |
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327 | /* States of the ALLOC_TRT fsm */ |
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328 | enum alloc_trt_fsm_state_e |
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329 | { |
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330 | ALLOC_TRT_READ, |
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331 | ALLOC_TRT_WRITE, |
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332 | ALLOC_TRT_CAS, |
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333 | ALLOC_TRT_XRAM_RSP, |
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334 | ALLOC_TRT_IXR_RSP, |
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335 | ALLOC_TRT_CONFIG, |
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336 | ALLOC_TRT_IXR_CMD |
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337 | }; |
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338 | |
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339 | /* States of the ALLOC_UPT fsm */ |
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340 | enum alloc_upt_fsm_state_e |
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341 | { |
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342 | ALLOC_UPT_WRITE, |
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343 | ALLOC_UPT_CAS, |
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344 | ALLOC_UPT_MULTI_ACK |
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345 | }; |
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346 | |
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347 | /* States of the ALLOC_IVT fsm */ |
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348 | enum alloc_ivt_fsm_state_e |
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349 | { |
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350 | ALLOC_IVT_WRITE, |
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351 | ALLOC_IVT_XRAM_RSP, |
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352 | ALLOC_IVT_CLEANUP, |
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353 | ALLOC_IVT_CAS, |
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354 | ALLOC_IVT_CONFIG |
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355 | }; |
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356 | |
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357 | /* States of the ALLOC_HEAP fsm */ |
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358 | enum alloc_heap_fsm_state_e |
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359 | { |
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360 | ALLOC_HEAP_RESET, |
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361 | ALLOC_HEAP_READ, |
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362 | ALLOC_HEAP_WRITE, |
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363 | ALLOC_HEAP_CAS, |
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364 | ALLOC_HEAP_CLEANUP, |
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365 | ALLOC_HEAP_XRAM_RSP, |
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366 | ALLOC_HEAP_CONFIG |
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367 | }; |
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368 | |
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369 | /* transaction type, pktid field */ |
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370 | enum transaction_type_e |
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371 | { |
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372 | // b3 unused |
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373 | // b2 READ / NOT READ |
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374 | // Si READ |
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375 | // b1 DATA / INS |
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376 | // b0 UNC / MISS |
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377 | // Si NOT READ |
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378 | // b1 accÚs table llsc type SW / other |
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379 | // b2 WRITE/CAS/LL/SC |
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380 | TYPE_READ_DATA_UNC = 0x0, |
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381 | TYPE_READ_DATA_MISS = 0x1, |
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382 | TYPE_READ_INS_UNC = 0x2, |
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383 | TYPE_READ_INS_MISS = 0x3, |
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384 | TYPE_WRITE = 0x4, |
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385 | TYPE_CAS = 0x5, |
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386 | TYPE_LL = 0x6, |
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387 | TYPE_SC = 0x7 |
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388 | }; |
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389 | |
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390 | /* SC return values */ |
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391 | enum sc_status_type_e |
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392 | { |
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393 | SC_SUCCESS = 0x00000000, |
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394 | SC_FAIL = 0x00000001 |
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395 | }; |
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396 | |
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397 | // debug variables |
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398 | bool m_debug; |
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399 | bool m_debug_previous_valid; |
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400 | size_t m_debug_previous_count; |
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401 | bool m_debug_previous_dirty; |
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402 | data_t * m_debug_previous_data; |
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403 | data_t * m_debug_data; |
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404 | |
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405 | // instrumentation counters |
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406 | uint32_t m_cpt_cycles; // Counter of cycles |
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407 | |
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408 | uint32_t m_cpt_read; // Number of READ transactions |
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409 | uint32_t m_cpt_read_remote; // number of remote READ transactions |
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410 | uint32_t m_cpt_read_flits; // number of flits for READs |
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411 | uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs |
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412 | |
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413 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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414 | |
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415 | uint32_t m_cpt_write; // Number of WRITE transactions |
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416 | uint32_t m_cpt_write_remote; // number of remote WRITE transactions |
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417 | uint32_t m_cpt_write_flits; // number of flits for WRITEs |
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418 | uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs |
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419 | |
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420 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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421 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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422 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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423 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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424 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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425 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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426 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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427 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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428 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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429 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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430 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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431 | uint32_t m_cpt_ll; // Number of LL transactions |
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432 | uint32_t m_cpt_sc; // Number of SC transactions |
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433 | uint32_t m_cpt_cas; // Number of CAS transactions |
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434 | |
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435 | uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs |
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436 | |
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437 | uint32_t m_cpt_update_flits; // Number of flits for UPDATEs |
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438 | uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs |
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439 | |
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440 | uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs |
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441 | |
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442 | uint32_t m_cpt_get; |
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443 | |
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444 | uint32_t m_cpt_put; |
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445 | |
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446 | size_t m_prev_count; |
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447 | |
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448 | protected: |
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449 | |
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450 | SC_HAS_PROCESS(VciMemCache); |
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451 | |
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452 | public: |
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453 | sc_in<bool> p_clk; |
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454 | sc_in<bool> p_resetn; |
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455 | soclib::caba::VciTarget<vci_param_int> p_vci_tgt; |
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456 | soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; |
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457 | soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m; |
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458 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p; |
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459 | soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; |
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460 | |
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461 | VciMemCache( |
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462 | sc_module_name name, // Instance Name |
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463 | const soclib::common::MappingTable &mtp, // Mapping table INT network |
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464 | const soclib::common::MappingTable &mtx, // Mapping table RAM network |
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465 | const soclib::common::IntTab &srcid_x, // global index RAM network |
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466 | const soclib::common::IntTab &tgtid_d, // global index INT network |
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467 | const size_t cc_global_id, // global index CC network |
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468 | const size_t nways, // Number of ways per set |
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469 | const size_t nsets, // Number of sets |
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470 | const size_t nwords, // Number of words per line |
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471 | const size_t max_copies, // max number of copies |
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472 | const size_t heap_size=HEAP_ENTRIES, |
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473 | const size_t trt_lines=TRT_ENTRIES, |
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474 | const size_t upt_lines=UPT_ENTRIES, |
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475 | const size_t ivt_lines=IVT_ENTRIES, |
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476 | const size_t debug_start_cycle=0, |
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477 | const bool debug_ok=false ); |
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478 | |
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479 | ~VciMemCache(); |
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480 | |
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481 | void print_stats(); |
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482 | void print_trace(); |
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483 | void cache_monitor(addr_t addr); |
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484 | void start_monitor(addr_t addr, addr_t length); |
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485 | void stop_monitor(); |
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486 | |
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487 | private: |
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488 | |
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489 | void transition(); |
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490 | void genMoore(); |
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491 | void check_monitor(addr_t addr, data_t data, bool read); |
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492 | |
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493 | // Component attributes |
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494 | std::list<soclib::common::Segment> m_seglist; // segments allocated |
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495 | size_t m_nseg; // number of segments |
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496 | soclib::common::Segment **m_seg; // array of segments pointers |
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497 | size_t m_seg_config; // config segment index |
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498 | const size_t m_srcid_x; // global index on RAM network |
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499 | const size_t m_initiators; // Number of initiators |
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500 | const size_t m_heap_size; // Size of the heap |
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501 | const size_t m_ways; // Number of ways in a set |
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502 | const size_t m_sets; // Number of cache sets |
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503 | const size_t m_words; // Number of words in a line |
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504 | const size_t m_cc_global_id; // global_index on cc network |
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505 | size_t m_debug_start_cycle; |
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506 | bool m_debug_ok; |
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507 | uint32_t m_trt_lines; |
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508 | TransactionTab m_trt; // xram transaction table |
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509 | uint32_t m_upt_lines; |
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510 | UpdateTab m_upt; // pending update |
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511 | UpdateTab m_ivt; // pending invalidate |
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512 | CacheDirectory m_cache_directory; // data cache directory |
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513 | CacheData m_cache_data; // data array[set][way][word] |
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514 | HeapDirectory m_heap; // heap for copies |
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515 | size_t m_max_copies; // max number of copies in heap |
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516 | GenericLLSCGlobalTable |
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517 | < 32 , // number of slots |
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518 | 4096, // number of processors in the system |
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519 | 8000, // registration life (# of LL operations) |
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520 | addr_t > m_llsc_table; // ll/sc registration table |
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521 | |
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522 | // adress masks |
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523 | const soclib::common::AddressMaskingTable<addr_t> m_x; |
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524 | const soclib::common::AddressMaskingTable<addr_t> m_y; |
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525 | const soclib::common::AddressMaskingTable<addr_t> m_z; |
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526 | const soclib::common::AddressMaskingTable<addr_t> m_nline; |
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527 | |
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528 | // broadcast address |
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529 | uint32_t m_broadcast_boundaries; |
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530 | |
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531 | // Fifo between TGT_CMD fsm and READ fsm |
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532 | GenericFifo<addr_t> m_cmd_read_addr_fifo; |
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533 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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534 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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535 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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536 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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537 | |
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538 | // Fifo between TGT_CMD fsm and WRITE fsm |
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539 | GenericFifo<addr_t> m_cmd_write_addr_fifo; |
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540 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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541 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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542 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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543 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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544 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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545 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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546 | |
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547 | // Fifo between TGT_CMD fsm and CAS fsm |
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548 | GenericFifo<addr_t> m_cmd_cas_addr_fifo; |
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549 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
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550 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
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551 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
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552 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
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553 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
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554 | |
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555 | // Fifo between CC_RECEIVE fsm and CLEANUP fsm |
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556 | GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; |
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557 | |
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558 | // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm |
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559 | GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; |
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560 | |
---|
561 | // Buffer between TGT_CMD fsm and TGT_RSP fsm |
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562 | // (segmentation violation response request) |
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563 | sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req; |
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564 | |
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565 | sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata; |
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566 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error; |
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567 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid; |
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568 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid; |
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569 | sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid; |
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570 | |
---|
571 | sc_signal<addr_t> r_tgt_cmd_config_addr; |
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572 | sc_signal<size_t> r_tgt_cmd_config_cmd; |
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573 | |
---|
574 | ////////////////////////////////////////////////// |
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575 | // Registers controlled by the TGT_CMD fsm |
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576 | ////////////////////////////////////////////////// |
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577 | |
---|
578 | sc_signal<int> r_tgt_cmd_fsm; |
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579 | sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config |
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580 | sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config |
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581 | sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config |
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582 | |
---|
583 | /////////////////////////////////////////////////////// |
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584 | // Registers controlled by the CONFIG fsm |
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585 | /////////////////////////////////////////////////////// |
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586 | |
---|
587 | sc_signal<int> r_config_fsm; // FSM state |
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588 | sc_signal<bool> r_config_lock; // lock protecting exclusive access |
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589 | sc_signal<int> r_config_cmd; // config request type |
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590 | sc_signal<addr_t> r_config_address; // target buffer physical address |
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591 | sc_signal<size_t> r_config_srcid; // config request srcid |
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592 | sc_signal<size_t> r_config_trdid; // config request trdid |
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593 | sc_signal<size_t> r_config_pktid; // config request pktid |
---|
594 | sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled |
---|
595 | sc_signal<size_t> r_config_rsp_lines; // number of lines not completed |
---|
596 | sc_signal<size_t> r_config_dir_way; // DIR: selected way |
---|
597 | sc_signal<bool> r_config_dir_lock; // DIR: locked entry |
---|
598 | sc_signal<size_t> r_config_dir_count; // DIR: number of copies |
---|
599 | sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast) |
---|
600 | sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID |
---|
601 | sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type |
---|
602 | sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP |
---|
603 | sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP |
---|
604 | sc_signal<size_t> r_config_trt_index; // selected entry in TRT |
---|
605 | sc_signal<size_t> r_config_ivt_index; // selected entry in IVT |
---|
606 | |
---|
607 | // Buffer between CONFIG fsm and IXR_CMD fsm |
---|
608 | sc_signal<bool> r_config_to_ixr_cmd_req; // valid request |
---|
609 | sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index |
---|
610 | |
---|
611 | // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) |
---|
612 | sc_signal<bool> r_config_to_tgt_rsp_req; // valid request |
---|
613 | sc_signal<bool> r_config_to_tgt_rsp_error; // error response |
---|
614 | sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid |
---|
615 | sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid |
---|
616 | sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid |
---|
617 | |
---|
618 | // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) |
---|
619 | sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request |
---|
620 | sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request |
---|
621 | sc_signal<addr_t> r_config_to_cc_send_nline; // line index |
---|
622 | sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index |
---|
623 | GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
624 | GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid |
---|
625 | |
---|
626 | /////////////////////////////////////////////////////// |
---|
627 | // Registers controlled by the READ fsm |
---|
628 | /////////////////////////////////////////////////////// |
---|
629 | |
---|
630 | sc_signal<int> r_read_fsm; // FSM state |
---|
631 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
---|
632 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
---|
633 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
---|
634 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
---|
635 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
---|
636 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
---|
637 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
---|
638 | sc_signal<size_t> r_read_count; // number of copies |
---|
639 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
---|
640 | sc_signal<data_t> * r_read_data; // data (one cache line) |
---|
641 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
642 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
643 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
644 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
645 | sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table |
---|
646 | |
---|
647 | // Buffer between READ fsm and IXR_CMD fsm |
---|
648 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
649 | sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index |
---|
650 | |
---|
651 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
652 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
653 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
654 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
655 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
656 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
---|
657 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
658 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
659 | sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
660 | |
---|
661 | /////////////////////////////////////////////////////////////// |
---|
662 | // Registers controlled by the WRITE fsm |
---|
663 | /////////////////////////////////////////////////////////////// |
---|
664 | |
---|
665 | sc_signal<int> r_write_fsm; // FSM state |
---|
666 | sc_signal<addr_t> r_write_address; // first word address |
---|
667 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
668 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
669 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
670 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
671 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
672 | sc_signal<data_t> * r_write_data; // data (one cache line) |
---|
673 | sc_signal<be_t> * r_write_be; // one byte enable per word |
---|
674 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
---|
675 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
676 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
677 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
678 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
679 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
---|
680 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
681 | sc_signal<size_t> r_write_count; // number of copies |
---|
682 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
683 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
684 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
685 | sc_signal<size_t> r_write_way; // way of the line |
---|
686 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
687 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
688 | sc_signal<bool> r_write_sc_fail; // sc command failed |
---|
689 | sc_signal<bool> r_write_pending_sc; // sc command pending |
---|
690 | |
---|
691 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
692 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
693 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
694 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
695 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
696 | sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed |
---|
697 | |
---|
698 | // Buffer between WRITE fsm and IXR_CMD fsm |
---|
699 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
700 | sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT) |
---|
701 | sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index |
---|
702 | |
---|
703 | // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
704 | sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request |
---|
705 | sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request |
---|
706 | sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index |
---|
707 | sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table |
---|
708 | sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line) |
---|
709 | sc_signal<be_t> * r_write_to_cc_send_be; // word enable |
---|
710 | sc_signal<size_t> r_write_to_cc_send_count; // number of words in line |
---|
711 | sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line |
---|
712 | GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
713 | GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids |
---|
714 | |
---|
715 | // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) |
---|
716 | sc_signal<bool> r_write_to_multi_ack_req; // valid request |
---|
717 | sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table |
---|
718 | |
---|
719 | ///////////////////////////////////////////////////////// |
---|
720 | // Registers controlled by MULTI_ACK fsm |
---|
721 | ////////////////////////////////////////////////////////// |
---|
722 | |
---|
723 | sc_signal<int> r_multi_ack_fsm; // FSM state |
---|
724 | sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table |
---|
725 | sc_signal<size_t> r_multi_ack_srcid; // pending write srcid |
---|
726 | sc_signal<size_t> r_multi_ack_trdid; // pending write trdid |
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727 | sc_signal<size_t> r_multi_ack_pktid; // pending write pktid |
---|
728 | sc_signal<addr_t> r_multi_ack_nline; // pending write nline |
---|
729 | |
---|
730 | // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) |
---|
731 | sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request |
---|
732 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid |
---|
733 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid |
---|
734 | sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid |
---|
735 | |
---|
736 | /////////////////////////////////////////////////////// |
---|
737 | // Registers controlled by CLEANUP fsm |
---|
738 | /////////////////////////////////////////////////////// |
---|
739 | |
---|
740 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
741 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
742 | sc_signal<bool> r_cleanup_inst; // Instruction or Data ? |
---|
743 | sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index |
---|
744 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
745 | |
---|
746 | |
---|
747 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
748 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
---|
749 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
750 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
751 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
752 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
753 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
754 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
---|
755 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
756 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
757 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
758 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
759 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
760 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
761 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
762 | |
---|
763 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp |
---|
764 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
765 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
766 | |
---|
767 | sc_signal<bool> r_cleanup_need_rsp; // write response required |
---|
768 | sc_signal<bool> r_cleanup_need_ack; // config acknowledge required |
---|
769 | |
---|
770 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
771 | |
---|
772 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
773 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
774 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
775 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
776 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
777 | |
---|
778 | /////////////////////////////////////////////////////// |
---|
779 | // Registers controlled by CAS fsm |
---|
780 | /////////////////////////////////////////////////////// |
---|
781 | |
---|
782 | sc_signal<int> r_cas_fsm; // FSM state |
---|
783 | sc_signal<data_t> r_cas_wdata; // write data word |
---|
784 | sc_signal<data_t> * r_cas_rdata; // read data word |
---|
785 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
---|
786 | sc_signal<size_t> r_cas_cpt; // size of command |
---|
787 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
---|
788 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
---|
789 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
---|
790 | sc_signal<size_t> r_cas_count; // number of copies |
---|
791 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
---|
792 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
---|
793 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
---|
794 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
---|
795 | sc_signal<size_t> r_cas_way; // way in directory |
---|
796 | sc_signal<size_t> r_cas_set; // set in directory |
---|
797 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
---|
798 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
---|
799 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
800 | sc_signal<data_t> * r_cas_data; // cache line data |
---|
801 | |
---|
802 | // Buffer between CAS fsm and IXR_CMD fsm |
---|
803 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
---|
804 | sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT) |
---|
805 | sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index |
---|
806 | |
---|
807 | // Buffer between CAS fsm and TGT_RSP fsm |
---|
808 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
---|
809 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
---|
810 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
---|
811 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
---|
812 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
813 | |
---|
814 | // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) |
---|
815 | sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request |
---|
816 | sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request |
---|
817 | sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index |
---|
818 | sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table |
---|
819 | sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word) |
---|
820 | sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS |
---|
821 | sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word) |
---|
822 | sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line |
---|
823 | GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
824 | GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids |
---|
825 | |
---|
826 | //////////////////////////////////////////////////// |
---|
827 | // Registers controlled by the IXR_RSP fsm |
---|
828 | //////////////////////////////////////////////////// |
---|
829 | |
---|
830 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
831 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
832 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
833 | |
---|
834 | // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) |
---|
835 | sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit |
---|
836 | |
---|
837 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
838 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry |
---|
839 | |
---|
840 | //////////////////////////////////////////////////// |
---|
841 | // Registers controlled by the XRAM_RSP fsm |
---|
842 | //////////////////////////////////////////////////// |
---|
843 | |
---|
844 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
845 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
846 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
847 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
848 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
849 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
850 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
851 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
852 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
853 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
854 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
855 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
856 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
857 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
858 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
859 | sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index |
---|
860 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
861 | |
---|
862 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
863 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
864 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
865 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
866 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
867 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
868 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
869 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
870 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
---|
871 | sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table |
---|
872 | |
---|
873 | // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) |
---|
874 | sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request |
---|
875 | sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request |
---|
876 | sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index; |
---|
877 | sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry |
---|
878 | GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type |
---|
879 | GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids |
---|
880 | |
---|
881 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm |
---|
882 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
883 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index |
---|
884 | |
---|
885 | //////////////////////////////////////////////////// |
---|
886 | // Registers controlled by the IXR_CMD fsm |
---|
887 | //////////////////////////////////////////////////// |
---|
888 | |
---|
889 | sc_signal<int> r_ixr_cmd_fsm; |
---|
890 | sc_signal<size_t> r_ixr_cmd_word; // word index for a put |
---|
891 | sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value |
---|
892 | sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM |
---|
893 | sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer |
---|
894 | sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET) |
---|
895 | |
---|
896 | //////////////////////////////////////////////////// |
---|
897 | // Registers controlled by TGT_RSP fsm |
---|
898 | //////////////////////////////////////////////////// |
---|
899 | |
---|
900 | sc_signal<int> r_tgt_rsp_fsm; |
---|
901 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
902 | sc_signal<bool> r_tgt_rsp_key_sent; |
---|
903 | |
---|
904 | //////////////////////////////////////////////////// |
---|
905 | // Registers controlled by CC_SEND fsm |
---|
906 | //////////////////////////////////////////////////// |
---|
907 | |
---|
908 | sc_signal<int> r_cc_send_fsm; |
---|
909 | sc_signal<size_t> r_cc_send_cpt; |
---|
910 | sc_signal<bool> r_cc_send_inst; |
---|
911 | |
---|
912 | //////////////////////////////////////////////////// |
---|
913 | // Registers controlled by CC_RECEIVE fsm |
---|
914 | //////////////////////////////////////////////////// |
---|
915 | |
---|
916 | sc_signal<int> r_cc_receive_fsm; |
---|
917 | |
---|
918 | //////////////////////////////////////////////////// |
---|
919 | // Registers controlled by ALLOC_DIR fsm |
---|
920 | //////////////////////////////////////////////////// |
---|
921 | |
---|
922 | sc_signal<int> r_alloc_dir_fsm; |
---|
923 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
924 | |
---|
925 | //////////////////////////////////////////////////// |
---|
926 | // Registers controlled by ALLOC_TRT fsm |
---|
927 | //////////////////////////////////////////////////// |
---|
928 | |
---|
929 | sc_signal<int> r_alloc_trt_fsm; |
---|
930 | |
---|
931 | //////////////////////////////////////////////////// |
---|
932 | // Registers controlled by ALLOC_UPT fsm |
---|
933 | //////////////////////////////////////////////////// |
---|
934 | |
---|
935 | sc_signal<int> r_alloc_upt_fsm; |
---|
936 | |
---|
937 | //////////////////////////////////////////////////// |
---|
938 | // Registers controlled by ALLOC_IVT fsm |
---|
939 | //////////////////////////////////////////////////// |
---|
940 | |
---|
941 | sc_signal<int> r_alloc_ivt_fsm; |
---|
942 | |
---|
943 | //////////////////////////////////////////////////// |
---|
944 | // Registers controlled by ALLOC_HEAP fsm |
---|
945 | //////////////////////////////////////////////////// |
---|
946 | |
---|
947 | sc_signal<int> r_alloc_heap_fsm; |
---|
948 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
---|
949 | }; // end class VciMemCache |
---|
950 | |
---|
951 | }} |
---|
952 | |
---|
953 | #endif |
---|
954 | |
---|
955 | // Local Variables: |
---|
956 | // tab-width: 2 |
---|
957 | // c-basic-offset: 2 |
---|
958 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
959 | // indent-tabs-mode: nil |
---|
960 | // End: |
---|
961 | |
---|
962 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
---|
963 | |
---|