[41] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache_v2s.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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| 28 | */ |
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| 29 | /* |
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| 30 | * |
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| 31 | * Modifications done by Christophe Choichillon on the 7/04/2009: |
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| 32 | * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE |
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| 33 | * - Adding a new VCI target port for the CLEANUP network |
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| 34 | * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP |
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| 35 | * |
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| 36 | * Modifications to do : |
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| 37 | * - Adding new variables used by the CLEANUP FSM |
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| 38 | * |
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| 39 | */ |
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| 40 | |
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| 41 | #ifndef SOCLIB_CABA_MEM_CACHE_V2S_H |
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| 42 | #define SOCLIB_CABA_MEM_CACHE_V2S_H |
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| 43 | |
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| 44 | #include <inttypes.h> |
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| 45 | #include <systemc> |
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| 46 | #include <list> |
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| 47 | #include <cassert> |
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| 48 | #include "arithmetics.h" |
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| 49 | #include "alloc_elems.h" |
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| 50 | #include "caba_base_module.h" |
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| 51 | #include "vci_target.h" |
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| 52 | #include "vci_initiator.h" |
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| 53 | #include "generic_fifo.h" |
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| 54 | #include "mapping_table.h" |
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| 55 | #include "int_tab.h" |
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| 56 | #include "mem_cache_directory_v2.h" |
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| 57 | #include "xram_transaction_v2.h" |
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| 58 | #include "update_tab_v2.h" |
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| 59 | #include "atomic_tab_v2.h" |
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| 60 | |
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| 61 | #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab |
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| 62 | #define UPDATE_TAB_LINES 4 // Number of lines in the update tab |
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| 63 | #define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate |
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| 64 | |
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| 65 | namespace soclib { namespace caba { |
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| 66 | using namespace sc_core; |
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| 67 | |
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| 68 | template<typename vci_param> |
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| 69 | class VciMemCacheV2S |
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| 70 | : public soclib::caba::BaseModule |
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| 71 | { |
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| 72 | typedef sc_dt::sc_uint<40> addr_t; |
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| 73 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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| 74 | typedef uint32_t data_t; |
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| 75 | typedef uint32_t tag_t; |
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| 76 | typedef uint32_t size_t; |
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| 77 | typedef uint32_t be_t; |
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| 78 | typedef uint32_t copy_t; |
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| 79 | |
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| 80 | /* States of the TGT_CMD fsm */ |
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| 81 | enum tgt_cmd_fsm_state_e{ |
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| 82 | TGT_CMD_IDLE, |
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| 83 | TGT_CMD_READ, |
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| 84 | TGT_CMD_READ_EOP, |
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| 85 | TGT_CMD_WRITE, |
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| 86 | TGT_CMD_ATOMIC, |
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| 87 | }; |
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| 88 | |
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| 89 | /* States of the TGT_RSP fsm */ |
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| 90 | enum tgt_rsp_fsm_state_e{ |
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| 91 | TGT_RSP_READ_IDLE, |
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| 92 | TGT_RSP_WRITE_IDLE, |
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| 93 | TGT_RSP_LLSC_IDLE, |
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| 94 | TGT_RSP_XRAM_IDLE, |
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| 95 | TGT_RSP_INIT_IDLE, |
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| 96 | TGT_RSP_CLEANUP_IDLE, |
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| 97 | TGT_RSP_READ, |
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| 98 | TGT_RSP_WRITE, |
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| 99 | TGT_RSP_LLSC, |
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| 100 | TGT_RSP_XRAM, |
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| 101 | TGT_RSP_INIT, |
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| 102 | TGT_RSP_CLEANUP, |
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| 103 | }; |
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| 104 | |
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| 105 | /* States of the INIT_CMD fsm */ |
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| 106 | enum init_cmd_fsm_state_e{ |
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| 107 | INIT_CMD_INVAL_IDLE, |
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| 108 | INIT_CMD_INVAL_SEL, |
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| 109 | INIT_CMD_INVAL_NLINE, |
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| 110 | INIT_CMD_UPDT_IDLE, |
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| 111 | INIT_CMD_UPDT_SEL, |
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| 112 | INIT_CMD_BRDCAST, |
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| 113 | INIT_CMD_UPDT_NLINE, |
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| 114 | INIT_CMD_UPDT_INDEX, |
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| 115 | INIT_CMD_UPDT_DATA, |
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| 116 | INIT_CMD_SC_UPDT_IDLE, |
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| 117 | INIT_CMD_SC_UPDT_SEL, |
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| 118 | INIT_CMD_SC_BRDCAST, |
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| 119 | INIT_CMD_SC_UPDT_NLINE, |
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| 120 | INIT_CMD_SC_UPDT_INDEX, |
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| 121 | INIT_CMD_SC_UPDT_DATA, |
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| 122 | }; |
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| 123 | |
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| 124 | /* States of the INIT_RSP fsm */ |
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| 125 | enum init_rsp_fsm_state_e{ |
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| 126 | INIT_RSP_IDLE, |
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| 127 | INIT_RSP_UPT_LOCK, |
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| 128 | INIT_RSP_UPT_CLEAR, |
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| 129 | INIT_RSP_END, |
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| 130 | }; |
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| 131 | |
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| 132 | /* States of the READ fsm */ |
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| 133 | enum read_fsm_state_e{ |
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| 134 | READ_IDLE, |
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| 135 | READ_DIR_LOCK, |
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| 136 | READ_DIR_HIT, |
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| 137 | READ_RSP, |
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| 138 | READ_TRT_LOCK, |
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| 139 | READ_TRT_SET, |
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| 140 | READ_XRAM_REQ, |
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| 141 | }; |
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| 142 | |
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| 143 | /* States of the WRITE fsm */ |
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| 144 | enum write_fsm_state_e{ |
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| 145 | WRITE_IDLE, |
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| 146 | WRITE_NEXT, |
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| 147 | WRITE_DIR_LOCK, |
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| 148 | WRITE_DIR_HIT_READ, |
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| 149 | WRITE_DIR_HIT, |
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| 150 | WRITE_DIR_HIT_RSP, |
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| 151 | WRITE_UPT_LOCK, |
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| 152 | WRITE_WAIT_UPT, |
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| 153 | WRITE_UPDATE, |
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| 154 | WRITE_RSP, |
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| 155 | WRITE_TRT_LOCK, |
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| 156 | WRITE_TRT_DATA, |
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| 157 | WRITE_TRT_SET, |
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| 158 | WRITE_WAIT_TRT, |
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| 159 | WRITE_XRAM_REQ, |
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| 160 | WRITE_TRT_WRITE_LOCK, |
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| 161 | WRITE_INVAL_LOCK, |
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| 162 | WRITE_DIR_INVAL, |
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| 163 | WRITE_INVAL, |
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| 164 | WRITE_XRAM_SEND, |
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| 165 | }; |
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| 166 | |
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| 167 | /* States of the IXR_RSP fsm */ |
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| 168 | enum ixr_rsp_fsm_state_e{ |
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| 169 | IXR_RSP_IDLE, |
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| 170 | IXR_RSP_ACK, |
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| 171 | IXR_RSP_TRT_ERASE, |
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| 172 | IXR_RSP_TRT_READ, |
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| 173 | }; |
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| 174 | |
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| 175 | /* States of the XRAM_RSP fsm */ |
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| 176 | enum xram_rsp_fsm_state_e{ |
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| 177 | XRAM_RSP_IDLE, |
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| 178 | XRAM_RSP_TRT_COPY, |
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| 179 | XRAM_RSP_TRT_DIRTY, |
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| 180 | XRAM_RSP_DIR_LOCK, |
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| 181 | XRAM_RSP_DIR_UPDT, |
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| 182 | XRAM_RSP_DIR_RSP, |
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| 183 | XRAM_RSP_INVAL_LOCK, |
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| 184 | XRAM_RSP_INVAL_WAIT, |
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| 185 | XRAM_RSP_INVAL, |
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| 186 | XRAM_RSP_WRITE_DIRTY, |
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| 187 | }; |
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| 188 | |
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| 189 | /* States of the IXR_CMD fsm */ |
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| 190 | enum ixr_cmd_fsm_state_e{ |
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| 191 | IXR_CMD_READ_IDLE, |
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| 192 | IXR_CMD_WRITE_IDLE, |
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| 193 | IXR_CMD_LLSC_IDLE, |
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| 194 | IXR_CMD_XRAM_IDLE, |
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| 195 | IXR_CMD_READ_NLINE, |
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| 196 | IXR_CMD_WRITE_NLINE, |
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| 197 | IXR_CMD_LLSC_NLINE, |
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| 198 | IXR_CMD_XRAM_DATA, |
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| 199 | }; |
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| 200 | |
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| 201 | /* States of the LLSC fsm */ |
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| 202 | enum llsc_fsm_state_e{ |
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| 203 | LLSC_IDLE, |
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| 204 | LL_DIR_LOCK, |
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| 205 | LL_DIR_HIT, |
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| 206 | LL_RSP, |
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| 207 | SC_DIR_LOCK, |
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| 208 | SC_DIR_HIT, |
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| 209 | SC_UPT_LOCK, |
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| 210 | SC_WAIT_UPT, |
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| 211 | SC_UPDATE, |
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| 212 | SC_TRT_LOCK, |
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| 213 | SC_INVAL_LOCK, |
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| 214 | SC_DIR_INVAL, |
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| 215 | SC_INVAL, |
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| 216 | SC_XRAM_SEND, |
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| 217 | SC_RSP_FALSE, |
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| 218 | SC_RSP_TRUE, |
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| 219 | LLSC_TRT_LOCK, |
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| 220 | LLSC_TRT_SET, |
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| 221 | LLSC_XRAM_REQ, |
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| 222 | }; |
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| 223 | |
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| 224 | /* States of the CLEANUP fsm */ |
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| 225 | enum cleanup_fsm_state_e{ |
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| 226 | CLEANUP_IDLE, |
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| 227 | CLEANUP_DIR_LOCK, |
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| 228 | CLEANUP_DIR_WRITE, |
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| 229 | CLEANUP_UPT_LOCK, |
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| 230 | CLEANUP_UPT_WRITE, |
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| 231 | CLEANUP_WRITE_RSP, |
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| 232 | CLEANUP_RSP, |
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| 233 | }; |
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| 234 | |
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| 235 | /* States of the ALLOC_DIR fsm */ |
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| 236 | enum alloc_dir_fsm_state_e{ |
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| 237 | ALLOC_DIR_READ, |
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| 238 | ALLOC_DIR_WRITE, |
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| 239 | ALLOC_DIR_LLSC, |
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| 240 | ALLOC_DIR_CLEANUP, |
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| 241 | ALLOC_DIR_XRAM_RSP, |
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| 242 | }; |
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| 243 | |
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| 244 | /* States of the ALLOC_TRT fsm */ |
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| 245 | enum alloc_trt_fsm_state_e{ |
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| 246 | ALLOC_TRT_READ, |
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| 247 | ALLOC_TRT_WRITE, |
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| 248 | ALLOC_TRT_LLSC, |
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| 249 | ALLOC_TRT_XRAM_RSP, |
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| 250 | ALLOC_TRT_IXR_RSP, |
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| 251 | }; |
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| 252 | |
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| 253 | /* States of the ALLOC_UPT fsm */ |
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| 254 | enum alloc_upt_fsm_state_e{ |
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| 255 | ALLOC_UPT_WRITE, |
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| 256 | ALLOC_UPT_XRAM_RSP, |
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| 257 | ALLOC_UPT_INIT_RSP, |
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| 258 | ALLOC_UPT_CLEANUP, |
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| 259 | ALLOC_UPT_LLSC, |
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| 260 | }; |
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| 261 | |
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| 262 | uint32_t m_cpt_cycles; // Counter of cycles |
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| 263 | uint32_t m_cpt_read; // Number of READ transactions |
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| 264 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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| 265 | uint32_t m_cpt_write; // Number of WRITE transactions |
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| 266 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 267 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 268 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 269 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 270 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 271 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 272 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 273 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 274 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 275 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 276 | uint32_t m_cpt_sc; // Number of SC transactions |
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| 277 | |
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| 278 | protected: |
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| 279 | |
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| 280 | SC_HAS_PROCESS(VciMemCacheV2S); |
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| 281 | |
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| 282 | public: |
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| 283 | sc_in<bool> p_clk; |
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| 284 | sc_in<bool> p_resetn; |
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| 285 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 286 | soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup; |
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| 287 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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| 288 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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| 289 | |
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| 290 | VciMemCacheV2S( |
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| 291 | sc_module_name name, // Instance Name |
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| 292 | const soclib::common::MappingTable &mtp, // Mapping table for primary requets |
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| 293 | const soclib::common::MappingTable &mtc, // Mapping table for coherence requets |
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| 294 | const soclib::common::MappingTable &mtx, // Mapping table for XRAM |
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| 295 | const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) |
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| 296 | const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) |
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| 297 | const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) |
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| 298 | const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup |
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| 299 | size_t nways, // Number of ways per set |
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| 300 | size_t nsets, // Number of sets |
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| 301 | size_t nwords); // Number of words per line |
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| 302 | |
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| 303 | ~VciMemCacheV2S(); |
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| 304 | |
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| 305 | void transition(); |
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| 306 | |
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| 307 | void genMoore(); |
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| 308 | |
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| 309 | void print_stats(); |
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| 310 | |
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| 311 | private: |
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| 312 | |
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| 313 | // Component attributes |
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| 314 | const size_t m_initiators; // Number of initiators |
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| 315 | const size_t m_ways; // Number of ways in a set |
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| 316 | const size_t m_sets; // Number of cache sets |
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| 317 | const size_t m_words; // Number of words in a line |
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| 318 | const size_t m_srcid_ixr; // Srcid for requests to XRAM |
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| 319 | const size_t m_srcid_ini; // Srcid for requests to processors |
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| 320 | std::list<soclib::common::Segment> m_seglist; // memory cached into the cache |
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| 321 | std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache |
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| 322 | vci_addr_t *m_coherence_table; // address(srcid) |
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| 323 | AtomicTab m_atomic_tab; // atomic access table |
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| 324 | TransactionTab m_transaction_tab; // xram transaction table |
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| 325 | UpdateTab m_update_tab; // pending update & invalidate |
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| 326 | CacheDirectory m_cache_directory; // data cache directory |
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| 327 | |
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| 328 | data_t ***m_cache_data; // data array[set][way][word] |
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| 329 | |
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| 330 | // adress masks |
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| 331 | const soclib::common::AddressMaskingTable<vci_addr_t> m_x; |
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| 332 | const soclib::common::AddressMaskingTable<vci_addr_t> m_y; |
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| 333 | const soclib::common::AddressMaskingTable<vci_addr_t> m_z; |
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| 334 | const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; |
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| 335 | |
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| 336 | ////////////////////////////////////////////////// |
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| 337 | // Others registers |
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| 338 | ////////////////////////////////////////////////// |
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| 339 | sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line |
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| 340 | |
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| 341 | ////////////////////////////////////////////////// |
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| 342 | // Registers controlled by the TGT_CMD fsm |
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| 343 | ////////////////////////////////////////////////// |
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| 344 | |
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| 345 | // Fifo between TGT_CMD fsm and READ fsm |
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| 346 | GenericFifo<uint64_t> m_cmd_read_addr_fifo; |
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| 347 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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| 348 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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| 349 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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| 350 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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| 351 | |
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| 352 | // Fifo between TGT_CMD fsm and WRITE fsm |
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| 353 | GenericFifo<uint64_t> m_cmd_write_addr_fifo; |
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| 354 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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| 355 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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| 356 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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| 357 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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| 358 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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| 359 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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| 360 | |
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| 361 | // Fifo between TGT_CMD fsm and LLSC fsm |
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| 362 | GenericFifo<uint64_t> m_cmd_llsc_addr_fifo; |
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| 363 | GenericFifo<bool> m_cmd_llsc_sc_fifo; |
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| 364 | GenericFifo<size_t> m_cmd_llsc_srcid_fifo; |
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| 365 | GenericFifo<size_t> m_cmd_llsc_trdid_fifo; |
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| 366 | GenericFifo<size_t> m_cmd_llsc_pktid_fifo; |
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| 367 | GenericFifo<data_t> m_cmd_llsc_wdata_fifo; |
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| 368 | |
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| 369 | sc_signal<int> r_tgt_cmd_fsm; |
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| 370 | |
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| 371 | sc_signal<size_t> r_index; |
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| 372 | size_t nseg; |
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| 373 | size_t ncseg; |
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| 374 | soclib::common::Segment **m_seg; |
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| 375 | soclib::common::Segment **m_cseg; |
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| 376 | /////////////////////////////////////////////////////// |
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| 377 | // Registers controlled by the READ fsm |
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| 378 | /////////////////////////////////////////////////////// |
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| 379 | |
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| 380 | sc_signal<int> r_read_fsm; // FSM state |
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| 381 | sc_signal<copy_t> r_read_d_copies; // bit-vector of copies |
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| 382 | sc_signal<copy_t> r_read_i_copies; // bit-vector of copies |
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| 383 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
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| 384 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
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| 385 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
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| 386 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
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| 387 | sc_signal<size_t> r_read_count; // number of copies |
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| 388 | sc_signal<data_t> *r_read_data; // data (one cache line) |
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| 389 | sc_signal<size_t> r_read_way; // associative way (in cache) |
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| 390 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
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| 391 | |
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| 392 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
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| 393 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
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| 394 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
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| 395 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
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| 396 | |
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| 397 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
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| 398 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
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| 399 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
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| 400 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
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| 401 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
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| 402 | sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line) |
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| 403 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
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| 404 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
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| 405 | |
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| 406 | /////////////////////////////////////////////////////////////// |
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| 407 | // Registers controlled by the WRITE fsm |
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| 408 | /////////////////////////////////////////////////////////////// |
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| 409 | |
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| 410 | sc_signal<int> r_write_fsm; // FSM state |
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| 411 | sc_signal<addr_t> r_write_address; // first word address |
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| 412 | sc_signal<size_t> r_write_word_index; // first word index in line |
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| 413 | sc_signal<size_t> r_write_word_count; // number of words in line |
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| 414 | sc_signal<size_t> r_write_srcid; // transaction srcid |
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| 415 | sc_signal<size_t> r_write_trdid; // transaction trdid |
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| 416 | sc_signal<size_t> r_write_pktid; // transaction pktid |
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| 417 | sc_signal<data_t> *r_write_data; // data (one cache line) |
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| 418 | sc_signal<be_t> *r_write_be; // one byte enable per word |
---|
| 419 | sc_signal<bool> r_write_byte; // is it a byte write |
---|
| 420 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 421 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 422 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 423 | sc_signal<copy_t> r_write_d_copies; // bit vector of copies |
---|
| 424 | sc_signal<copy_t> r_write_i_copies; // bit vector of copies |
---|
| 425 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 426 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 427 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 428 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 429 | |
---|
| 430 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 431 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 432 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 433 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 434 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 435 | |
---|
| 436 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 437 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 438 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
| 439 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
| 440 | sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data |
---|
| 441 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 442 | |
---|
| 443 | // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
| 444 | sc_signal<bool> r_write_to_init_cmd_req; // valid request |
---|
| 445 | sc_signal<bool> r_write_to_init_cmd_brdcast; // brdcast request |
---|
| 446 | sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index |
---|
| 447 | sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table |
---|
| 448 | sc_signal<copy_t> r_write_to_init_cmd_d_copies; // bit_vector of L1 to update |
---|
| 449 | sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line) |
---|
| 450 | sc_signal<bool> *r_write_to_init_cmd_we; // word enable |
---|
| 451 | sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line |
---|
| 452 | sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line |
---|
| 453 | |
---|
| 454 | ///////////////////////////////////////////////////////// |
---|
| 455 | // Registers controlled by INIT_RSP fsm |
---|
| 456 | ////////////////////////////////////////////////////////// |
---|
| 457 | |
---|
| 458 | sc_signal<int> r_init_rsp_fsm; // FSM state |
---|
| 459 | sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table |
---|
| 460 | sc_signal<size_t> r_init_rsp_srcid; // pending write srcid |
---|
| 461 | sc_signal<size_t> r_init_rsp_trdid; // pending write trdid |
---|
| 462 | sc_signal<size_t> r_init_rsp_pktid; // pending write pktid |
---|
| 463 | sc_signal<addr_t> r_init_rsp_nline; // pending write nline |
---|
| 464 | |
---|
| 465 | // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) |
---|
| 466 | sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request |
---|
| 467 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 468 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 469 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 470 | |
---|
| 471 | /////////////////////////////////////////////////////// |
---|
| 472 | // Registers controlled by CLEANUP fsm |
---|
| 473 | /////////////////////////////////////////////////////// |
---|
| 474 | |
---|
| 475 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 476 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 477 | sc_signal<size_t> r_cleanup_trdid; // transaction trdid |
---|
| 478 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
| 479 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 480 | |
---|
| 481 | sc_signal<copy_t> r_cleanup_d_copies; // bit-vector of copies |
---|
| 482 | sc_signal<copy_t> r_cleanup_i_copies; // bit-vector of copies |
---|
| 483 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 484 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 485 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 486 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 487 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 488 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 489 | |
---|
| 490 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
---|
| 491 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 492 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 493 | sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp |
---|
| 494 | |
---|
| 495 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 496 | |
---|
| 497 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 498 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 499 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 500 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 501 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
| 502 | |
---|
| 503 | /////////////////////////////////////////////////////// |
---|
| 504 | // Registers controlled by LLSC fsm |
---|
| 505 | /////////////////////////////////////////////////////// |
---|
| 506 | |
---|
| 507 | sc_signal<int> r_llsc_fsm; // FSM state |
---|
| 508 | sc_signal<data_t> r_llsc_data; // read data word |
---|
| 509 | sc_signal<uint32_t> r_llsc_lfsr; // lfsr for random introducing |
---|
| 510 | sc_signal<copy_t> r_llsc_i_copies; // bit_vector of copies |
---|
| 511 | sc_signal<copy_t> r_llsc_d_copies; // bit_vector of copies |
---|
| 512 | sc_signal<copy_t> r_llsc_count; // number of copies |
---|
| 513 | sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory) |
---|
| 514 | sc_signal<bool> r_llsc_dirty; // dirty bit (in directory) |
---|
| 515 | sc_signal<size_t> r_llsc_way; // way in directory |
---|
| 516 | sc_signal<size_t> r_llsc_set; // set in directory |
---|
| 517 | sc_signal<data_t> r_llsc_tag; // cache line tag (in directory) |
---|
| 518 | sc_signal<size_t> r_llsc_trt_index; // Transaction Table index |
---|
| 519 | sc_signal<size_t> r_llsc_upt_index; // Update Table index |
---|
| 520 | |
---|
| 521 | // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read) |
---|
| 522 | sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request |
---|
| 523 | sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index |
---|
| 524 | sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 525 | sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request |
---|
| 526 | sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data |
---|
| 527 | |
---|
| 528 | |
---|
| 529 | // Buffer between LLSC fsm and TGT_RSP fsm |
---|
| 530 | sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request |
---|
| 531 | sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word |
---|
| 532 | sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 533 | sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 534 | sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 535 | |
---|
| 536 | // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
| 537 | sc_signal<bool> r_llsc_to_init_cmd_req; // valid request |
---|
| 538 | sc_signal<bool> r_llsc_to_init_cmd_brdcast; // brdcast request |
---|
| 539 | sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index |
---|
| 540 | sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table |
---|
| 541 | sc_signal<copy_t> r_llsc_to_init_cmd_d_copies; // bit_vector of L1 to update |
---|
| 542 | sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word) |
---|
| 543 | sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line |
---|
| 544 | |
---|
| 545 | //////////////////////////////////////////////////// |
---|
| 546 | // Registers controlled by the IXR_RSP fsm |
---|
| 547 | //////////////////////////////////////////////////// |
---|
| 548 | |
---|
| 549 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 550 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 551 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
| 552 | |
---|
| 553 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
| 554 | sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
| 555 | |
---|
| 556 | //////////////////////////////////////////////////// |
---|
| 557 | // Registers controlled by the XRAM_RSP fsm |
---|
| 558 | //////////////////////////////////////////////////// |
---|
| 559 | |
---|
| 560 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 561 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 562 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 563 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 564 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 565 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 566 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 567 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 568 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 569 | sc_signal<copy_t> r_xram_rsp_victim_d_copies; // victim line copies |
---|
| 570 | sc_signal<copy_t> r_xram_rsp_victim_i_copies; // victim line copies |
---|
| 571 | sc_signal<copy_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 572 | sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data |
---|
| 573 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
| 574 | |
---|
| 575 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
| 576 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 577 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 578 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 579 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 580 | sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 581 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 582 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response |
---|
| 583 | |
---|
| 584 | // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) |
---|
| 585 | sc_signal<bool> r_xram_rsp_to_init_cmd_req; // Valid request |
---|
| 586 | sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast; // Broadcast request |
---|
| 587 | sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index; |
---|
| 588 | sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry |
---|
| 589 | sc_signal<copy_t> r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies |
---|
| 590 | sc_signal<copy_t> r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies |
---|
| 591 | |
---|
| 592 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
---|
| 593 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
| 594 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
---|
| 595 | sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data |
---|
| 596 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
---|
| 597 | |
---|
| 598 | //////////////////////////////////////////////////// |
---|
| 599 | // Registers controlled by the IXR_CMD fsm |
---|
| 600 | //////////////////////////////////////////////////// |
---|
| 601 | |
---|
| 602 | sc_signal<int> r_ixr_cmd_fsm; |
---|
| 603 | sc_signal<size_t> r_ixr_cmd_cpt; |
---|
| 604 | |
---|
| 605 | //////////////////////////////////////////////////// |
---|
| 606 | // Registers controlled by TGT_RSP fsm |
---|
| 607 | //////////////////////////////////////////////////// |
---|
| 608 | |
---|
| 609 | sc_signal<int> r_tgt_rsp_fsm; |
---|
| 610 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
| 611 | |
---|
| 612 | //////////////////////////////////////////////////// |
---|
| 613 | // Registers controlled by INIT_CMD fsm |
---|
| 614 | //////////////////////////////////////////////////// |
---|
| 615 | |
---|
| 616 | sc_signal<int> r_init_cmd_fsm; |
---|
| 617 | sc_signal<size_t> r_init_cmd_cpt; |
---|
| 618 | sc_signal<size_t> r_init_cmd_target; |
---|
| 619 | sc_signal<bool> r_init_cmd_inst; |
---|
| 620 | |
---|
| 621 | //////////////////////////////////////////////////// |
---|
| 622 | // Registers controlled by ALLOC_DIR fsm |
---|
| 623 | //////////////////////////////////////////////////// |
---|
| 624 | |
---|
| 625 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 626 | |
---|
| 627 | //////////////////////////////////////////////////// |
---|
| 628 | // Registers controlled by ALLOC_TRT fsm |
---|
| 629 | //////////////////////////////////////////////////// |
---|
| 630 | |
---|
| 631 | sc_signal<int> r_alloc_trt_fsm; |
---|
| 632 | |
---|
| 633 | //////////////////////////////////////////////////// |
---|
| 634 | // Registers controlled by ALLOC_UPT fsm |
---|
| 635 | //////////////////////////////////////////////////// |
---|
| 636 | |
---|
| 637 | sc_signal<int> r_alloc_upt_fsm; |
---|
| 638 | |
---|
| 639 | }; // end class VciMemCacheV2S |
---|
| 640 | |
---|
| 641 | }} |
---|
| 642 | |
---|
| 643 | #endif |
---|
| 644 | |
---|
| 645 | // Local Variables: |
---|
| 646 | // tab-width: 4 |
---|
| 647 | // c-basic-offset: 4 |
---|
| 648 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 649 | // indent-tabs-mode: nil |
---|
| 650 | // End: |
---|
| 651 | |
---|
| 652 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 653 | |
---|