source: trunk/modules/vci_mem_cache_v2s/caba/source/include/vci_mem_cache_v2s.h @ 41

Last change on this file since 41 was 41, checked in by gao, 14 years ago

Special for cc_vcache and cc_vcache_multi
File size: 27.6 KB
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1/* -*- c++ -*-
2 * File         : vci_mem_cache_v2s.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 */
29/*
30 *
31 * Modifications done by Christophe Choichillon on the 7/04/2009:
32 * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33 * - Adding a new VCI target port for the CLEANUP network
34 * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35 *
36 * Modifications to do :
37 * - Adding new variables used by the CLEANUP FSM
38 *
39 */
40
41#ifndef SOCLIB_CABA_MEM_CACHE_V2S_H
42#define SOCLIB_CABA_MEM_CACHE_V2S_H
43
44#include <inttypes.h>
45#include <systemc>
46#include <list>
47#include <cassert>
48#include "arithmetics.h"
49#include "alloc_elems.h"
50#include "caba_base_module.h"
51#include "vci_target.h"
52#include "vci_initiator.h"
53#include "generic_fifo.h"
54#include "mapping_table.h"
55#include "int_tab.h"
56#include "mem_cache_directory_v2.h"
57#include "xram_transaction_v2.h"
58#include "update_tab_v2.h"
59#include "atomic_tab_v2.h"
60
61#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
62#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
63#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
64
65namespace soclib {  namespace caba {
66  using namespace sc_core;
67
68  template<typename vci_param>
69    class VciMemCacheV2S
70    : public soclib::caba::BaseModule
71    {
72      typedef sc_dt::sc_uint<40> addr_t;
73      typedef typename vci_param::fast_addr_t vci_addr_t;
74      typedef uint32_t data_t;
75      typedef uint32_t tag_t;
76      typedef uint32_t size_t;
77      typedef uint32_t be_t;
78      typedef uint32_t copy_t;
79
80      /* States of the TGT_CMD fsm */
81      enum tgt_cmd_fsm_state_e{
82        TGT_CMD_IDLE,
83        TGT_CMD_READ,
84        TGT_CMD_READ_EOP,
85        TGT_CMD_WRITE,
86        TGT_CMD_ATOMIC,
87      };
88
89      /* States of the TGT_RSP fsm */
90      enum tgt_rsp_fsm_state_e{
91        TGT_RSP_READ_IDLE,
92        TGT_RSP_WRITE_IDLE,
93        TGT_RSP_LLSC_IDLE,
94        TGT_RSP_XRAM_IDLE,
95        TGT_RSP_INIT_IDLE,
96        TGT_RSP_CLEANUP_IDLE,
97        TGT_RSP_READ,
98        TGT_RSP_WRITE,
99        TGT_RSP_LLSC,
100        TGT_RSP_XRAM,
101        TGT_RSP_INIT,
102        TGT_RSP_CLEANUP,
103      };
104
105      /* States of the INIT_CMD fsm */
106      enum init_cmd_fsm_state_e{
107        INIT_CMD_INVAL_IDLE,
108        INIT_CMD_INVAL_SEL,
109        INIT_CMD_INVAL_NLINE,
110        INIT_CMD_UPDT_IDLE,
111        INIT_CMD_UPDT_SEL,
112        INIT_CMD_BRDCAST,
113        INIT_CMD_UPDT_NLINE,
114        INIT_CMD_UPDT_INDEX,
115        INIT_CMD_UPDT_DATA,
116        INIT_CMD_SC_UPDT_IDLE,
117        INIT_CMD_SC_UPDT_SEL,
118        INIT_CMD_SC_BRDCAST,
119        INIT_CMD_SC_UPDT_NLINE,
120        INIT_CMD_SC_UPDT_INDEX,
121        INIT_CMD_SC_UPDT_DATA,
122      };
123
124      /* States of the INIT_RSP fsm */
125      enum init_rsp_fsm_state_e{
126        INIT_RSP_IDLE,
127        INIT_RSP_UPT_LOCK,
128        INIT_RSP_UPT_CLEAR,
129        INIT_RSP_END,
130      };
131
132      /* States of the READ fsm */
133      enum read_fsm_state_e{
134        READ_IDLE,
135        READ_DIR_LOCK,
136        READ_DIR_HIT,
137        READ_RSP,
138        READ_TRT_LOCK,
139        READ_TRT_SET,
140        READ_XRAM_REQ,
141      };
142
143      /* States of the WRITE fsm */
144      enum write_fsm_state_e{
145        WRITE_IDLE,
146        WRITE_NEXT,
147        WRITE_DIR_LOCK,
148        WRITE_DIR_HIT_READ,
149        WRITE_DIR_HIT,
150        WRITE_DIR_HIT_RSP,
151        WRITE_UPT_LOCK,
152        WRITE_WAIT_UPT,
153        WRITE_UPDATE,
154        WRITE_RSP,
155        WRITE_TRT_LOCK,
156        WRITE_TRT_DATA,
157        WRITE_TRT_SET,
158        WRITE_WAIT_TRT,
159        WRITE_XRAM_REQ,
160        WRITE_TRT_WRITE_LOCK,
161        WRITE_INVAL_LOCK,
162        WRITE_DIR_INVAL,
163        WRITE_INVAL,
164        WRITE_XRAM_SEND,
165      };
166
167      /* States of the IXR_RSP fsm */
168      enum ixr_rsp_fsm_state_e{
169        IXR_RSP_IDLE,
170        IXR_RSP_ACK,
171        IXR_RSP_TRT_ERASE,
172        IXR_RSP_TRT_READ,
173      };
174
175      /* States of the XRAM_RSP fsm */
176      enum xram_rsp_fsm_state_e{
177        XRAM_RSP_IDLE,
178        XRAM_RSP_TRT_COPY,
179        XRAM_RSP_TRT_DIRTY,
180        XRAM_RSP_DIR_LOCK,
181        XRAM_RSP_DIR_UPDT,
182        XRAM_RSP_DIR_RSP,
183        XRAM_RSP_INVAL_LOCK,
184        XRAM_RSP_INVAL_WAIT,
185        XRAM_RSP_INVAL,
186        XRAM_RSP_WRITE_DIRTY,
187      };
188
189      /* States of the IXR_CMD fsm */
190      enum ixr_cmd_fsm_state_e{
191        IXR_CMD_READ_IDLE,
192        IXR_CMD_WRITE_IDLE,
193        IXR_CMD_LLSC_IDLE,
194        IXR_CMD_XRAM_IDLE,
195        IXR_CMD_READ_NLINE,
196        IXR_CMD_WRITE_NLINE,
197        IXR_CMD_LLSC_NLINE,
198        IXR_CMD_XRAM_DATA,
199      };
200
201      /* States of the LLSC fsm */
202      enum llsc_fsm_state_e{
203        LLSC_IDLE,
204        LL_DIR_LOCK,
205        LL_DIR_HIT,
206        LL_RSP,
207        SC_DIR_LOCK,
208        SC_DIR_HIT,
209        SC_UPT_LOCK,
210        SC_WAIT_UPT,
211        SC_UPDATE,
212        SC_TRT_LOCK,
213        SC_INVAL_LOCK,
214        SC_DIR_INVAL,
215        SC_INVAL,
216        SC_XRAM_SEND,
217        SC_RSP_FALSE,
218        SC_RSP_TRUE,
219        LLSC_TRT_LOCK,
220        LLSC_TRT_SET,
221        LLSC_XRAM_REQ,
222      };
223
224      /* States of the CLEANUP fsm */
225      enum cleanup_fsm_state_e{
226        CLEANUP_IDLE,
227        CLEANUP_DIR_LOCK,
228        CLEANUP_DIR_WRITE,
229        CLEANUP_UPT_LOCK,
230        CLEANUP_UPT_WRITE,
231        CLEANUP_WRITE_RSP,
232        CLEANUP_RSP,
233      };
234
235      /* States of the ALLOC_DIR fsm */
236      enum alloc_dir_fsm_state_e{
237        ALLOC_DIR_READ,
238        ALLOC_DIR_WRITE,
239        ALLOC_DIR_LLSC,
240        ALLOC_DIR_CLEANUP,
241        ALLOC_DIR_XRAM_RSP,
242      };
243
244      /* States of the ALLOC_TRT fsm */
245      enum alloc_trt_fsm_state_e{
246        ALLOC_TRT_READ,
247        ALLOC_TRT_WRITE,
248        ALLOC_TRT_LLSC,
249        ALLOC_TRT_XRAM_RSP,
250        ALLOC_TRT_IXR_RSP,
251      };
252
253      /* States of the ALLOC_UPT fsm */
254      enum alloc_upt_fsm_state_e{
255        ALLOC_UPT_WRITE,
256        ALLOC_UPT_XRAM_RSP,
257        ALLOC_UPT_INIT_RSP,
258        ALLOC_UPT_CLEANUP,
259        ALLOC_UPT_LLSC,
260      };
261
262      uint32_t     m_cpt_cycles;            // Counter of cycles
263      uint32_t     m_cpt_read;              // Number of READ transactions
264      uint32_t     m_cpt_read_miss;         // Number of MISS READ
265      uint32_t     m_cpt_write;             // Number of WRITE transactions
266      uint32_t     m_cpt_write_miss;        // Number of MISS WRITE
267      uint32_t     m_cpt_write_cells;       // Cumulated length for WRITE transactions
268      uint32_t     m_cpt_write_dirty;       // Cumulated length for WRITE transactions
269      uint32_t     m_cpt_update;            // Number of UPDATE transactions
270      uint32_t     m_cpt_update_mult;       // Number of targets for UPDATE
271      uint32_t     m_cpt_inval;             // Number of INVAL  transactions
272      uint32_t     m_cpt_inval_mult;        // Number of targets for INVAL 
273      uint32_t     m_cpt_inval_brdcast;     // Number of BROADCAST INVAL 
274      uint32_t     m_cpt_cleanup;           // Number of CLEANUP transactions
275      uint32_t     m_cpt_ll;                // Number of LL transactions
276      uint32_t     m_cpt_sc;                // Number of SC transactions
277
278      protected:
279
280      SC_HAS_PROCESS(VciMemCacheV2S);
281
282      public:
283      sc_in<bool>                               p_clk;
284      sc_in<bool>                               p_resetn;
285      soclib::caba::VciTarget<vci_param>        p_vci_tgt;
286      soclib::caba::VciTarget<vci_param>        p_vci_tgt_cleanup;
287      soclib::caba::VciInitiator<vci_param>     p_vci_ini;     
288      soclib::caba::VciInitiator<vci_param>     p_vci_ixr;
289
290      VciMemCacheV2S(
291          sc_module_name name,                              // Instance Name
292          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
293          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
294          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
295          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
296          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
297          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
298          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
299          size_t nways,                                   // Number of ways per set
300          size_t nsets,                                   // Number of sets
301          size_t nwords);                                 // Number of words per line
302
303      ~VciMemCacheV2S();
304
305      void transition();
306
307      void genMoore();
308
309      void print_stats();
310
311      private:
312
313      // Component attributes
314      const size_t              m_initiators;           // Number of initiators
315      const size_t              m_ways;                 // Number of ways in a set
316      const size_t              m_sets;                 // Number of cache sets
317      const size_t              m_words;                        // Number of words in a line
318      const size_t              m_srcid_ixr;                // Srcid for requests to XRAM
319      const size_t              m_srcid_ini;                // Srcid for requests to processors
320      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
321      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
322      vci_addr_t                        *m_coherence_table;     // address(srcid)
323      AtomicTab                 m_atomic_tab;           // atomic access table
324      TransactionTab                    m_transaction_tab;          // xram transaction table
325      UpdateTab                 m_update_tab;               // pending update & invalidate
326      CacheDirectory                    m_cache_directory;          // data cache directory
327
328      data_t                           ***m_cache_data;         // data array[set][way][word]
329
330      // adress masks
331      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
332      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
333      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
334      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
335
336      //////////////////////////////////////////////////
337      // Others registers
338      //////////////////////////////////////////////////
339      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
340
341      //////////////////////////////////////////////////
342      // Registers controlled by the TGT_CMD fsm
343      //////////////////////////////////////////////////
344
345      // Fifo between TGT_CMD fsm and READ fsm
346      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
347      GenericFifo<size_t>    m_cmd_read_length_fifo;
348      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
349      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
350      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
351
352      // Fifo between TGT_CMD fsm and WRITE fsm   
353      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
354      GenericFifo<bool>      m_cmd_write_eop_fifo;
355      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
356      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
357      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
358      GenericFifo<data_t>    m_cmd_write_data_fifo;
359      GenericFifo<be_t>      m_cmd_write_be_fifo;
360
361      // Fifo between TGT_CMD fsm and LLSC fsm
362      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
363      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
364      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
365      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
366      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
367      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
368
369      sc_signal<int>         r_tgt_cmd_fsm;
370
371      sc_signal<size_t>      r_index;
372      size_t nseg;
373      size_t ncseg;
374      soclib::common::Segment  **m_seg;
375      soclib::common::Segment  **m_cseg;
376      ///////////////////////////////////////////////////////
377      // Registers controlled by the READ fsm
378      ///////////////////////////////////////////////////////
379
380      sc_signal<int>         r_read_fsm;        // FSM state
381      sc_signal<copy_t>      r_read_d_copies;   // bit-vector of copies
382      sc_signal<copy_t>      r_read_i_copies;   // bit-vector of copies
383      sc_signal<tag_t>       r_read_tag;            // cache line tag (in directory)
384      sc_signal<bool>        r_read_is_cnt;         // is_cnt bit (in directory)
385      sc_signal<bool>        r_read_lock;           // lock bit (in directory)
386      sc_signal<bool>        r_read_dirty;          // dirty bit (in directory)
387      sc_signal<size_t>      r_read_count;      // number of copies
388      sc_signal<data_t>     *r_read_data;       // data (one cache line)
389      sc_signal<size_t>      r_read_way;        // associative way (in cache)
390      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
391
392      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
393      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
394      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
395      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
396
397      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
398      sc_signal<bool>      r_read_to_tgt_rsp_req;       // valid request
399      sc_signal<size_t>    r_read_to_tgt_rsp_srcid;         // Transaction srcid
400      sc_signal<size_t>    r_read_to_tgt_rsp_trdid;         // Transaction trdid
401      sc_signal<size_t>    r_read_to_tgt_rsp_pktid;         // Transaction pktid
402      sc_signal<data_t>   *r_read_to_tgt_rsp_data;          // data (one cache line)
403      sc_signal<size_t>    r_read_to_tgt_rsp_word;      // first word of the response
404      sc_signal<size_t>    r_read_to_tgt_rsp_length;    // length of the response
405
406      ///////////////////////////////////////////////////////////////
407      // Registers controlled by the WRITE fsm
408      ///////////////////////////////////////////////////////////////
409
410      sc_signal<int>       r_write_fsm;             // FSM state
411      sc_signal<addr_t>    r_write_address;         // first word address
412      sc_signal<size_t>    r_write_word_index;      // first word index in line
413      sc_signal<size_t>    r_write_word_count;      // number of words in line
414      sc_signal<size_t>    r_write_srcid;           // transaction srcid
415      sc_signal<size_t>    r_write_trdid;           // transaction trdid
416      sc_signal<size_t>    r_write_pktid;           // transaction pktid
417      sc_signal<data_t>   *r_write_data;            // data (one cache line)   
418      sc_signal<be_t>     *r_write_be;              // one byte enable per word
419      sc_signal<bool>      r_write_byte;            // is it a byte write
420      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
421      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
422      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
423      sc_signal<copy_t>    r_write_d_copies;        // bit vector of copies
424      sc_signal<copy_t>    r_write_i_copies;        // bit vector of copies
425      sc_signal<size_t>    r_write_count;           // number of copies
426      sc_signal<size_t>    r_write_way;                 // way of the line
427      sc_signal<size_t>    r_write_trt_index;       // index in Transaction Table
428      sc_signal<size_t>    r_write_upt_index;       // index in Update Table
429
430      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
431      sc_signal<bool>      r_write_to_tgt_rsp_req;              // valid request
432      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
433      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;    // transaction trdid
434      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;    // transaction pktid
435
436      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
437      sc_signal<bool>      r_write_to_ixr_cmd_req;      // valid request
438      sc_signal<bool>      r_write_to_ixr_cmd_write;    // write request
439      sc_signal<addr_t>    r_write_to_ixr_cmd_nline;    // cache line index
440      sc_signal<data_t>   *r_write_to_ixr_cmd_data;         // cache line data
441      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;    // index in Transaction Table
442
443      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
444      sc_signal<bool>      r_write_to_init_cmd_req;         // valid request
445      sc_signal<bool>      r_write_to_init_cmd_brdcast;     // brdcast request
446      sc_signal<addr_t>    r_write_to_init_cmd_nline;       // cache line index
447      sc_signal<size_t>    r_write_to_init_cmd_trdid;       // index in Update Table
448      sc_signal<copy_t>    r_write_to_init_cmd_d_copies;    // bit_vector of L1 to update
449      sc_signal<data_t>   *r_write_to_init_cmd_data;        // data (one cache line)
450      sc_signal<bool>     *r_write_to_init_cmd_we;              // word enable
451      sc_signal<size_t>    r_write_to_init_cmd_count;       // number of words in line
452      sc_signal<size_t>    r_write_to_init_cmd_index;       // index of first word in line
453
454      /////////////////////////////////////////////////////////
455      // Registers controlled by INIT_RSP fsm
456      //////////////////////////////////////////////////////////
457
458      sc_signal<int>       r_init_rsp_fsm;        // FSM state
459      sc_signal<size_t>    r_init_rsp_upt_index;  // index in the Update Table
460      sc_signal<size_t>    r_init_rsp_srcid;      // pending write srcid     
461      sc_signal<size_t>    r_init_rsp_trdid;      // pending write trdid     
462      sc_signal<size_t>    r_init_rsp_pktid;      // pending write pktid     
463      sc_signal<addr_t>    r_init_rsp_nline;      // pending write nline     
464
465      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
466      sc_signal<bool>        r_init_rsp_to_tgt_rsp_req;         // valid request
467      sc_signal<size_t>    r_init_rsp_to_tgt_rsp_srcid;         // Transaction srcid
468      sc_signal<size_t>    r_init_rsp_to_tgt_rsp_trdid;         // Transaction trdid
469      sc_signal<size_t>    r_init_rsp_to_tgt_rsp_pktid;         // Transaction pktid
470
471      ///////////////////////////////////////////////////////
472      // Registers controlled by CLEANUP fsm
473      ///////////////////////////////////////////////////////
474
475      sc_signal<int>         r_cleanup_fsm;         // FSM state
476      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
477      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
478      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
479      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
480
481      sc_signal<copy_t>      r_cleanup_d_copies;    // bit-vector of copies
482      sc_signal<copy_t>      r_cleanup_i_copies;    // bit-vector of copies
483      sc_signal<copy_t>      r_cleanup_count;       // number of copies
484      sc_signal<tag_t>       r_cleanup_tag;             // cache line tag (in directory)
485      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
486      sc_signal<bool>        r_cleanup_lock;        // lock bit (in directory)
487      sc_signal<bool>        r_cleanup_dirty;       // dirty bit (in directory)
488      sc_signal<size_t>      r_cleanup_way;             // associative way (in cache)
489
490      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
491      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
492      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
493      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
494
495      sc_signal<size_t>      r_cleanup_index;       // index of the INVAL line (in the UPT)
496
497      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
498      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
499      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
500      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;  // transaction trdid
501      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;  // transaction pktid
502
503      ///////////////////////////////////////////////////////
504      // Registers controlled by LLSC fsm
505      ///////////////////////////////////////////////////////
506
507      sc_signal<int>       r_llsc_fsm;          // FSM state
508      sc_signal<data_t>    r_llsc_data;             // read data word
509      sc_signal<uint32_t>  r_llsc_lfsr;         // lfsr for random introducing
510      sc_signal<copy_t>    r_llsc_i_copies;         // bit_vector of copies
511      sc_signal<copy_t>    r_llsc_d_copies;         // bit_vector of copies
512      sc_signal<copy_t>    r_llsc_count;            // number of copies
513      sc_signal<bool>      r_llsc_is_cnt;           // is_cnt bit (in directory)
514      sc_signal<bool>      r_llsc_dirty;            // dirty bit (in directory)
515      sc_signal<size_t>    r_llsc_way;              // way in directory
516      sc_signal<size_t>    r_llsc_set;              // set in directory
517      sc_signal<data_t>    r_llsc_tag;              // cache line tag (in directory)
518      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
519      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
520
521      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)   
522      sc_signal<bool>      r_llsc_to_ixr_cmd_req;   // valid request
523      sc_signal<addr_t>    r_llsc_to_ixr_cmd_nline; // cache line index
524      sc_signal<size_t>    r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
525      sc_signal<bool>      r_llsc_to_ixr_cmd_write; // write request
526      sc_signal<data_t>   *r_llsc_to_ixr_cmd_data;  // cache line data
527
528
529      // Buffer between LLSC fsm and TGT_RSP fsm
530      sc_signal<bool>      r_llsc_to_tgt_rsp_req;   // valid request
531      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
532      sc_signal<size_t>    r_llsc_to_tgt_rsp_srcid; // Transaction srcid
533      sc_signal<size_t>    r_llsc_to_tgt_rsp_trdid; // Transaction trdid
534      sc_signal<size_t>    r_llsc_to_tgt_rsp_pktid; // Transaction pktid
535
536      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
537      sc_signal<bool>      r_llsc_to_init_cmd_req;          // valid request
538      sc_signal<bool>      r_llsc_to_init_cmd_brdcast;      // brdcast request
539      sc_signal<addr_t>    r_llsc_to_init_cmd_nline;        // cache line index
540      sc_signal<size_t>    r_llsc_to_init_cmd_trdid;        // index in Update Table
541      sc_signal<copy_t>    r_llsc_to_init_cmd_d_copies;     // bit_vector of L1 to update
542      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
543      sc_signal<size_t>    r_llsc_to_init_cmd_index;        // index of the word in line
544
545      ////////////////////////////////////////////////////
546      // Registers controlled by the IXR_RSP fsm
547      ////////////////////////////////////////////////////
548
549      sc_signal<int>       r_ixr_rsp_fsm;       // FSM state
550      sc_signal<size_t>    r_ixr_rsp_trt_index; // TRT entry index
551      sc_signal<size_t>    r_ixr_rsp_cpt;           // word counter
552
553      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
554      sc_signal<bool>     *r_ixr_rsp_to_xram_rsp_rok;   // A xram response is ready
555
556      ////////////////////////////////////////////////////
557      // Registers controlled by the XRAM_RSP fsm
558      ////////////////////////////////////////////////////
559
560      sc_signal<int>       r_xram_rsp_fsm;                      // FSM state
561      sc_signal<size_t>    r_xram_rsp_trt_index;            // TRT entry index
562      TransactionTabEntry  r_xram_rsp_trt_buf;              // TRT entry local buffer
563      sc_signal<bool>      r_xram_rsp_victim_inval;         // victim line invalidate
564      sc_signal<bool>      r_xram_rsp_victim_is_cnt;    // victim line inst bit
565      sc_signal<bool>      r_xram_rsp_victim_dirty;         // victim line dirty bit
566      sc_signal<size_t>    r_xram_rsp_victim_way;           // victim line way
567      sc_signal<size_t>    r_xram_rsp_victim_set;           // victim line set
568      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
569      sc_signal<copy_t>    r_xram_rsp_victim_d_copies;  // victim line copies
570      sc_signal<copy_t>    r_xram_rsp_victim_i_copies;  // victim line copies
571      sc_signal<copy_t>    r_xram_rsp_victim_count;         // victim line number of copies
572      sc_signal<data_t>   *r_xram_rsp_victim_data;          // victim line data
573      sc_signal<size_t>    r_xram_rsp_upt_index;            // UPT entry index
574
575      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
576      sc_signal<bool>      r_xram_rsp_to_tgt_rsp_req;   // Valid request
577      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
578      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
579      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
580      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;  // data (one cache line)
581      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;  // first word index
582      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;// length of the response
583
584      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
585      sc_signal<bool>        r_xram_rsp_to_init_cmd_req;    // Valid request
586      sc_signal<bool>      r_xram_rsp_to_init_cmd_brdcast;  // Broadcast request
587      sc_signal<addr_t>    r_xram_rsp_to_init_cmd_nline;    // cache line index;
588      sc_signal<size_t>    r_xram_rsp_to_init_cmd_trdid;    // index of UPT entry
589      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies
590      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies
591
592      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
593      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_req;   // Valid request
594      sc_signal<addr_t>    r_xram_rsp_to_ixr_cmd_nline; // cache line index
595      sc_signal<data_t>   *r_xram_rsp_to_ixr_cmd_data;  // cache line data
596      sc_signal<size_t>    r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
597
598      ////////////////////////////////////////////////////
599      // Registers controlled by the IXR_CMD fsm
600      ////////////////////////////////////////////////////
601
602      sc_signal<int>       r_ixr_cmd_fsm;
603      sc_signal<size_t>    r_ixr_cmd_cpt;
604
605      ////////////////////////////////////////////////////
606      // Registers controlled by TGT_RSP fsm
607      ////////////////////////////////////////////////////
608
609      sc_signal<int>       r_tgt_rsp_fsm;
610      sc_signal<size_t>    r_tgt_rsp_cpt;
611
612      ////////////////////////////////////////////////////
613      // Registers controlled by INIT_CMD fsm
614      ////////////////////////////////////////////////////
615
616      sc_signal<int>      r_init_cmd_fsm;
617      sc_signal<size_t>   r_init_cmd_cpt;
618      sc_signal<size_t>   r_init_cmd_target;
619      sc_signal<bool>     r_init_cmd_inst;
620
621      ////////////////////////////////////////////////////
622      // Registers controlled by ALLOC_DIR fsm
623      ////////////////////////////////////////////////////
624
625      sc_signal<int>            r_alloc_dir_fsm;
626
627      ////////////////////////////////////////////////////
628      // Registers controlled by ALLOC_TRT fsm
629      ////////////////////////////////////////////////////
630
631      sc_signal<int>            r_alloc_trt_fsm;
632
633      ////////////////////////////////////////////////////
634      // Registers controlled by ALLOC_UPT fsm
635      ////////////////////////////////////////////////////
636
637      sc_signal<int>            r_alloc_upt_fsm;
638
639    }; // end class VciMemCacheV2S
640
641}}
642
643#endif
644
645// Local Variables:
646// tab-width: 4
647// c-basic-offset: 4
648// c-file-offsets:((innamespace . 0)(inline-open . 0))
649// indent-tabs-mode: nil
650// End:
651
652// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
653
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