[551] | 1 | |
---|
| 2 | /* -*- c++ -*- |
---|
| 3 | * |
---|
| 4 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
| 5 | * |
---|
| 6 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
| 7 | * |
---|
| 8 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
| 9 | * under the terms of the GNU Lesser General Public License as published |
---|
| 10 | * by the Free Software Foundation; version 2.1 of the License. |
---|
| 11 | * |
---|
| 12 | * SoCLib is distributed in the hope that it will be useful, but |
---|
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 15 | * Lesser General Public License for more details. |
---|
| 16 | * |
---|
| 17 | * You should have received a copy of the GNU Lesser General Public |
---|
| 18 | * License along with SoCLib; if not, write to the Free Software |
---|
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
| 20 | * 02110-1301 USA |
---|
| 21 | * |
---|
| 22 | * SOCLIB_LGPL_HEADER_END |
---|
| 23 | * |
---|
| 24 | * Copyright (c) UPMC, Lip6, SoC |
---|
| 25 | * manuel.bouyer@lip6.fr october 2013 |
---|
| 26 | * |
---|
| 27 | * Maintainers: bouyer |
---|
| 28 | */ |
---|
| 29 | |
---|
| 30 | ////////////////////////////////////////////////////////////////////////////////////// |
---|
| 31 | // This component is a SPI controller with a VCI interface |
---|
| 32 | // It supports only 32 or 64 bits VCI DATA width, but all addressable registers |
---|
| 33 | // contain 32 bits words. It supports VCI addresss lartger than 32 bits. |
---|
| 34 | // |
---|
| 35 | // This component can perform data transfers between one single file belonging |
---|
| 36 | // to the host system and a buffer in the memory of the virtual prototype. |
---|
| 37 | // The file name is an argument of the constructor. |
---|
| 38 | // This component has a DMA capability, and is both a target and an initiator. |
---|
| 39 | // The burst size (bytes) must be power of 2. |
---|
| 40 | // The burst size is typically a cache line. |
---|
| 41 | // The memory buffer must be aligned to a a burst boundary. |
---|
| 42 | // Both read and write transfers are supported. An IRQ is optionally |
---|
| 43 | // asserted when the transfer is completed. |
---|
| 44 | // |
---|
| 45 | |
---|
| 46 | #ifndef SOCLIB_VCI_SPI_H |
---|
| 47 | #define SOCLIB_VCI_SPI_H |
---|
| 48 | |
---|
| 49 | #include <stdint.h> |
---|
| 50 | #include <systemc> |
---|
| 51 | #include <unistd.h> |
---|
| 52 | #include "caba_base_module.h" |
---|
| 53 | #include "mapping_table.h" |
---|
| 54 | #include "vci_initiator.h" |
---|
| 55 | #include "vci_target.h" |
---|
| 56 | |
---|
| 57 | namespace soclib { |
---|
| 58 | namespace caba { |
---|
| 59 | |
---|
| 60 | using namespace sc_core; |
---|
| 61 | |
---|
| 62 | template<typename vci_param> |
---|
| 63 | class VciSpi |
---|
| 64 | : public caba::BaseModule |
---|
| 65 | { |
---|
| 66 | private: |
---|
| 67 | |
---|
| 68 | // Registers |
---|
| 69 | sc_signal<int> r_target_fsm; // target fsm state register |
---|
| 70 | sc_signal<int> r_initiator_fsm; // initiator fsm state register |
---|
| 71 | sc_signal<int> r_spi_fsm; // spi engine state |
---|
| 72 | sc_signal<uint64_t> r_txrx[2]; // data in/out |
---|
| 73 | sc_signal<uint32_t> r_divider; // SPI clk divider |
---|
| 74 | sc_signal<uint8_t> r_ss; // SPI slave select |
---|
| 75 | sc_signal<bool> r_ctrl_cpol; // clock polarity |
---|
| 76 | sc_signal<bool> r_ctrl_cpha; // clock phase |
---|
| 77 | sc_signal<bool> r_ctrl_ass; // auto slave select |
---|
| 78 | sc_signal<bool> r_ctrl_ie; // interrupt enable |
---|
| 79 | sc_signal<bool> r_ctrl_go_bsy; |
---|
| 80 | sc_signal<uint8_t> r_ctrl_char_len; // number of bits in xfer |
---|
| 81 | |
---|
| 82 | sc_signal<uint32_t> r_bit_count; |
---|
| 83 | sc_signal<uint32_t> r_clk_counter; |
---|
| 84 | sc_signal<bool> r_spi_clk; |
---|
| 85 | sc_signal<bool> r_spi_clk_previous; |
---|
| 86 | sc_signal<bool> r_spi_clk_ignore; |
---|
| 87 | sc_signal<bool> r_spi_out; |
---|
| 88 | sc_signal<bool> r_irq; |
---|
| 89 | |
---|
| 90 | sc_signal<bool> r_read; |
---|
| 91 | sc_signal<uint32_t> r_nblocks; // number of blocks in transfer |
---|
| 92 | sc_signal<uint64_t> r_buf_address; // memory buffer address |
---|
| 93 | sc_signal<uint32_t> r_index; // word index in local buffer |
---|
| 94 | sc_signal<uint32_t> r_latency_count; // latency counter |
---|
| 95 | sc_signal<uint32_t> r_words_count; // word counter (in a burst) |
---|
| 96 | sc_signal<uint32_t> r_burst_count; // burst counter (in a block) |
---|
| 97 | sc_signal<uint32_t> r_block_count; // block counter (in a transfer) |
---|
| 98 | sc_signal<uint32_t> r_burst_offset; // number of non aligned words |
---|
| 99 | sc_signal<uint32_t> r_burst_nwords; // number of words in a burst |
---|
| 100 | sc_signal<bool> r_go; // command from T_FSM to M_FSM |
---|
| 101 | |
---|
| 102 | sc_signal<typename vci_param::srcid_t > r_srcid; // save srcid |
---|
| 103 | sc_signal<typename vci_param::trdid_t > r_trdid; // save trdid |
---|
| 104 | sc_signal<typename vci_param::pktid_t > r_pktid; // save pktid |
---|
| 105 | |
---|
[558] | 106 | sc_signal<typename vci_param::data_t > r_rdata; // save reply |
---|
| 107 | |
---|
[551] | 108 | uint32_t* r_local_buffer; // capacity is one block |
---|
| 109 | |
---|
| 110 | // structural parameters |
---|
| 111 | std::list<soclib::common::Segment> m_seglist; |
---|
| 112 | uint32_t m_srcid; // initiator index |
---|
| 113 | const uint32_t m_words_per_block; // block size |
---|
| 114 | const uint32_t m_words_per_burst; // number of words in a burst |
---|
| 115 | const uint32_t m_bursts_per_block; // number of bursts in a block |
---|
| 116 | |
---|
| 117 | // methods |
---|
| 118 | void transition(); |
---|
| 119 | void genMoore(); |
---|
| 120 | |
---|
| 121 | // Master FSM states |
---|
| 122 | enum { |
---|
| 123 | M_IDLE = 0, |
---|
| 124 | |
---|
| 125 | M_READ_BLOCK = 1, |
---|
| 126 | M_READ_BURST = 2, |
---|
| 127 | M_READ_CMD = 3, |
---|
| 128 | M_READ_RSP = 4, |
---|
| 129 | M_READ_SUCCESS = 5, |
---|
| 130 | M_READ_ERROR = 6, |
---|
| 131 | |
---|
| 132 | M_WRITE_BURST = 7, |
---|
| 133 | M_WRITE_CMD = 8, |
---|
| 134 | M_WRITE_RSP = 9, |
---|
| 135 | M_WRITE_BLOCK = 10, |
---|
| 136 | M_WRITE_SUCCESS = 11, |
---|
| 137 | M_WRITE_ERROR = 12, |
---|
| 138 | }; |
---|
| 139 | |
---|
| 140 | // Target FSM states |
---|
| 141 | enum { |
---|
| 142 | T_IDLE = 0, |
---|
[558] | 143 | T_RSP_READ = 1, |
---|
| 144 | T_RSP_WRITE = 2, |
---|
| 145 | T_ERROR_READ = 3, |
---|
| 146 | T_ERROR_WRITE = 4 |
---|
[551] | 147 | }; |
---|
| 148 | |
---|
| 149 | // SPI FSM states |
---|
| 150 | enum { |
---|
| 151 | S_IDLE = 0, |
---|
| 152 | S_XMIT = 1, |
---|
| 153 | }; |
---|
| 154 | |
---|
| 155 | // Error codes values |
---|
| 156 | enum { |
---|
| 157 | VCI_READ_OK = 0, |
---|
| 158 | VCI_READ_ERROR = 1, |
---|
| 159 | VCI_WRITE_OK = 2, |
---|
| 160 | VCI_WRITE_ERROR = 3, |
---|
| 161 | }; |
---|
| 162 | |
---|
| 163 | /* transaction type, pktid field */ |
---|
| 164 | enum transaction_type_e |
---|
| 165 | { |
---|
| 166 | // b3 unused |
---|
| 167 | // b2 READ / NOT READ |
---|
| 168 | // Si READ |
---|
| 169 | // b1 DATA / INS |
---|
| 170 | // b0 UNC / MISS |
---|
| 171 | // Si NOT READ |
---|
| 172 | // b1 accÚs table llsc type SW / other |
---|
| 173 | // b2 WRITE/CAS/LL/SC |
---|
| 174 | TYPE_READ_DATA_UNC = 0x0, |
---|
| 175 | TYPE_READ_DATA_MISS = 0x1, |
---|
| 176 | TYPE_READ_INS_UNC = 0x2, |
---|
| 177 | TYPE_READ_INS_MISS = 0x3, |
---|
| 178 | TYPE_WRITE = 0x4, |
---|
| 179 | TYPE_CAS = 0x5, |
---|
| 180 | TYPE_LL = 0x6, |
---|
| 181 | TYPE_SC = 0x7 |
---|
| 182 | }; |
---|
| 183 | |
---|
| 184 | protected: |
---|
| 185 | |
---|
| 186 | SC_HAS_PROCESS(VciSpi); |
---|
| 187 | |
---|
| 188 | public: |
---|
| 189 | |
---|
| 190 | // ports |
---|
| 191 | sc_in<bool> p_clk; |
---|
| 192 | sc_in<bool> p_resetn; |
---|
| 193 | sc_out<bool> p_irq; |
---|
| 194 | soclib::caba::VciInitiator<vci_param> p_vci_initiator; |
---|
| 195 | soclib::caba::VciTarget<vci_param> p_vci_target; |
---|
| 196 | sc_out<bool> p_spi_ss; |
---|
| 197 | sc_out<bool> p_spi_clk; |
---|
| 198 | sc_out<bool> p_spi_mosi; |
---|
| 199 | sc_in<bool> p_spi_miso; |
---|
| 200 | |
---|
| 201 | void print_trace(); |
---|
| 202 | |
---|
| 203 | // Constructor |
---|
| 204 | VciSpi( |
---|
| 205 | sc_module_name name, |
---|
| 206 | const soclib::common::MappingTable &mt, |
---|
| 207 | const soclib::common::IntTab &srcid, |
---|
| 208 | const soclib::common::IntTab &tgtid, |
---|
| 209 | const uint32_t burst_size = 64); |
---|
| 210 | |
---|
| 211 | ~VciSpi(); |
---|
| 212 | |
---|
| 213 | }; |
---|
| 214 | |
---|
| 215 | }} |
---|
| 216 | |
---|
| 217 | #endif /* SOCLIB_VCI_SPI_H */ |
---|
| 218 | |
---|
| 219 | // Local Variables: |
---|
| 220 | // tab-width: 4 |
---|
| 221 | // c-basic-offset: 4 |
---|
| 222 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 223 | // indent-tabs-mode: nil |
---|
| 224 | // End: |
---|
| 225 | |
---|
| 226 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 227 | |
---|