[551] | 1 | |
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| 2 | /* -*- c++ -*- |
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| 3 | * |
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| 4 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 5 | * |
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| 6 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 7 | * |
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| 8 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU Lesser General Public License as published |
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| 10 | * by the Free Software Foundation; version 2.1 of the License. |
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| 11 | * |
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| 12 | * SoCLib is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * Lesser General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU Lesser General Public |
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| 18 | * License along with SoCLib; if not, write to the Free Software |
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| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 20 | * 02110-1301 USA |
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| 21 | * |
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| 22 | * SOCLIB_LGPL_HEADER_END |
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| 23 | * |
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| 24 | * Copyright (c) UPMC, Lip6, SoC |
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| 25 | * manuel.bouyer@lip6.fr october 2013 |
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| 26 | * |
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| 27 | * Maintainers: bouyer |
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| 28 | */ |
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| 29 | |
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| 30 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 31 | // This component is a SPI controller with a VCI interface |
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| 32 | // It supports only 32 or 64 bits VCI DATA width, but all addressable registers |
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| 33 | // contain 32 bits words. It supports VCI addresss lartger than 32 bits. |
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| 34 | // |
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| 35 | // This component can perform data transfers between one single file belonging |
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| 36 | // to the host system and a buffer in the memory of the virtual prototype. |
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| 37 | // The file name is an argument of the constructor. |
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| 38 | // This component has a DMA capability, and is both a target and an initiator. |
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| 39 | // The burst size (bytes) must be power of 2. |
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| 40 | // The burst size is typically a cache line. |
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| 41 | // The memory buffer must be aligned to a a burst boundary. |
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| 42 | // Both read and write transfers are supported. An IRQ is optionally |
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| 43 | // asserted when the transfer is completed. |
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| 44 | // |
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| 45 | |
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| 46 | #ifndef SOCLIB_VCI_SPI_H |
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| 47 | #define SOCLIB_VCI_SPI_H |
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| 48 | |
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| 49 | #include <stdint.h> |
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| 50 | #include <systemc> |
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| 51 | #include <unistd.h> |
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| 52 | #include "caba_base_module.h" |
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| 53 | #include "mapping_table.h" |
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| 54 | #include "vci_initiator.h" |
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| 55 | #include "vci_target.h" |
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[579] | 56 | #include "generic_fifo.h" |
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[551] | 57 | |
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| 58 | namespace soclib { |
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| 59 | namespace caba { |
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| 60 | |
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| 61 | using namespace sc_core; |
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| 62 | |
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| 63 | template<typename vci_param> |
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| 64 | class VciSpi |
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| 65 | : public caba::BaseModule |
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| 66 | { |
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| 67 | private: |
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| 68 | |
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| 69 | // Registers |
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| 70 | sc_signal<int> r_target_fsm; // target fsm state register |
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| 71 | sc_signal<int> r_initiator_fsm; // initiator fsm state register |
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| 72 | sc_signal<int> r_spi_fsm; // spi engine state |
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| 73 | sc_signal<uint64_t> r_txrx[2]; // data in/out |
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| 74 | sc_signal<uint32_t> r_divider; // SPI clk divider |
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| 75 | sc_signal<uint8_t> r_ss; // SPI slave select |
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| 76 | sc_signal<bool> r_ctrl_cpol; // clock polarity |
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| 77 | sc_signal<bool> r_ctrl_cpha; // clock phase |
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| 78 | sc_signal<bool> r_ctrl_ie; // interrupt enable |
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| 79 | sc_signal<uint8_t> r_ctrl_char_len; // number of bits in xfer |
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[579] | 80 | sc_signal<uint64_t> r_buf_address; // memory buffer address |
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| 81 | sc_signal<uint32_t> r_dma_count; // DMA burst count |
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| 82 | sc_signal<bool> r_read; // DMA read/write |
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[551] | 83 | |
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[579] | 84 | sc_signal<uint32_t> r_burst_word; // DMA burst word count |
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| 85 | sc_signal<bool> r_dma_error; // DMA error |
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| 86 | |
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| 87 | sc_signal<bool> r_spi_bsy; // SPI shifter busy |
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[565] | 88 | sc_signal<uint32_t> r_spi_bit_count; |
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[579] | 89 | sc_signal<uint32_t> r_spi_word_count; |
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[565] | 90 | sc_signal<uint32_t> r_spi_clk_counter; |
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[551] | 91 | sc_signal<bool> r_spi_clk; |
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| 92 | sc_signal<bool> r_spi_clk_previous; |
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| 93 | sc_signal<bool> r_spi_clk_ignore; |
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| 94 | sc_signal<bool> r_spi_out; |
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[565] | 95 | sc_signal<bool> r_spi_done; |
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[551] | 96 | sc_signal<bool> r_irq; |
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| 97 | |
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[579] | 98 | GenericFifo<typename vci_param::data_t> r_dma_fifo_read; // buffer data from SPI to network |
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| 99 | GenericFifo<typename vci_param::data_t> r_dma_fifo_write;// buffer data from network to SPI |
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[551] | 100 | |
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| 101 | sc_signal<typename vci_param::srcid_t > r_srcid; // save srcid |
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| 102 | sc_signal<typename vci_param::trdid_t > r_trdid; // save trdid |
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| 103 | sc_signal<typename vci_param::pktid_t > r_pktid; // save pktid |
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| 104 | |
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[558] | 105 | sc_signal<typename vci_param::data_t > r_rdata; // save reply |
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| 106 | |
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[551] | 107 | // structural parameters |
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| 108 | std::list<soclib::common::Segment> m_seglist; |
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| 109 | uint32_t m_srcid; // initiator index |
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[579] | 110 | const uint32_t m_burst_size; // number of words in a burst |
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[551] | 111 | const uint32_t m_words_per_burst; // number of words in a burst |
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[579] | 112 | const uint32_t m_byte2burst_shift; // log2(burst_size) |
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[551] | 113 | |
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| 114 | // methods |
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| 115 | void transition(); |
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| 116 | void genMoore(); |
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| 117 | |
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| 118 | // Master FSM states |
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| 119 | enum { |
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| 120 | M_IDLE = 0, |
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[579] | 121 | M_READ_WAIT = 1, |
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| 122 | M_READ_CMD = 2, |
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| 123 | M_READ_RSP = 3, |
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| 124 | M_WRITE_WAIT = 4, |
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| 125 | M_WRITE_CMD = 5, |
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| 126 | M_WRITE_RSP = 6, |
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| 127 | M_WRITE_END = 7 |
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[551] | 128 | }; |
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| 129 | |
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| 130 | // Target FSM states |
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| 131 | enum { |
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| 132 | T_IDLE = 0, |
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[558] | 133 | T_RSP_READ = 1, |
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| 134 | T_RSP_WRITE = 2, |
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| 135 | T_ERROR_READ = 3, |
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| 136 | T_ERROR_WRITE = 4 |
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[551] | 137 | }; |
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| 138 | |
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| 139 | // SPI FSM states |
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| 140 | enum { |
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| 141 | S_IDLE = 0, |
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[579] | 142 | S_DMA_RECEIVE = 1, |
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| 143 | S_DMA_SEND_START = 2, |
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| 144 | S_DMA_SEND = 3, |
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| 145 | S_DMA_SEND_END = 4, |
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| 146 | S_XMIT = 5, |
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[551] | 147 | }; |
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| 148 | |
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| 149 | // Error codes values |
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| 150 | enum { |
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| 151 | VCI_READ_OK = 0, |
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| 152 | VCI_READ_ERROR = 1, |
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| 153 | VCI_WRITE_OK = 2, |
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| 154 | VCI_WRITE_ERROR = 3, |
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| 155 | }; |
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| 156 | |
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| 157 | /* transaction type, pktid field */ |
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| 158 | enum transaction_type_e |
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| 159 | { |
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| 160 | // b3 unused |
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| 161 | // b2 READ / NOT READ |
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| 162 | // Si READ |
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| 163 | // b1 DATA / INS |
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| 164 | // b0 UNC / MISS |
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| 165 | // Si NOT READ |
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| 166 | // b1 accÚs table llsc type SW / other |
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| 167 | // b2 WRITE/CAS/LL/SC |
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| 168 | TYPE_READ_DATA_UNC = 0x0, |
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| 169 | TYPE_READ_DATA_MISS = 0x1, |
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| 170 | TYPE_READ_INS_UNC = 0x2, |
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| 171 | TYPE_READ_INS_MISS = 0x3, |
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| 172 | TYPE_WRITE = 0x4, |
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| 173 | TYPE_CAS = 0x5, |
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| 174 | TYPE_LL = 0x6, |
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| 175 | TYPE_SC = 0x7 |
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| 176 | }; |
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| 177 | |
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| 178 | protected: |
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| 179 | |
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| 180 | SC_HAS_PROCESS(VciSpi); |
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| 181 | |
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| 182 | public: |
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| 183 | |
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| 184 | // ports |
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| 185 | sc_in<bool> p_clk; |
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| 186 | sc_in<bool> p_resetn; |
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| 187 | sc_out<bool> p_irq; |
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| 188 | soclib::caba::VciInitiator<vci_param> p_vci_initiator; |
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| 189 | soclib::caba::VciTarget<vci_param> p_vci_target; |
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| 190 | sc_out<bool> p_spi_ss; |
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| 191 | sc_out<bool> p_spi_clk; |
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| 192 | sc_out<bool> p_spi_mosi; |
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| 193 | sc_in<bool> p_spi_miso; |
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| 194 | |
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| 195 | void print_trace(); |
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| 196 | |
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| 197 | // Constructor |
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| 198 | VciSpi( |
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| 199 | sc_module_name name, |
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| 200 | const soclib::common::MappingTable &mt, |
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| 201 | const soclib::common::IntTab &srcid, |
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| 202 | const soclib::common::IntTab &tgtid, |
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| 203 | const uint32_t burst_size = 64); |
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| 204 | |
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| 205 | ~VciSpi(); |
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| 206 | |
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| 207 | }; |
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| 208 | |
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| 209 | }} |
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| 210 | |
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| 211 | #endif /* SOCLIB_VCI_SPI_H */ |
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| 212 | |
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| 213 | // Local Variables: |
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| 214 | // tab-width: 4 |
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| 215 | // c-basic-offset: 4 |
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| 216 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 217 | // indent-tabs-mode: nil |
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| 218 | // End: |
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| 219 | |
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| 220 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 221 | |
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