[551] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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[558] | 24 | * manuel.bouyer@lip6.fr october 2013 |
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[551] | 25 | * |
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| 26 | * Maintainers: bouyer |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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[579] | 31 | #include <arithmetics.h> |
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[551] | 32 | #include <fcntl.h> |
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| 33 | #include "vci_spi.h" |
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| 34 | #include "vcispi.h" |
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| 35 | |
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| 36 | namespace soclib { namespace caba { |
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| 37 | |
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| 38 | #define tmpl(t) template<typename vci_param> t VciSpi<vci_param> |
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| 39 | |
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| 40 | using namespace soclib::caba; |
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| 41 | using namespace soclib::common; |
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| 42 | |
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| 43 | //////////////////////// |
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| 44 | tmpl(void)::transition() |
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| 45 | { |
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[579] | 46 | |
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| 47 | bool s_dma_bsy = (r_initiator_fsm != M_IDLE); |
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[551] | 48 | if(p_resetn.read() == false) |
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| 49 | { |
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[558] | 50 | r_initiator_fsm = M_IDLE; |
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| 51 | r_target_fsm = T_IDLE; |
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[579] | 52 | r_spi_fsm = S_IDLE; |
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| 53 | r_ss = 0; |
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| 54 | r_divider = 0xffff; |
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[558] | 55 | r_ctrl_char_len = 0; |
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[579] | 56 | r_ctrl_ie = false; |
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[558] | 57 | r_ctrl_cpol = false; |
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| 58 | r_ctrl_cpha = false; |
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[579] | 59 | r_spi_bsy = false; |
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| 60 | r_dma_count = 0; |
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[595] | 61 | r_dma_error = false; |
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[579] | 62 | r_spi_clk_counter = 0xffff; |
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| 63 | r_spi_clk = 0; |
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[565] | 64 | r_spi_done = false; |
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[551] | 65 | |
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| 66 | r_irq = false; |
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| 67 | r_read = false; |
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| 68 | |
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[579] | 69 | r_dma_fifo_read.init(); |
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| 70 | r_dma_fifo_write.init(); |
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| 71 | |
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[558] | 72 | return; |
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[551] | 73 | } |
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| 74 | |
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| 75 | ////////////////////////////////////////////////////////////////////////////// |
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| 76 | // The Target FSM controls the following registers: |
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| 77 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 78 | ////////////////////////////////////////////////////////////////////////////// |
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| 79 | |
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[565] | 80 | if (r_spi_done) |
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[579] | 81 | r_spi_bsy = false; |
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[565] | 82 | |
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[551] | 83 | switch(r_target_fsm) { |
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| 84 | //////////// |
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| 85 | case T_IDLE: |
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| 86 | { |
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[558] | 87 | if ( p_vci_target.cmdval.read() ) |
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| 88 | { |
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| 89 | r_srcid = p_vci_target.srcid.read(); |
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| 90 | r_trdid = p_vci_target.trdid.read(); |
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| 91 | r_pktid = p_vci_target.pktid.read(); |
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| 92 | uint32_t wdata = p_vci_target.wdata.read(); |
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| 93 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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[551] | 94 | |
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[558] | 95 | bool found = false; |
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| 96 | std::list<soclib::common::Segment>::iterator seg; |
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| 97 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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| 98 | { |
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| 99 | if ( seg->contains(address) ) found = true; |
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| 100 | } |
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[551] | 101 | |
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| 102 | |
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[558] | 103 | if (not found) { |
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| 104 | if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) |
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| 105 | r_target_fsm = T_ERROR_WRITE; |
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| 106 | else |
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| 107 | r_target_fsm = T_ERROR_READ; |
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| 108 | } else if (p_vci_target.cmd.read() != vci_param::CMD_READ && |
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| 109 | p_vci_target.cmd.read() != vci_param::CMD_WRITE) { |
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| 110 | r_target_fsm = T_ERROR_READ; |
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| 111 | } else { |
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[579] | 112 | bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_spi_bsy &!s_dma_bsy; |
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[558] | 113 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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| 114 | switch(cell) { |
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| 115 | case SPI_DATA_TXRX0: |
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| 116 | r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; |
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| 117 | if (write) { |
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| 118 | r_txrx[0] = |
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| 119 | (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | |
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| 120 | ((uint64_t)wdata); |
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| 121 | } |
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| 122 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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[551] | 123 | break; |
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[558] | 124 | case SPI_DATA_TXRX1: |
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| 125 | r_rdata = r_txrx[0] >> 32; |
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| 126 | if (write) { |
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| 127 | r_txrx[0] = |
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| 128 | (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | |
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| 129 | ((uint64_t)wdata << 32); |
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| 130 | } |
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| 131 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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[551] | 132 | break; |
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[558] | 133 | case SPI_DATA_TXRX2: |
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| 134 | r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; |
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| 135 | if (write) { |
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| 136 | r_txrx[1] = |
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| 137 | (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | |
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| 138 | ((uint64_t)wdata); |
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| 139 | } |
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| 140 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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[551] | 141 | break; |
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[558] | 142 | case SPI_DATA_TXRX3: |
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| 143 | r_rdata = r_txrx[1] >> 32; |
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| 144 | if (write) { |
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| 145 | r_txrx[1] = |
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| 146 | (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | |
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| 147 | ((uint64_t)wdata << 32); |
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| 148 | } |
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| 149 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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[551] | 150 | break; |
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[558] | 151 | case SPI_CTRL: |
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| 152 | { |
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| 153 | uint32_t data = 0; |
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| 154 | if (r_ctrl_cpol.read()) |
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| 155 | data |= SPI_CTRL_CPOL; |
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| 156 | if (r_ctrl_cpha.read()) |
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| 157 | data |= SPI_CTRL_CPHA; |
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| 158 | if (r_ctrl_ie.read()) |
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| 159 | data |= SPI_CTRL_IE_EN; |
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[579] | 160 | if (r_spi_bsy.read()) |
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[558] | 161 | data |= SPI_CTRL_GO_BSY; |
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[579] | 162 | if (s_dma_bsy) |
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| 163 | data |= SPI_CTRL_DMA_BSY; |
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[592] | 164 | if (r_dma_error) |
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| 165 | data |= SPI_CTRL_DMA_ERR; |
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[558] | 166 | data |= (uint32_t)r_ctrl_char_len.read(); |
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| 167 | r_rdata = data; |
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| 168 | if (write) { |
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| 169 | r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); |
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| 170 | r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); |
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| 171 | r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); |
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[564] | 172 | if (wdata & SPI_CTRL_GO_BSY) |
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[579] | 173 | r_spi_bsy = true; |
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[558] | 174 | r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); |
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[551] | 175 | #ifdef SOCLIB_MODULE_DEBUG |
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[558] | 176 | if ((wdata & SPI_CTRL_GO_BSY) != 0) { |
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| 177 | std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 178 | } |
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| 179 | #endif |
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| 180 | } else { |
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[595] | 181 | r_irq = false; |
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[558] | 182 | } |
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| 183 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 184 | break; |
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[551] | 185 | } |
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[558] | 186 | case SPI_DIVIDER: |
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| 187 | r_rdata = r_divider.read(); |
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| 188 | if (write) { |
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| 189 | #ifdef SOCLIB_MODULE_DEBUG |
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| 190 | std::cout << name() << " divider set to " << std::dec << wdata << std::endl; |
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[551] | 191 | #endif |
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[558] | 192 | r_divider = wdata; |
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| 193 | } |
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| 194 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 195 | break; |
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| 196 | case SPI_SS: |
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| 197 | r_rdata = r_ss.read(); |
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| 198 | if (write) { |
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| 199 | r_ss = wdata; |
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| 200 | } |
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| 201 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 202 | break; |
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[579] | 203 | case SPI_DMA_BASE: |
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| 204 | r_rdata = r_buf_address.read(); |
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| 205 | if (write) { |
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| 206 | r_buf_address = (r_buf_address & (uint64_t)0xffffffff00000000) | wdata; |
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| 207 | } |
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| 208 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 209 | break; |
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| 210 | case SPI_DMA_BASEH: |
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| 211 | r_rdata = r_buf_address >> 32; |
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| 212 | if (write) { |
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| 213 | r_buf_address = (r_buf_address & (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); |
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| 214 | } |
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| 215 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 216 | break; |
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| 217 | case SPI_DMA_COUNT: |
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| 218 | r_rdata = (r_dma_count.read() << m_byte2burst_shift) | |
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| 219 | r_read; |
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| 220 | if (write) { |
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| 221 | r_read = (wdata & 0x1); |
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| 222 | r_dma_count = wdata >> m_byte2burst_shift; |
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| 223 | r_ctrl_char_len = vci_param::B * 8; |
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| 224 | } |
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| 225 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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| 226 | break; |
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[558] | 227 | default: |
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| 228 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; |
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| 229 | break; |
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| 230 | } |
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[551] | 231 | } |
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| 232 | } |
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[558] | 233 | break; |
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[551] | 234 | } |
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[558] | 235 | //////////////////// |
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| 236 | case T_RSP_READ: |
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| 237 | case T_RSP_WRITE: |
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| 238 | case T_ERROR_READ: |
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| 239 | case T_ERROR_WRITE: |
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[551] | 240 | if (p_vci_target.rspack.read() ) { |
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[558] | 241 | r_target_fsm = T_IDLE; |
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[551] | 242 | } |
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[558] | 243 | break; |
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[551] | 244 | } // end switch target fsm |
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| 245 | |
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| 246 | |
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| 247 | |
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| 248 | |
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| 249 | ////////////////////////////////////////////////////////////////////////////// |
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| 250 | // the SPI FSM controls SPI signals |
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| 251 | ////////////////////////////////////////////////////////////////////////////// |
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[579] | 252 | if (r_spi_bsy == false) |
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[565] | 253 | r_spi_done = false; |
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[551] | 254 | switch (r_spi_fsm) { |
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| 255 | case S_IDLE: |
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[565] | 256 | r_spi_clk_counter = r_divider.read(); |
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[551] | 257 | r_spi_clk = 0; |
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| 258 | r_spi_clk_previous = r_ctrl_cpha; |
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| 259 | r_spi_clk_ignore = r_ctrl_cpha; |
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[565] | 260 | r_spi_bit_count = r_ctrl_char_len; |
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[579] | 261 | if (r_dma_count != 0) { |
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| 262 | if (r_read.read()) |
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| 263 | r_spi_fsm = S_DMA_SEND_START; |
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| 264 | else |
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| 265 | r_spi_fsm = S_DMA_RECEIVE; |
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| 266 | } else if (r_spi_bsy.read() && !r_spi_done.read()) { |
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| 267 | r_spi_fsm = S_XMIT; |
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[592] | 268 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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[579] | 269 | } |
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[551] | 270 | break; |
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[579] | 271 | case S_DMA_RECEIVE: |
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| 272 | { |
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| 273 | r_spi_clk_counter = r_divider.read(); |
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| 274 | r_spi_clk = 0; |
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| 275 | r_spi_clk_previous = r_ctrl_cpha; |
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| 276 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 277 | r_spi_bit_count = r_ctrl_char_len; |
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| 278 | if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) { |
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| 279 | if (r_dma_fifo_write.rok()) { |
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| 280 | typename vci_param::data_t v = r_dma_fifo_write.read(); |
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| 281 | r_dma_fifo_write.simple_get(); |
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| 282 | r_txrx[0] = v; |
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| 283 | r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; |
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| 284 | r_spi_fsm = S_XMIT; |
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| 285 | } else if (r_initiator_fsm == M_WRITE_END) { |
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| 286 | r_spi_fsm = S_IDLE; |
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| 287 | } |
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| 288 | } |
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| 289 | break; |
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| 290 | } |
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| 291 | case S_DMA_SEND_START: |
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| 292 | r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; |
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| 293 | r_spi_out = 1; |
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| 294 | r_txrx[0] = 0xffffffff; |
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| 295 | r_spi_fsm = S_XMIT; |
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| 296 | break; |
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| 297 | case S_DMA_SEND: |
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| 298 | r_spi_out = 1; |
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| 299 | r_spi_clk_counter = r_divider.read(); |
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| 300 | r_spi_clk = 0; |
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| 301 | r_spi_clk_previous = r_ctrl_cpha; |
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| 302 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 303 | r_spi_bit_count = r_ctrl_char_len; |
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| 304 | if (r_initiator_fsm != M_READ_CMD) { |
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| 305 | if (r_dma_fifo_read.wok()) { |
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| 306 | r_dma_fifo_read.simple_put( |
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| 307 | (typename vci_param::data_t)r_txrx[0]); |
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| 308 | r_spi_word_count = r_spi_word_count - 1; |
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[592] | 309 | r_txrx[0] = 0xffffffff; |
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[579] | 310 | if ( r_spi_word_count == 0 ) { |
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| 311 | r_spi_fsm = S_DMA_SEND_END; |
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| 312 | } else { |
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| 313 | r_spi_fsm = S_XMIT; |
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| 314 | } |
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| 315 | } |
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| 316 | } |
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| 317 | break; |
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| 318 | case S_DMA_SEND_END: |
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| 319 | if (r_initiator_fsm == M_IDLE) |
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| 320 | r_spi_fsm = S_IDLE; |
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| 321 | break; |
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[551] | 322 | case S_XMIT: |
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| 323 | { |
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| 324 | bool s_clk_sample; |
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| 325 | // on clock transition, sample input line, and shift data |
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| 326 | s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
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| 327 | if (!r_spi_clk_ignore) { |
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| 328 | if (r_spi_clk_previous == 0 && s_clk_sample == 1) { |
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[558] | 329 | // low to high transition: shift and sample |
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| 330 | r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); |
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| 331 | r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; |
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[565] | 332 | r_spi_bit_count = r_spi_bit_count - 1; |
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[551] | 333 | } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { |
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[558] | 334 | // high to low transition: change output, or stop |
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[565] | 335 | if (r_spi_bit_count == 0) { |
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[579] | 336 | if (r_initiator_fsm != M_IDLE) { |
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| 337 | if (r_read) |
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| 338 | r_spi_fsm = S_DMA_SEND; |
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| 339 | else |
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| 340 | r_spi_fsm = S_DMA_RECEIVE; |
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| 341 | } else { |
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| 342 | r_spi_fsm = S_IDLE; |
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| 343 | r_irq = r_ctrl_ie; |
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| 344 | r_spi_done = true; |
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| 345 | } |
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[558] | 346 | #ifdef SOCLIB_MODULE_DEBUG0 |
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[551] | 347 | std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 348 | #endif |
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| 349 | } else { |
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[553] | 350 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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[551] | 351 | } |
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| 352 | } |
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| 353 | } |
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| 354 | r_spi_clk_previous = s_clk_sample; |
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[558] | 355 | // generate the SPI clock |
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[565] | 356 | if (r_spi_clk_counter.read() == 0) { |
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| 357 | r_spi_clk_counter = r_divider.read(); |
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[551] | 358 | r_spi_clk = !r_spi_clk.read(); |
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| 359 | r_spi_clk_ignore = false; |
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| 360 | } else { |
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[565] | 361 | r_spi_clk_counter = r_spi_clk_counter.read() - 1; |
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[551] | 362 | } |
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| 363 | break; |
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| 364 | } |
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| 365 | } |
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| 366 | ////////////////////////////////////////////////////////////////////////////// |
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[579] | 367 | // The initiator FSM executes a loop, transfering one burst per iteration. |
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| 368 | // data comes from or goes to fifos, the other end of the fifos is |
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| 369 | // feed by or eaten by the SPI fsm. |
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[551] | 370 | ////////////////////////////////////////////////////////////////////////////// |
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| 371 | |
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| 372 | switch( r_initiator_fsm.read() ) { |
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| 373 | //////////// |
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| 374 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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| 375 | { |
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[579] | 376 | if ( r_dma_count != 0 ) |
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[558] | 377 | { |
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[579] | 378 | // start transfer |
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| 379 | if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; |
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| 380 | else r_initiator_fsm = M_WRITE_WAIT; |
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[558] | 381 | } |
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| 382 | break; |
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[551] | 383 | } |
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[579] | 384 | case M_READ_WAIT: // wait for the FIFO to be full |
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| 385 | if (!r_dma_fifo_read.wok()) { |
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| 386 | r_burst_word = m_words_per_burst - 1; |
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| 387 | r_initiator_fsm = M_READ_CMD; |
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[558] | 388 | } |
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| 389 | break; |
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[551] | 390 | //////////////// |
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| 391 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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| 392 | { |
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[558] | 393 | if ( p_vci_initiator.cmdack.read() ) |
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| 394 | { |
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[579] | 395 | if ( r_burst_word == 0 ) // last flit |
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[558] | 396 | { |
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[579] | 397 | r_initiator_fsm = M_READ_RSP; |
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[558] | 398 | } |
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[579] | 399 | else // not the last flit |
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[558] | 400 | { |
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[579] | 401 | r_burst_word = r_burst_word.read() - 1; |
---|
[558] | 402 | } |
---|
[579] | 403 | |
---|
| 404 | r_dma_fifo_read.simple_get(); // consume one fifo word |
---|
| 405 | // compute next word address |
---|
| 406 | r_buf_address = r_buf_address.read() + vci_param::B; |
---|
[558] | 407 | } |
---|
| 408 | break; |
---|
[551] | 409 | } |
---|
| 410 | //////////////// |
---|
| 411 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
---|
| 412 | { |
---|
[558] | 413 | if ( p_vci_initiator.rspval.read() ) |
---|
| 414 | { |
---|
| 415 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
| 416 | { |
---|
[579] | 417 | r_burst_word = 0; |
---|
| 418 | r_dma_count = 0; |
---|
| 419 | r_dma_error = true; |
---|
[595] | 420 | r_initiator_fsm = M_INTR; |
---|
[551] | 421 | #ifdef SOCLIB_MODULE_DEBUG |
---|
| 422 | std::cout << "vci_bd M_READ_ERROR" << std::endl; |
---|
| 423 | #endif |
---|
[558] | 424 | } |
---|
[579] | 425 | else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst |
---|
[558] | 426 | { |
---|
[579] | 427 | r_dma_count = 0; |
---|
[595] | 428 | r_initiator_fsm = M_INTR; |
---|
[579] | 429 | r_dma_error = false; |
---|
[551] | 430 | #ifdef SOCLIB_MODULE_DEBUG |
---|
[579] | 431 | std::cout << "vci_bd M_READ_SUCCESS" << std::endl; |
---|
[551] | 432 | #endif |
---|
[558] | 433 | } |
---|
[579] | 434 | else // keep on reading |
---|
[558] | 435 | { |
---|
[579] | 436 | r_dma_count = r_dma_count - 1; |
---|
| 437 | r_initiator_fsm = M_READ_WAIT; |
---|
[558] | 438 | } |
---|
| 439 | } |
---|
| 440 | break; |
---|
[551] | 441 | } |
---|
| 442 | /////////////////// |
---|
[595] | 443 | case M_INTR: |
---|
[594] | 444 | r_initiator_fsm = M_IDLE; |
---|
[595] | 445 | r_irq = true; |
---|
[594] | 446 | break; |
---|
| 447 | /////////////////// |
---|
[579] | 448 | case M_WRITE_WAIT: // wait for the FIFO to be empty |
---|
| 449 | if (!r_dma_fifo_write.rok()) { |
---|
| 450 | r_burst_word = m_words_per_burst - 1; |
---|
| 451 | r_dma_count = r_dma_count - 1; |
---|
| 452 | r_initiator_fsm = M_WRITE_CMD; |
---|
[558] | 453 | } |
---|
| 454 | break; |
---|
[551] | 455 | ///////////////// |
---|
| 456 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
---|
| 457 | { |
---|
[579] | 458 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
[558] | 459 | break; |
---|
[551] | 460 | } |
---|
| 461 | ///////////////// |
---|
| 462 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
---|
| 463 | { |
---|
[558] | 464 | if ( p_vci_initiator.rspval.read() ) |
---|
| 465 | { |
---|
[579] | 466 | typename vci_param::data_t v = p_vci_initiator.rdata.read(); |
---|
| 467 | typename vci_param::data_t f = 0; |
---|
| 468 | // byte-swap |
---|
| 469 | for (int i = 0; i < (vci_param::B * 8); i += 8) { |
---|
| 470 | f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
[558] | 471 | } |
---|
[579] | 472 | r_dma_fifo_write.simple_put(f); |
---|
| 473 | r_burst_word = r_burst_word.read() - 1; |
---|
[558] | 474 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
| 475 | { |
---|
[579] | 476 | r_buf_address = r_buf_address.read() + m_burst_size; |
---|
[551] | 477 | |
---|
[579] | 478 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
[558] | 479 | { |
---|
[579] | 480 | r_dma_count = 0; |
---|
| 481 | r_dma_error = 1; |
---|
| 482 | r_initiator_fsm = M_WRITE_END; |
---|
[551] | 483 | #ifdef SOCLIB_MODULE_DEBUG |
---|
| 484 | std::cout << "vci_bd M_WRITE_ERROR" << std::endl; |
---|
| 485 | #endif |
---|
[558] | 486 | } |
---|
[579] | 487 | else if ( r_dma_count.read() == 0) // last burst |
---|
[558] | 488 | { |
---|
[579] | 489 | r_dma_error = 0; |
---|
| 490 | r_initiator_fsm = M_WRITE_END; |
---|
[558] | 491 | } |
---|
| 492 | else // not the last burst |
---|
| 493 | { |
---|
[579] | 494 | r_initiator_fsm = M_WRITE_WAIT; |
---|
[558] | 495 | } |
---|
| 496 | } |
---|
| 497 | } |
---|
| 498 | break; |
---|
[551] | 499 | } |
---|
[579] | 500 | ///////////////// |
---|
| 501 | case M_WRITE_END: // wait for the write to be complete |
---|
[551] | 502 | { |
---|
[579] | 503 | if (r_spi_fsm == S_IDLE) { // write complete |
---|
[595] | 504 | r_initiator_fsm = M_INTR; |
---|
[558] | 505 | } |
---|
| 506 | break; |
---|
[551] | 507 | } |
---|
[579] | 508 | } // end switch r_initiator_fsm |
---|
[551] | 509 | } // end transition |
---|
| 510 | |
---|
| 511 | ////////////////////// |
---|
| 512 | tmpl(void)::genMoore() |
---|
| 513 | { |
---|
| 514 | // p_vci_target port |
---|
| 515 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
| 516 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
| 517 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
| 518 | p_vci_target.reop = true; |
---|
| 519 | |
---|
| 520 | switch(r_target_fsm) { |
---|
| 521 | case T_IDLE: |
---|
[558] | 522 | p_vci_target.cmdack = true; |
---|
| 523 | p_vci_target.rspval = false; |
---|
| 524 | p_vci_target.rdata = 0; |
---|
| 525 | break; |
---|
| 526 | case T_RSP_READ: |
---|
| 527 | p_vci_target.cmdack = false; |
---|
| 528 | p_vci_target.rspval = true; |
---|
| 529 | p_vci_target.rdata = r_rdata; |
---|
| 530 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 531 | break; |
---|
| 532 | case T_RSP_WRITE: |
---|
| 533 | p_vci_target.cmdack = false; |
---|
| 534 | p_vci_target.rspval = true; |
---|
| 535 | p_vci_target.rdata = 0; |
---|
| 536 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 537 | break; |
---|
| 538 | case T_ERROR_READ: |
---|
| 539 | p_vci_target.cmdack = false; |
---|
| 540 | p_vci_target.rspval = true; |
---|
| 541 | p_vci_target.rdata = 0; |
---|
| 542 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 543 | break; |
---|
| 544 | case T_ERROR_WRITE: |
---|
| 545 | p_vci_target.cmdack = false; |
---|
| 546 | p_vci_target.rspval = true; |
---|
| 547 | p_vci_target.rdata = 0; |
---|
| 548 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 549 | break; |
---|
[551] | 550 | } // end switch target fsm |
---|
| 551 | |
---|
| 552 | // p_vci_initiator port |
---|
| 553 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
| 554 | p_vci_initiator.trdid = 0; |
---|
| 555 | p_vci_initiator.contig = true; |
---|
| 556 | p_vci_initiator.cons = false; |
---|
| 557 | p_vci_initiator.wrap = false; |
---|
| 558 | p_vci_initiator.cfixed = false; |
---|
| 559 | p_vci_initiator.clen = 0; |
---|
| 560 | |
---|
| 561 | switch (r_initiator_fsm) { |
---|
| 562 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
[558] | 563 | p_vci_initiator.rspack = false; |
---|
| 564 | p_vci_initiator.cmdval = true; |
---|
| 565 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
| 566 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
| 567 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
| 568 | p_vci_initiator.wdata = 0; |
---|
| 569 | p_vci_initiator.be = 0; |
---|
[579] | 570 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
[558] | 571 | p_vci_initiator.eop = true; |
---|
| 572 | break; |
---|
[551] | 573 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
[579] | 574 | { |
---|
| 575 | typename vci_param::data_t v = 0; |
---|
| 576 | typename vci_param::data_t f; |
---|
[558] | 577 | p_vci_initiator.rspack = false; |
---|
| 578 | p_vci_initiator.cmdval = true; |
---|
[579] | 579 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
[558] | 580 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
| 581 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
[579] | 582 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
| 583 | f = r_dma_fifo_read.read(); |
---|
| 584 | // byte-swap |
---|
| 585 | for (int i = 0; i < (vci_param::B * 8); i += 8) { |
---|
| 586 | v |= ((f >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
| 587 | } |
---|
| 588 | p_vci_initiator.wdata = v; |
---|
| 589 | p_vci_initiator.eop = ( r_burst_word.read() == 0); |
---|
| 590 | if (vci_param::B == 8) |
---|
[558] | 591 | { |
---|
| 592 | p_vci_initiator.be = 0xFF; |
---|
| 593 | } |
---|
| 594 | else |
---|
| 595 | { |
---|
| 596 | p_vci_initiator.be = 0xF; |
---|
| 597 | } |
---|
| 598 | break; |
---|
[579] | 599 | } |
---|
[551] | 600 | case M_READ_RSP: |
---|
| 601 | case M_WRITE_RSP: |
---|
[558] | 602 | p_vci_initiator.rspack = true; |
---|
| 603 | p_vci_initiator.cmdval = false; |
---|
| 604 | break; |
---|
[551] | 605 | default: |
---|
[558] | 606 | p_vci_initiator.rspack = false; |
---|
| 607 | p_vci_initiator.cmdval = false; |
---|
| 608 | break; |
---|
[551] | 609 | } |
---|
| 610 | |
---|
| 611 | // SPI signals |
---|
| 612 | p_spi_ss = ((r_ss & 0x1) == 0); |
---|
| 613 | switch(r_spi_fsm) { |
---|
[579] | 614 | default: |
---|
[576] | 615 | p_spi_mosi = r_spi_out; |
---|
[551] | 616 | p_spi_clk = 0; |
---|
| 617 | break; |
---|
| 618 | case S_XMIT: |
---|
[575] | 619 | { |
---|
| 620 | bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
---|
[551] | 621 | p_spi_clk = r_spi_clk ^ r_ctrl_cpol; |
---|
[575] | 622 | if (s_clk_sample == 0) { |
---|
| 623 | // clock low: get data directly from shift register |
---|
| 624 | // as r_spi_out may be delayed by one clock cycle |
---|
| 625 | p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
---|
| 626 | } else { |
---|
| 627 | // clock high: get data from saved value, as the shift register |
---|
| 628 | // may have changed |
---|
| 629 | p_spi_mosi = r_spi_out; |
---|
| 630 | } |
---|
[551] | 631 | break; |
---|
[575] | 632 | } |
---|
[551] | 633 | } |
---|
| 634 | |
---|
| 635 | // IRQ signal |
---|
| 636 | p_irq = r_irq; |
---|
| 637 | } // end GenMoore() |
---|
| 638 | |
---|
| 639 | ////////////////////////////////////////////////////////////////////////////// |
---|
[558] | 640 | tmpl(/**/)::VciSpi( sc_core::sc_module_name name, |
---|
| 641 | const soclib::common::MappingTable &mt, |
---|
| 642 | const soclib::common::IntTab &srcid, |
---|
| 643 | const soclib::common::IntTab &tgtid, |
---|
| 644 | const uint32_t burst_size) |
---|
[551] | 645 | |
---|
| 646 | : caba::BaseModule(name), |
---|
| 647 | m_seglist(mt.getSegmentList(tgtid)), |
---|
| 648 | m_srcid(mt.indexForId(srcid)), |
---|
[579] | 649 | m_burst_size(burst_size), |
---|
| 650 | m_words_per_burst(burst_size / vci_param::B), |
---|
| 651 | m_byte2burst_shift(soclib::common::uint32_log2(burst_size)), |
---|
[551] | 652 | p_clk("p_clk"), |
---|
| 653 | p_resetn("p_resetn"), |
---|
| 654 | p_vci_initiator("p_vci_initiator"), |
---|
| 655 | p_vci_target("p_vci_target"), |
---|
| 656 | p_irq("p_irq"), |
---|
| 657 | p_spi_ss("p_spi_ss"), |
---|
| 658 | p_spi_clk("p_spi_clk"), |
---|
| 659 | p_spi_mosi("p_spi_mosi"), |
---|
[579] | 660 | p_spi_miso("p_spi_miso"), |
---|
| 661 | |
---|
| 662 | r_dma_fifo_read("r_dma_fifo_read", burst_size / vci_param::B), // one cache line |
---|
| 663 | r_dma_fifo_write("r_dma_fifo_read", burst_size / vci_param::B) // one cache line |
---|
[551] | 664 | { |
---|
| 665 | std::cout << " - Building VciSpi " << name << std::endl; |
---|
| 666 | |
---|
| 667 | SC_METHOD(transition); |
---|
| 668 | dont_initialize(); |
---|
| 669 | sensitive << p_clk.pos(); |
---|
| 670 | |
---|
| 671 | SC_METHOD(genMoore); |
---|
| 672 | dont_initialize(); |
---|
| 673 | sensitive << p_clk.neg(); |
---|
| 674 | |
---|
| 675 | size_t nbsegs = 0; |
---|
| 676 | std::list<soclib::common::Segment>::iterator seg; |
---|
| 677 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
| 678 | { |
---|
[558] | 679 | nbsegs++; |
---|
| 680 | |
---|
[551] | 681 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
| 682 | { |
---|
| 683 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 684 | << "The base address of segment " << seg->name() |
---|
| 685 | << " must be multiple of 64 bytes" << std::endl; |
---|
[551] | 686 | exit(1); |
---|
| 687 | } |
---|
| 688 | if ( seg->size() < 64 ) |
---|
| 689 | { |
---|
| 690 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 691 | << "The size of segment " << seg->name() |
---|
| 692 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
[551] | 693 | exit(1); |
---|
| 694 | } |
---|
[558] | 695 | std::cout << " => segment " << seg->name() |
---|
| 696 | << " / base = " << std::hex << seg->baseAddress() |
---|
| 697 | << " / size = " << seg->size() << std::endl; |
---|
[551] | 698 | } |
---|
| 699 | |
---|
| 700 | if( nbsegs == 0 ) |
---|
| 701 | { |
---|
| 702 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 703 | << " No segment allocated" << std::endl; |
---|
[551] | 704 | exit(1); |
---|
| 705 | } |
---|
| 706 | |
---|
| 707 | if( (burst_size != 8 ) && |
---|
| 708 | (burst_size != 16) && |
---|
| 709 | (burst_size != 32) && |
---|
| 710 | (burst_size != 64) ) |
---|
| 711 | { |
---|
| 712 | std::cout << "Error in component VciSpi : " << name |
---|
[558] | 713 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
[551] | 714 | exit(1); |
---|
| 715 | } |
---|
| 716 | |
---|
| 717 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
| 718 | { |
---|
[558] | 719 | std::cout << "Error in component VciSpi : " << name |
---|
| 720 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
[551] | 721 | exit(1); |
---|
| 722 | } |
---|
| 723 | |
---|
| 724 | } // end constructor |
---|
| 725 | |
---|
| 726 | tmpl(/**/)::~VciSpi() |
---|
| 727 | { |
---|
| 728 | } |
---|
| 729 | |
---|
| 730 | |
---|
| 731 | ////////////////////////// |
---|
| 732 | tmpl(void)::print_trace() |
---|
| 733 | { |
---|
| 734 | const char* initiator_str[] = |
---|
| 735 | { |
---|
| 736 | "M_IDLE", |
---|
| 737 | |
---|
[579] | 738 | "M_READ_WAIT", |
---|
[551] | 739 | "M_READ_CMD", |
---|
| 740 | "M_READ_RSP", |
---|
[595] | 741 | "M_INTR", |
---|
[551] | 742 | |
---|
[579] | 743 | "M_WRITE_WAIT", |
---|
[551] | 744 | "M_WRITE_CMD", |
---|
| 745 | "M_WRITE_RSP", |
---|
[579] | 746 | "M_WRITE_END", |
---|
[551] | 747 | }; |
---|
| 748 | const char* target_str[] = |
---|
[558] | 749 | { |
---|
[551] | 750 | "T_IDLE", |
---|
[558] | 751 | "T_RSP_READ", |
---|
| 752 | "T_RSP_WRITE", |
---|
| 753 | "T_ERROR_READ", |
---|
| 754 | "T_ERROR_WRITE", |
---|
[551] | 755 | }; |
---|
| 756 | const char* spi_str[] = |
---|
[558] | 757 | { |
---|
[551] | 758 | "S_IDLE", |
---|
[579] | 759 | "S_DMA_RECEIVE", |
---|
| 760 | "S_DMA_SEND_START", |
---|
| 761 | "S_DMA_SEND", |
---|
| 762 | "S_DMA_SEND_END", |
---|
[551] | 763 | "S_XMIT", |
---|
| 764 | }; |
---|
| 765 | |
---|
| 766 | std::cout << name() << " _TGT : " << target_str[r_target_fsm.read()] |
---|
| 767 | << std::endl; |
---|
| 768 | std::cout << name() << " _SPI : " << spi_str[r_spi_fsm.read()] |
---|
[565] | 769 | << " clk_counter " << r_spi_clk_counter.read() |
---|
| 770 | << " r_spi_bit_count " << r_spi_bit_count.read() |
---|
[579] | 771 | << " r_spi_bsy " << (int)r_spi_bsy.read() << std::endl; |
---|
[551] | 772 | std::cout << name() << " _SPI : " |
---|
| 773 | << " r_spi_clk " << r_spi_clk.read() |
---|
| 774 | << " cpol " << r_ctrl_cpol.read() |
---|
| 775 | << " cpha " << r_ctrl_cpha.read() |
---|
| 776 | << " r_spi_clk_ignore " << r_spi_clk_ignore.read() |
---|
| 777 | << " r_txrx 0x" << std::hex |
---|
| 778 | << r_txrx[1].read() << " " << r_txrx[0].read() |
---|
[579] | 779 | |
---|
[551] | 780 | << std::endl; |
---|
| 781 | std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] |
---|
[558] | 782 | << " buf = " << std::hex << r_buf_address.read() |
---|
[579] | 783 | << " burst = " << r_burst_word.read() |
---|
| 784 | << " count = " << r_dma_count.read() |
---|
| 785 | << " spi_count = " << r_spi_word_count.read() |
---|
| 786 | <<std::endl; |
---|
[551] | 787 | } |
---|
| 788 | |
---|
| 789 | }} // end namespace |
---|
| 790 | |
---|
| 791 | // Local Variables: |
---|
| 792 | // tab-width: 4 |
---|
| 793 | // c-basic-offset: 4 |
---|
| 794 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 795 | // indent-tabs-mode: nil |
---|
| 796 | // End: |
---|
| 797 | |
---|
| 798 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 799 | |
---|