[551] | 1 | /* -*- c++ -*- |
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| 2 | * |
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| 3 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 4 | * |
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| 5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 6 | * |
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| 7 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU Lesser General Public License as published |
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| 9 | * by the Free Software Foundation; version 2.1 of the License. |
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| 10 | * |
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| 11 | * SoCLib is distributed in the hope that it will be useful, but |
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| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | * Lesser General Public License for more details. |
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| 15 | * |
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| 16 | * You should have received a copy of the GNU Lesser General Public |
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| 17 | * License along with SoCLib; if not, write to the Free Software |
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| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 19 | * 02110-1301 USA |
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| 20 | * |
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| 21 | * SOCLIB_LGPL_HEADER_END |
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| 22 | * |
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| 23 | * Copyright (c) UPMC, Lip6, SoC |
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| 24 | * manuel.bouyer@lip6.fr october 2013 |
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| 25 | * |
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| 26 | * Maintainers: bouyer |
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| 27 | */ |
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| 28 | |
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| 29 | #include <stdint.h> |
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| 30 | #include <iostream> |
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| 31 | #include <fcntl.h> |
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| 32 | #include "vci_spi.h" |
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| 33 | #include "vcispi.h" |
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| 34 | |
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| 35 | namespace soclib { namespace caba { |
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| 36 | |
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| 37 | #define tmpl(t) template<typename vci_param> t VciSpi<vci_param> |
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| 38 | |
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| 39 | using namespace soclib::caba; |
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| 40 | using namespace soclib::common; |
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| 41 | |
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| 42 | //////////////////////// |
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| 43 | tmpl(void)::transition() |
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| 44 | { |
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| 45 | if(p_resetn.read() == false) |
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| 46 | { |
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| 47 | r_initiator_fsm = M_IDLE; |
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| 48 | r_target_fsm = T_IDLE; |
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| 49 | r_spi_fsm = S_IDLE; |
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| 50 | r_ss = 0; |
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| 51 | r_divider = 0xffff; |
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| 52 | r_ctrl_char_len = 0; |
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| 53 | r_ctrl_ass = false; |
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| 54 | r_ctrl_ie = false; |
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| 55 | r_ctrl_cpol = false; |
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| 56 | r_ctrl_cpha = false; |
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| 57 | r_ctrl_go_bsy = false; |
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| 58 | r_clk_counter = 0xffff; |
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| 59 | r_spi_clk = 0; |
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| 60 | |
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| 61 | r_irq = false; |
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| 62 | r_read = false; |
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| 63 | |
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| 64 | return; |
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| 65 | } |
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| 66 | |
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| 67 | ////////////////////////////////////////////////////////////////////////////// |
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| 68 | // The Target FSM controls the following registers: |
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| 69 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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| 70 | ////////////////////////////////////////////////////////////////////////////// |
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| 71 | |
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| 72 | switch(r_target_fsm) { |
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| 73 | //////////// |
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| 74 | case T_IDLE: |
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| 75 | { |
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| 76 | if ( p_vci_target.cmdval.read() ) |
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| 77 | { |
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| 78 | r_srcid = p_vci_target.srcid.read(); |
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| 79 | r_trdid = p_vci_target.trdid.read(); |
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| 80 | r_pktid = p_vci_target.pktid.read(); |
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| 81 | r_tdata = p_vci_target.wdata.read(); |
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| 82 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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| 83 | |
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| 84 | bool found = false; |
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| 85 | std::list<soclib::common::Segment>::iterator seg; |
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| 86 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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| 87 | { |
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| 88 | if ( seg->contains(address) ) found = true; |
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| 89 | } |
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| 90 | |
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| 91 | bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); |
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| 92 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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| 93 | |
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| 94 | if (read) { |
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| 95 | if (not found) { |
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| 96 | r_target_fsm = T_READ_ERROR; |
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| 97 | } else { |
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| 98 | switch(cell) { |
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| 99 | case SPI_DATA_TXRX0: |
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| 100 | case SPI_DATA_TXRX1: |
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| 101 | case SPI_DATA_TXRX2: |
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| 102 | case SPI_DATA_TXRX3: |
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| 103 | r_target_fsm = T_READ_TXRX; |
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| 104 | r_txrx_addr = cell; |
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| 105 | break; |
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| 106 | case SPI_CTRL: |
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| 107 | r_target_fsm = T_READ_CTRL; |
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| 108 | break; |
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| 109 | case SPI_DIVIDER: |
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| 110 | r_target_fsm = T_READ_DIVIDER; |
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| 111 | break; |
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| 112 | case SPI_SS: |
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| 113 | r_target_fsm = T_READ_SS; |
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| 114 | break; |
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| 115 | default: |
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| 116 | r_target_fsm = T_READ_ERROR; |
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| 117 | break; |
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| 118 | } |
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| 119 | } |
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| 120 | } else { // write |
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| 121 | if (not found) { |
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| 122 | r_target_fsm = T_WRITE_ERROR; |
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| 123 | } else { |
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| 124 | switch(cell) { |
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| 125 | case SPI_DATA_TXRX0: |
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| 126 | case SPI_DATA_TXRX1: |
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| 127 | case SPI_DATA_TXRX2: |
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| 128 | case SPI_DATA_TXRX3: |
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| 129 | r_target_fsm = T_WRITE_TXRX; |
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| 130 | r_txrx_addr = cell; |
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| 131 | break; |
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| 132 | case SPI_CTRL: |
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| 133 | r_target_fsm = T_WRITE_CTRL; |
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| 134 | break; |
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| 135 | case SPI_DIVIDER: |
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| 136 | r_target_fsm = T_WRITE_DIVIDER; |
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| 137 | break; |
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| 138 | case SPI_SS: |
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| 139 | r_target_fsm = T_WRITE_SS; |
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| 140 | break; |
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| 141 | default: |
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| 142 | r_target_fsm = T_WRITE_ERROR; |
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| 143 | break; |
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| 144 | } |
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| 145 | } |
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| 146 | } |
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| 147 | |
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| 148 | } |
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| 149 | break; |
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| 150 | } |
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| 151 | //////////////////// |
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| 152 | case T_WRITE_TXRX: |
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| 153 | { |
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| 154 | if (p_vci_target.rspack.read() ) { |
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| 155 | if (r_ctrl_go_bsy.read() == false) |
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| 156 | { |
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| 157 | switch(r_txrx_addr.read()) { |
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| 158 | case 0: |
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[553] | 159 | r_txrx[0] = (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | |
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| 160 | ((uint64_t)r_tdata.read() & (uint64_t)0x00000000ffffffffULL); |
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[551] | 161 | break; |
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| 162 | case 1: |
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[553] | 163 | r_txrx[0] = (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | |
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[551] | 164 | ((uint64_t)r_tdata.read() << 32); |
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| 165 | break; |
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| 166 | case 2: |
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[553] | 167 | r_txrx[1] = (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | |
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| 168 | ((uint64_t)r_tdata.read() & (uint64_t)0x00000000ffffffffULL); |
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[551] | 169 | break; |
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| 170 | case 3: |
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[553] | 171 | r_txrx[1] = (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | |
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[551] | 172 | ((uint64_t)r_tdata.read() << 32); |
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| 173 | break; |
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| 174 | } |
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| 175 | r_target_fsm = T_IDLE; |
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| 176 | } |
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| 177 | break; |
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| 178 | } |
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| 179 | //////////////////////// |
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| 180 | case T_WRITE_CTRL: |
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| 181 | { |
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| 182 | if (p_vci_target.rspack.read() ) { |
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| 183 | if (r_ctrl_go_bsy.read() == false) |
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| 184 | { |
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| 185 | r_ctrl_cpol = ((r_tdata.read() & SPI_CTRL_CPOL) != 0); |
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| 186 | r_ctrl_cpha = ((r_tdata.read() & SPI_CTRL_CPHA) != 0); |
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| 187 | r_ctrl_ass = ((r_tdata.read() & SPI_CTRL_ASS_EN) != 0); |
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| 188 | r_ctrl_ie = ((r_tdata.read() & SPI_CTRL_IE_EN) != 0); |
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| 189 | r_ctrl_go_bsy = ((r_tdata.read() & SPI_CTRL_GO_BSY) != 0); |
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| 190 | r_ctrl_char_len = (r_tdata.read() & SPI_CTRL_CHAR_LEN_MASK); |
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| 191 | #ifdef SOCLIB_MODULE_DEBUG |
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| 192 | if ((r_tdata.read() & SPI_CTRL_GO_BSY) != 0) { |
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| 193 | std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 194 | } |
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| 195 | #endif |
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| 196 | } |
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| 197 | r_target_fsm = T_IDLE; |
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| 198 | } |
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| 199 | break; |
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| 200 | } |
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| 201 | /////////////////// |
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| 202 | case T_WRITE_DIVIDER: |
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| 203 | { |
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| 204 | if (p_vci_target.rspack.read() ) { |
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| 205 | if (r_ctrl_go_bsy.read() == false) |
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| 206 | { |
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| 207 | r_divider = (uint32_t)r_tdata.read(); |
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| 208 | #ifdef SOCLIB_MODULE_DEBUG |
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| 209 | std::cout << name() << " divider set to " << std::dec << (uint32_t)r_tdata.read() << std::endl; |
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| 210 | #endif |
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| 211 | } |
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| 212 | r_target_fsm = T_IDLE; |
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| 213 | } |
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| 214 | break; |
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| 215 | } |
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| 216 | ///////////////// |
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| 217 | case T_WRITE_SS: |
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| 218 | { |
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| 219 | if (p_vci_target.rspack.read() ) { |
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| 220 | if (r_ctrl_go_bsy.read() == false) |
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| 221 | r_ss = (uint32_t)r_tdata.read(); |
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| 222 | } |
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| 223 | r_target_fsm = T_IDLE; |
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| 224 | } |
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| 225 | break; |
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| 226 | } |
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| 227 | /////////////////// |
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| 228 | case T_READ_TXRX: |
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| 229 | case T_READ_DIVIDER: |
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| 230 | case T_READ_SS: |
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| 231 | case T_WRITE_ERROR: |
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| 232 | case T_READ_ERROR: |
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| 233 | { |
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| 234 | if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; |
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| 235 | break; |
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| 236 | } |
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| 237 | /////////////////// |
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| 238 | case T_READ_CTRL: |
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| 239 | { |
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| 240 | if ( p_vci_target.rspack.read() ) |
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| 241 | { |
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| 242 | r_target_fsm = T_IDLE; |
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| 243 | r_irq = r_irq & r_ctrl_go_bsy; |
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| 244 | } |
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| 245 | break; |
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| 246 | } |
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| 247 | } // end switch target fsm |
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| 248 | |
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| 249 | |
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| 250 | |
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| 251 | |
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| 252 | ////////////////////////////////////////////////////////////////////////////// |
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| 253 | // the SPI FSM controls SPI signals |
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| 254 | ////////////////////////////////////////////////////////////////////////////// |
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| 255 | switch (r_spi_fsm) { |
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| 256 | case S_IDLE: |
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| 257 | r_clk_counter = r_divider.read(); |
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| 258 | r_spi_clk = 0; |
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| 259 | r_spi_clk_previous = r_ctrl_cpha; |
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| 260 | r_spi_clk_ignore = r_ctrl_cpha; |
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| 261 | r_bit_count = r_ctrl_char_len; |
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[553] | 262 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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[551] | 263 | if (r_ctrl_go_bsy.read()) |
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| 264 | r_spi_fsm = S_XMIT; |
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| 265 | break; |
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| 266 | case S_XMIT: |
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| 267 | { |
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| 268 | bool s_clk_sample; |
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| 269 | // on clock transition, sample input line, and shift data |
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| 270 | s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
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| 271 | if (!r_spi_clk_ignore) { |
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| 272 | if (r_spi_clk_previous == 0 && s_clk_sample == 1) { |
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| 273 | // low to high transition: shift and sample |
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| 274 | r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); |
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| 275 | r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; |
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| 276 | r_bit_count = r_bit_count - 1; |
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| 277 | } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { |
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| 278 | // high to low transition: change output, or stop |
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| 279 | if (r_bit_count == 0) { |
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| 280 | r_spi_fsm = S_IDLE; |
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| 281 | r_irq = r_ctrl_ie; |
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| 282 | r_ctrl_go_bsy = false; |
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| 283 | #ifdef SOCLIB_MODULE_DEBUG |
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| 284 | std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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| 285 | #endif |
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| 286 | } else { |
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[553] | 287 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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[551] | 288 | } |
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| 289 | } |
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| 290 | } |
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| 291 | r_spi_clk_previous = s_clk_sample; |
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| 292 | // generate the SPI clock |
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| 293 | if (r_clk_counter.read() == 0) { |
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| 294 | r_clk_counter = r_divider.read(); |
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| 295 | r_spi_clk = !r_spi_clk.read(); |
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| 296 | r_spi_clk_ignore = false; |
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| 297 | } else { |
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| 298 | r_clk_counter = r_clk_counter.read() - 1; |
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| 299 | } |
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| 300 | break; |
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| 301 | } |
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| 302 | } |
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| 303 | ////////////////////////////////////////////////////////////////////////////// |
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| 304 | // The initiator FSM executes a loop, transfering one block per iteration. |
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| 305 | // Each block is split in bursts, and the number of bursts depends |
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| 306 | // on the memory buffer alignment on a burst boundary: |
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| 307 | // - If buffer aligned, all burst have the same length (m_words_per burst) |
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| 308 | // and the number of bursts is (m_bursts_per_block). |
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| 309 | // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) |
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| 310 | // and first and last burst are shorter, because all words in a burst |
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| 311 | // must be contained in a single cache line. |
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| 312 | // first burst => nwords = m_words_per_burst - offset |
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| 313 | // last burst => nwords = offset |
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| 314 | // other burst => nwords = m_words_per_burst |
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| 315 | ////////////////////////////////////////////////////////////////////////////// |
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| 316 | |
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| 317 | switch( r_initiator_fsm.read() ) { |
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| 318 | //////////// |
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| 319 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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| 320 | { |
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| 321 | if ( false ) // XXX |
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| 322 | { |
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| 323 | r_index = 0; |
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| 324 | r_block_count = 0; |
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| 325 | r_burst_count = 0; |
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| 326 | r_words_count = 0; |
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| 327 | |
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| 328 | // compute r_burst_offset (zero when buffer aligned) |
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| 329 | r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); |
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| 330 | |
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| 331 | // start tranfer |
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| 332 | if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; |
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| 333 | else r_initiator_fsm = M_WRITE_BURST; |
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| 334 | } |
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| 335 | break; |
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| 336 | } |
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| 337 | ////////////////// |
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| 338 | case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles |
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| 339 | { |
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| 340 | r_burst_count = 0; |
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| 341 | r_words_count = 0; |
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| 342 | r_initiator_fsm = M_READ_BURST; |
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| 343 | break; |
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| 344 | } |
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| 345 | ////////////////// |
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| 346 | case M_READ_BURST: // Compute the number of words and the number of flits in the burst |
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| 347 | // The number of flits can be smaller than the number of words |
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| 348 | // in case of 8 bytes flits... |
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| 349 | { |
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| 350 | uint32_t nwords; |
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| 351 | uint32_t offset = r_burst_offset.read(); |
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| 352 | |
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| 353 | if ( offset ) // buffer not aligned |
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| 354 | { |
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| 355 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
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| 356 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
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| 357 | else nwords = m_words_per_burst; |
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| 358 | } |
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| 359 | else // buffer aligned |
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| 360 | { |
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| 361 | nwords = m_words_per_burst; |
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| 362 | } |
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| 363 | |
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| 364 | r_burst_nwords = nwords; |
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| 365 | r_initiator_fsm = M_READ_CMD; |
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| 366 | break; |
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| 367 | } |
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| 368 | //////////////// |
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| 369 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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| 370 | { |
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| 371 | if ( p_vci_initiator.cmdack.read() ) |
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| 372 | { |
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| 373 | uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); |
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| 374 | |
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| 375 | if ( vci_param::B == 4 ) // one word per flit |
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| 376 | { |
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| 377 | if ( nwords <= 1 ) // last flit |
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| 378 | { |
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| 379 | r_initiator_fsm = M_READ_RSP; |
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| 380 | r_words_count = 0; |
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| 381 | } |
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| 382 | else // not the last flit |
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| 383 | { |
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| 384 | r_words_count = r_words_count.read() + 1; |
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| 385 | } |
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| 386 | |
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| 387 | // compute next word address and next local buffer index |
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| 388 | r_buf_address = r_buf_address.read() + 4; |
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| 389 | r_index = r_index.read() + 1; |
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| 390 | } |
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| 391 | else // 2 words per flit |
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| 392 | { |
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| 393 | if ( nwords <= 2 ) // last flit |
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| 394 | { |
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| 395 | r_initiator_fsm = M_READ_RSP; |
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| 396 | r_words_count = 0; |
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| 397 | } |
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| 398 | else // not the last flit |
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| 399 | { |
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| 400 | r_words_count = r_words_count.read() + 2; |
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| 401 | } |
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| 402 | |
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| 403 | // compute next word address and next local buffer index |
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| 404 | if ( nwords == 1 ) |
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| 405 | { |
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| 406 | r_buf_address = r_buf_address.read() + 4; |
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| 407 | r_index = r_index.read() + 1; |
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| 408 | } |
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| 409 | else |
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| 410 | { |
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| 411 | r_buf_address = r_buf_address.read() + 8; |
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| 412 | r_index = r_index.read() + 2; |
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| 413 | } |
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| 414 | } |
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| 415 | } |
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| 416 | break; |
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| 417 | } |
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| 418 | //////////////// |
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| 419 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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| 420 | { |
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| 421 | if ( p_vci_initiator.rspval.read() ) |
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| 422 | { |
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| 423 | bool aligned = (r_burst_offset.read() == 0); |
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| 424 | |
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| 425 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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| 426 | { |
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| 427 | r_initiator_fsm = M_READ_ERROR; |
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| 428 | #ifdef SOCLIB_MODULE_DEBUG |
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| 429 | std::cout << "vci_bd M_READ_ERROR" << std::endl; |
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| 430 | #endif |
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| 431 | } |
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| 432 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
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| 433 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) |
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| 434 | { |
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| 435 | if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block |
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| 436 | { |
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| 437 | r_initiator_fsm = M_READ_SUCCESS; |
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| 438 | #ifdef SOCLIB_MODULE_DEBUG |
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| 439 | std::cout << "vci_bd M_READ_SUCCESS" << std::endl; |
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| 440 | #endif |
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| 441 | } |
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| 442 | else // last burst not last block |
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| 443 | { |
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| 444 | r_index = 0; |
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| 445 | r_burst_count = 0; |
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| 446 | r_block_count = r_block_count.read() + 1; |
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| 447 | r_initiator_fsm = M_READ_BLOCK; |
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| 448 | } |
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| 449 | } |
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| 450 | else // not the last burst |
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| 451 | { |
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| 452 | r_burst_count = r_burst_count.read() + 1; |
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| 453 | r_initiator_fsm = M_READ_BURST; |
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| 454 | } |
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| 455 | } |
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| 456 | break; |
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| 457 | } |
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| 458 | /////////////////// |
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| 459 | case M_READ_SUCCESS: |
---|
| 460 | case M_READ_ERROR: |
---|
| 461 | { |
---|
| 462 | if( !r_go ) r_initiator_fsm = M_IDLE; |
---|
| 463 | break; |
---|
| 464 | } |
---|
| 465 | /////////////////// |
---|
| 466 | case M_WRITE_BURST: // Compute the number of words in the burst |
---|
| 467 | { |
---|
| 468 | uint32_t nwords; |
---|
| 469 | uint32_t offset = r_burst_offset.read(); |
---|
| 470 | |
---|
| 471 | if ( offset ) // buffer not aligned |
---|
| 472 | { |
---|
| 473 | if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; |
---|
| 474 | else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; |
---|
| 475 | else nwords = m_words_per_burst; |
---|
| 476 | } |
---|
| 477 | else // buffer aligned |
---|
| 478 | { |
---|
| 479 | nwords = m_words_per_burst; |
---|
| 480 | } |
---|
| 481 | |
---|
| 482 | r_burst_nwords = nwords; |
---|
| 483 | r_initiator_fsm = M_WRITE_CMD; |
---|
| 484 | break; |
---|
| 485 | } |
---|
| 486 | ///////////////// |
---|
| 487 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
---|
| 488 | { |
---|
| 489 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
| 490 | break; |
---|
| 491 | } |
---|
| 492 | ///////////////// |
---|
| 493 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
---|
| 494 | { |
---|
| 495 | if ( p_vci_initiator.rspval.read() ) |
---|
| 496 | { |
---|
| 497 | bool aligned = (r_burst_offset.read() == 0); |
---|
| 498 | |
---|
| 499 | if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) |
---|
| 500 | { |
---|
| 501 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 502 | r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); |
---|
| 503 | r_index = r_index.read() + 2; |
---|
| 504 | } |
---|
| 505 | else |
---|
| 506 | { |
---|
| 507 | r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); |
---|
| 508 | r_index = r_index.read() + 1; |
---|
| 509 | } |
---|
| 510 | |
---|
| 511 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
| 512 | { |
---|
| 513 | r_words_count = 0; |
---|
| 514 | r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); |
---|
| 515 | |
---|
| 516 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
| 517 | { |
---|
| 518 | r_initiator_fsm = M_WRITE_ERROR; |
---|
| 519 | #ifdef SOCLIB_MODULE_DEBUG |
---|
| 520 | std::cout << "vci_bd M_WRITE_ERROR" << std::endl; |
---|
| 521 | #endif |
---|
| 522 | } |
---|
| 523 | else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or |
---|
| 524 | (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst |
---|
| 525 | { |
---|
| 526 | r_initiator_fsm = M_WRITE_BLOCK; |
---|
| 527 | } |
---|
| 528 | else // not the last burst |
---|
| 529 | { |
---|
| 530 | r_burst_count = r_burst_count.read() + 1; |
---|
| 531 | r_initiator_fsm = M_WRITE_BURST; |
---|
| 532 | } |
---|
| 533 | } |
---|
| 534 | else |
---|
| 535 | { |
---|
| 536 | r_words_count = r_words_count.read() + 1; |
---|
| 537 | } |
---|
| 538 | } |
---|
| 539 | break; |
---|
| 540 | } |
---|
| 541 | /////////////////// |
---|
| 542 | case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles |
---|
| 543 | { |
---|
| 544 | if ( r_block_count.read() == r_nblocks.read() - 1 ) |
---|
| 545 | { |
---|
| 546 | r_initiator_fsm = M_WRITE_SUCCESS; |
---|
| 547 | #ifdef SOCLIB_MODULE_DEBUG |
---|
| 548 | std::cout << "vci_bd M_WRITE_SUCCESS" << std::endl; |
---|
| 549 | #endif |
---|
| 550 | } |
---|
| 551 | else |
---|
| 552 | { |
---|
| 553 | r_burst_count = 0; |
---|
| 554 | r_index = 0; |
---|
| 555 | r_block_count = r_block_count.read() + 1; |
---|
| 556 | r_initiator_fsm = M_WRITE_BURST; |
---|
| 557 | } |
---|
| 558 | break; |
---|
| 559 | } |
---|
| 560 | ///////////////////// |
---|
| 561 | case M_WRITE_SUCCESS: |
---|
| 562 | case M_WRITE_ERROR: |
---|
| 563 | { |
---|
| 564 | r_initiator_fsm = M_IDLE; |
---|
| 565 | break; |
---|
| 566 | } |
---|
| 567 | } // end switch r_initiator_fsm |
---|
| 568 | } // end transition |
---|
| 569 | |
---|
| 570 | ////////////////////// |
---|
| 571 | tmpl(void)::genMoore() |
---|
| 572 | { |
---|
| 573 | // p_vci_target port |
---|
| 574 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
| 575 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
| 576 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
| 577 | p_vci_target.reop = true; |
---|
| 578 | |
---|
| 579 | switch(r_target_fsm) { |
---|
| 580 | case T_IDLE: |
---|
| 581 | p_vci_target.cmdack = true; |
---|
| 582 | p_vci_target.rspval = false; |
---|
| 583 | p_vci_target.rdata = 0; |
---|
| 584 | break; |
---|
| 585 | case T_READ_TXRX: |
---|
| 586 | p_vci_target.cmdack = false; |
---|
| 587 | p_vci_target.rspval = true; |
---|
| 588 | switch(r_txrx_addr.read()) { |
---|
| 589 | case 0: |
---|
[553] | 590 | p_vci_target.rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; |
---|
[551] | 591 | break; |
---|
| 592 | case 1: |
---|
| 593 | p_vci_target.rdata = r_txrx[0] >> 32; |
---|
| 594 | break; |
---|
| 595 | case 2: |
---|
[553] | 596 | p_vci_target.rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; |
---|
[551] | 597 | break; |
---|
| 598 | case 3: |
---|
| 599 | p_vci_target.rdata = r_txrx[1] >> 32; |
---|
| 600 | break; |
---|
| 601 | } |
---|
| 602 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 603 | break; |
---|
| 604 | case T_READ_CTRL: |
---|
| 605 | { |
---|
| 606 | uint32_t data = 0; |
---|
| 607 | if (r_ctrl_cpol.read()) |
---|
| 608 | data |= SPI_CTRL_CPOL; |
---|
| 609 | if (r_ctrl_cpha.read()) |
---|
| 610 | data |= SPI_CTRL_CPHA; |
---|
| 611 | if (r_ctrl_ass.read()) |
---|
| 612 | data |= SPI_CTRL_ASS_EN; |
---|
| 613 | if (r_ctrl_ie.read()) |
---|
| 614 | data |= SPI_CTRL_IE_EN; |
---|
| 615 | if (r_ctrl_go_bsy.read()) |
---|
| 616 | data |= SPI_CTRL_GO_BSY; |
---|
| 617 | data |= (uint32_t)r_ctrl_char_len.read(); |
---|
| 618 | |
---|
| 619 | p_vci_target.cmdack = false; |
---|
| 620 | p_vci_target.rspval = true; |
---|
| 621 | p_vci_target.rdata = data; |
---|
| 622 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 623 | break; |
---|
| 624 | } |
---|
| 625 | case T_READ_DIVIDER: |
---|
| 626 | p_vci_target.cmdack = false; |
---|
| 627 | p_vci_target.rspval = true; |
---|
| 628 | p_vci_target.rdata = r_divider.read(); |
---|
| 629 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 630 | break; |
---|
| 631 | case T_READ_SS: |
---|
| 632 | p_vci_target.cmdack = false; |
---|
| 633 | p_vci_target.rspval = true; |
---|
| 634 | p_vci_target.rdata = r_ss.read(); |
---|
| 635 | p_vci_target.rerror = VCI_READ_OK; |
---|
| 636 | break; |
---|
| 637 | case T_READ_ERROR: |
---|
| 638 | p_vci_target.cmdack = false; |
---|
| 639 | p_vci_target.rspval = true; |
---|
| 640 | p_vci_target.rdata = 0; |
---|
| 641 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
| 642 | break; |
---|
| 643 | case T_WRITE_ERROR: |
---|
| 644 | p_vci_target.cmdack = false; |
---|
| 645 | p_vci_target.rspval = true; |
---|
| 646 | p_vci_target.rdata = 0; |
---|
| 647 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
| 648 | break; |
---|
| 649 | default: |
---|
| 650 | p_vci_target.cmdack = false; |
---|
| 651 | p_vci_target.rspval = true; |
---|
| 652 | p_vci_target.rdata = 0; |
---|
| 653 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
| 654 | break; |
---|
| 655 | } // end switch target fsm |
---|
| 656 | |
---|
| 657 | // p_vci_initiator port |
---|
| 658 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
| 659 | p_vci_initiator.trdid = 0; |
---|
| 660 | p_vci_initiator.contig = true; |
---|
| 661 | p_vci_initiator.cons = false; |
---|
| 662 | p_vci_initiator.wrap = false; |
---|
| 663 | p_vci_initiator.cfixed = false; |
---|
| 664 | p_vci_initiator.clen = 0; |
---|
| 665 | |
---|
| 666 | switch (r_initiator_fsm) { |
---|
| 667 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
| 668 | p_vci_initiator.rspack = false; |
---|
| 669 | p_vci_initiator.cmdval = true; |
---|
| 670 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
| 671 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
| 672 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
| 673 | p_vci_initiator.wdata = 0; |
---|
| 674 | p_vci_initiator.be = 0; |
---|
| 675 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
| 676 | p_vci_initiator.eop = true; |
---|
| 677 | break; |
---|
| 678 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
| 679 | p_vci_initiator.rspack = false; |
---|
| 680 | p_vci_initiator.cmdval = true; |
---|
| 681 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
| 682 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
| 683 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
| 684 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); |
---|
| 685 | if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) |
---|
| 686 | { |
---|
| 687 | p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + |
---|
| 688 | (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); |
---|
| 689 | p_vci_initiator.be = 0xFF; |
---|
| 690 | p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); |
---|
| 691 | } |
---|
| 692 | else |
---|
| 693 | { |
---|
| 694 | p_vci_initiator.wdata = r_local_buffer[r_index.read()]; |
---|
| 695 | p_vci_initiator.be = 0xF; |
---|
| 696 | p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); |
---|
| 697 | } |
---|
| 698 | break; |
---|
| 699 | case M_READ_RSP: |
---|
| 700 | case M_WRITE_RSP: |
---|
| 701 | p_vci_initiator.rspack = true; |
---|
| 702 | p_vci_initiator.cmdval = false; |
---|
| 703 | break; |
---|
| 704 | default: |
---|
| 705 | p_vci_initiator.rspack = false; |
---|
| 706 | p_vci_initiator.cmdval = false; |
---|
| 707 | break; |
---|
| 708 | } |
---|
| 709 | |
---|
| 710 | // SPI signals |
---|
| 711 | p_spi_ss = ((r_ss & 0x1) == 0); |
---|
| 712 | switch(r_spi_fsm) { |
---|
| 713 | case S_IDLE: |
---|
| 714 | p_spi_mosi = 0; |
---|
| 715 | p_spi_clk = 0; |
---|
| 716 | break; |
---|
| 717 | case S_XMIT: |
---|
| 718 | p_spi_clk = r_spi_clk ^ r_ctrl_cpol; |
---|
| 719 | p_spi_mosi = r_spi_out; |
---|
| 720 | break; |
---|
| 721 | } |
---|
| 722 | |
---|
| 723 | // IRQ signal |
---|
| 724 | p_irq = r_irq; |
---|
| 725 | } // end GenMoore() |
---|
| 726 | |
---|
| 727 | ////////////////////////////////////////////////////////////////////////////// |
---|
| 728 | tmpl(/**/)::VciSpi( sc_core::sc_module_name name, |
---|
| 729 | const soclib::common::MappingTable &mt, |
---|
| 730 | const soclib::common::IntTab &srcid, |
---|
| 731 | const soclib::common::IntTab &tgtid, |
---|
| 732 | const uint32_t burst_size) |
---|
| 733 | |
---|
| 734 | : caba::BaseModule(name), |
---|
| 735 | m_seglist(mt.getSegmentList(tgtid)), |
---|
| 736 | m_srcid(mt.indexForId(srcid)), |
---|
| 737 | m_words_per_block(512/4), |
---|
| 738 | m_words_per_burst(burst_size/4), |
---|
| 739 | m_bursts_per_block(512/burst_size), |
---|
| 740 | p_clk("p_clk"), |
---|
| 741 | p_resetn("p_resetn"), |
---|
| 742 | p_vci_initiator("p_vci_initiator"), |
---|
| 743 | p_vci_target("p_vci_target"), |
---|
| 744 | p_irq("p_irq"), |
---|
| 745 | p_spi_ss("p_spi_ss"), |
---|
| 746 | p_spi_clk("p_spi_clk"), |
---|
| 747 | p_spi_mosi("p_spi_mosi"), |
---|
| 748 | p_spi_miso("p_spi_miso") |
---|
| 749 | { |
---|
| 750 | std::cout << " - Building VciSpi " << name << std::endl; |
---|
| 751 | |
---|
| 752 | SC_METHOD(transition); |
---|
| 753 | dont_initialize(); |
---|
| 754 | sensitive << p_clk.pos(); |
---|
| 755 | |
---|
| 756 | SC_METHOD(genMoore); |
---|
| 757 | dont_initialize(); |
---|
| 758 | sensitive << p_clk.neg(); |
---|
| 759 | |
---|
| 760 | size_t nbsegs = 0; |
---|
| 761 | std::list<soclib::common::Segment>::iterator seg; |
---|
| 762 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
| 763 | { |
---|
| 764 | nbsegs++; |
---|
| 765 | |
---|
| 766 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
| 767 | { |
---|
| 768 | std::cout << "Error in component VciSpi : " << name |
---|
| 769 | << "The base address of segment " << seg->name() |
---|
| 770 | << " must be multiple of 64 bytes" << std::endl; |
---|
| 771 | exit(1); |
---|
| 772 | } |
---|
| 773 | if ( seg->size() < 64 ) |
---|
| 774 | { |
---|
| 775 | std::cout << "Error in component VciSpi : " << name |
---|
| 776 | << "The size of segment " << seg->name() |
---|
| 777 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
| 778 | exit(1); |
---|
| 779 | } |
---|
| 780 | std::cout << " => segment " << seg->name() |
---|
| 781 | << " / base = " << std::hex << seg->baseAddress() |
---|
| 782 | << " / size = " << seg->size() << std::endl; |
---|
| 783 | } |
---|
| 784 | |
---|
| 785 | if( nbsegs == 0 ) |
---|
| 786 | { |
---|
| 787 | std::cout << "Error in component VciSpi : " << name |
---|
| 788 | << " No segment allocated" << std::endl; |
---|
| 789 | exit(1); |
---|
| 790 | } |
---|
| 791 | |
---|
| 792 | if( (burst_size != 8 ) && |
---|
| 793 | (burst_size != 16) && |
---|
| 794 | (burst_size != 32) && |
---|
| 795 | (burst_size != 64) ) |
---|
| 796 | { |
---|
| 797 | std::cout << "Error in component VciSpi : " << name |
---|
| 798 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
| 799 | exit(1); |
---|
| 800 | } |
---|
| 801 | |
---|
| 802 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
| 803 | { |
---|
| 804 | std::cout << "Error in component VciSpi : " << name |
---|
| 805 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
| 806 | exit(1); |
---|
| 807 | } |
---|
| 808 | |
---|
| 809 | r_local_buffer = new uint32_t[m_words_per_block]; |
---|
| 810 | |
---|
| 811 | } // end constructor |
---|
| 812 | |
---|
| 813 | tmpl(/**/)::~VciSpi() |
---|
| 814 | { |
---|
| 815 | delete [] r_local_buffer; |
---|
| 816 | } |
---|
| 817 | |
---|
| 818 | |
---|
| 819 | ////////////////////////// |
---|
| 820 | tmpl(void)::print_trace() |
---|
| 821 | { |
---|
| 822 | const char* initiator_str[] = |
---|
| 823 | { |
---|
| 824 | "M_IDLE", |
---|
| 825 | |
---|
| 826 | "M_READ_BLOCK", |
---|
| 827 | "M_READ_BURST", |
---|
| 828 | "M_READ_CMD", |
---|
| 829 | "M_READ_RSP", |
---|
| 830 | "M_READ_SUCCESS", |
---|
| 831 | "M_READ_ERROR", |
---|
| 832 | |
---|
| 833 | "M_WRITE_BURST", |
---|
| 834 | "M_WRITE_CMD", |
---|
| 835 | "M_WRITE_RSP", |
---|
| 836 | "M_WRITE_BLOCK", |
---|
| 837 | "M_WRITE_SUCCESS", |
---|
| 838 | "M_WRITE_ERROR", |
---|
| 839 | }; |
---|
| 840 | const char* target_str[] = |
---|
| 841 | { |
---|
| 842 | "T_IDLE", |
---|
| 843 | "T_WRITE_TXRX", |
---|
| 844 | "T_READ_TXRX", |
---|
| 845 | "T_WRITE_CTRL", |
---|
| 846 | "T_READ_CTRL", |
---|
| 847 | "T_WRITE_DIVIDER", |
---|
| 848 | "T_READ_DIVIDER", |
---|
| 849 | "T_WRITE_SS", |
---|
| 850 | "T_READ_SS", |
---|
| 851 | "T_WRITE_ERROR", |
---|
| 852 | "T_READ_ERROR", |
---|
| 853 | }; |
---|
| 854 | const char* spi_str[] = |
---|
| 855 | { |
---|
| 856 | "S_IDLE", |
---|
| 857 | "S_XMIT", |
---|
| 858 | }; |
---|
| 859 | |
---|
| 860 | std::cout << name() << " _TGT : " << target_str[r_target_fsm.read()] |
---|
| 861 | << std::endl; |
---|
| 862 | std::cout << name() << " _SPI : " << spi_str[r_spi_fsm.read()] |
---|
| 863 | << " clk_counter " << r_clk_counter.read() |
---|
| 864 | << " r_bit_count " << r_bit_count.read() << std::endl; |
---|
| 865 | std::cout << name() << " _SPI : " |
---|
| 866 | << " r_spi_clk " << r_spi_clk.read() |
---|
| 867 | << " cpol " << r_ctrl_cpol.read() |
---|
| 868 | << " cpha " << r_ctrl_cpha.read() |
---|
| 869 | << " r_spi_clk_ignore " << r_spi_clk_ignore.read() |
---|
| 870 | << " r_txrx 0x" << std::hex |
---|
| 871 | << r_txrx[1].read() << " " << r_txrx[0].read() |
---|
| 872 | << std::endl; |
---|
| 873 | std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] |
---|
| 874 | << " buf = " << std::hex << r_buf_address.read() |
---|
| 875 | << " block = " << std::dec << r_block_count.read() |
---|
| 876 | << " burst = " << r_burst_count.read() |
---|
| 877 | << " word = " << r_words_count.read() <<std::endl; |
---|
| 878 | } |
---|
| 879 | |
---|
| 880 | }} // end namespace |
---|
| 881 | |
---|
| 882 | // Local Variables: |
---|
| 883 | // tab-width: 4 |
---|
| 884 | // c-basic-offset: 4 |
---|
| 885 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 886 | // indent-tabs-mode: nil |
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| 887 | // End: |
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| 888 | |
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| 889 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 890 | |
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