1 | /* -*- c++ -*- |
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2 | * |
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3 | * SOCLIB_LGPL_HEADER_BEGIN |
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4 | * |
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5 | * This file is part of SoCLib, GNU LGPLv2.1. |
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6 | * |
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7 | * SoCLib is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU Lesser General Public License as published |
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9 | * by the Free Software Foundation; version 2.1 of the License. |
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10 | * |
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11 | * SoCLib is distributed in the hope that it will be useful, but |
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12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | * Lesser General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU Lesser General Public |
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17 | * License along with SoCLib; if not, write to the Free Software |
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18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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19 | * 02110-1301 USA |
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20 | * |
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21 | * SOCLIB_LGPL_HEADER_END |
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22 | * |
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23 | * Copyright (c) UPMC, Lip6, SoC |
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24 | * manuel.bouyer@lip6.fr october 2013 |
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25 | * |
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26 | * Maintainers: bouyer |
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27 | */ |
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28 | |
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29 | #include <stdint.h> |
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30 | #include <iostream> |
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31 | #include <arithmetics.h> |
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32 | #include <fcntl.h> |
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33 | #include "vci_spi.h" |
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34 | #include "vcispi.h" |
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35 | |
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36 | namespace soclib { namespace caba { |
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37 | |
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38 | #define tmpl(t) template<typename vci_param> t VciSpi<vci_param> |
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39 | |
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40 | using namespace soclib::caba; |
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41 | using namespace soclib::common; |
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42 | |
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43 | //////////////////////// |
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44 | tmpl(void)::transition() |
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45 | { |
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46 | |
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47 | bool s_dma_bsy = (r_initiator_fsm != M_IDLE); |
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48 | if(p_resetn.read() == false) |
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49 | { |
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50 | r_initiator_fsm = M_IDLE; |
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51 | r_target_fsm = T_IDLE; |
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52 | r_spi_fsm = S_IDLE; |
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53 | r_ss = 0; |
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54 | r_divider = 0xffff; |
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55 | r_ctrl_char_len = 0; |
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56 | r_ctrl_ie = false; |
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57 | r_ctrl_cpol = false; |
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58 | r_ctrl_cpha = false; |
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59 | r_spi_bsy = false; |
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60 | r_dma_count = 0; |
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61 | r_spi_clk_counter = 0xffff; |
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62 | r_spi_clk = 0; |
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63 | r_spi_done = false; |
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64 | |
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65 | r_irq = false; |
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66 | r_read = false; |
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67 | |
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68 | r_dma_fifo_read.init(); |
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69 | r_dma_fifo_write.init(); |
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70 | |
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71 | return; |
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72 | } |
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73 | |
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74 | ////////////////////////////////////////////////////////////////////////////// |
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75 | // The Target FSM controls the following registers: |
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76 | // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read |
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77 | ////////////////////////////////////////////////////////////////////////////// |
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78 | |
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79 | if (r_spi_done) |
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80 | r_spi_bsy = false; |
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81 | |
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82 | switch(r_target_fsm) { |
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83 | //////////// |
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84 | case T_IDLE: |
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85 | { |
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86 | if ( p_vci_target.cmdval.read() ) |
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87 | { |
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88 | r_srcid = p_vci_target.srcid.read(); |
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89 | r_trdid = p_vci_target.trdid.read(); |
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90 | r_pktid = p_vci_target.pktid.read(); |
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91 | uint32_t wdata = p_vci_target.wdata.read(); |
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92 | sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); |
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93 | |
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94 | bool found = false; |
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95 | std::list<soclib::common::Segment>::iterator seg; |
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96 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
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97 | { |
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98 | if ( seg->contains(address) ) found = true; |
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99 | } |
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100 | |
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101 | |
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102 | if (not found) { |
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103 | if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) |
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104 | r_target_fsm = T_ERROR_WRITE; |
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105 | else |
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106 | r_target_fsm = T_ERROR_READ; |
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107 | } else if (p_vci_target.cmd.read() != vci_param::CMD_READ && |
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108 | p_vci_target.cmd.read() != vci_param::CMD_WRITE) { |
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109 | r_target_fsm = T_ERROR_READ; |
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110 | } else { |
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111 | bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_spi_bsy &!s_dma_bsy; |
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112 | uint32_t cell = (uint32_t)((address & 0x3F)>>2); |
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113 | switch(cell) { |
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114 | case SPI_DATA_TXRX0: |
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115 | r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; |
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116 | if (write) { |
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117 | r_txrx[0] = |
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118 | (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | |
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119 | ((uint64_t)wdata); |
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120 | } |
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121 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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122 | break; |
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123 | case SPI_DATA_TXRX1: |
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124 | r_rdata = r_txrx[0] >> 32; |
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125 | if (write) { |
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126 | r_txrx[0] = |
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127 | (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | |
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128 | ((uint64_t)wdata << 32); |
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129 | } |
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130 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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131 | break; |
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132 | case SPI_DATA_TXRX2: |
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133 | r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; |
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134 | if (write) { |
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135 | r_txrx[1] = |
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136 | (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | |
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137 | ((uint64_t)wdata); |
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138 | } |
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139 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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140 | break; |
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141 | case SPI_DATA_TXRX3: |
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142 | r_rdata = r_txrx[1] >> 32; |
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143 | if (write) { |
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144 | r_txrx[1] = |
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145 | (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | |
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146 | ((uint64_t)wdata << 32); |
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147 | } |
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148 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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149 | break; |
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150 | case SPI_CTRL: |
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151 | { |
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152 | uint32_t data = 0; |
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153 | if (r_ctrl_cpol.read()) |
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154 | data |= SPI_CTRL_CPOL; |
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155 | if (r_ctrl_cpha.read()) |
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156 | data |= SPI_CTRL_CPHA; |
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157 | if (r_ctrl_ie.read()) |
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158 | data |= SPI_CTRL_IE_EN; |
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159 | if (r_spi_bsy.read()) |
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160 | data |= SPI_CTRL_GO_BSY; |
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161 | if (s_dma_bsy) |
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162 | data |= SPI_CTRL_DMA_BSY; |
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163 | if (r_dma_error) |
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164 | data |= SPI_CTRL_DMA_ERR; |
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165 | data |= (uint32_t)r_ctrl_char_len.read(); |
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166 | r_rdata = data; |
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167 | if (write) { |
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168 | r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); |
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169 | r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); |
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170 | r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); |
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171 | if (wdata & SPI_CTRL_GO_BSY) |
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172 | r_spi_bsy = true; |
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173 | r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); |
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174 | #ifdef SOCLIB_MODULE_DEBUG |
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175 | if ((wdata & SPI_CTRL_GO_BSY) != 0) { |
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176 | std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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177 | } |
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178 | #endif |
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179 | } else { |
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180 | r_irq = r_irq & r_spi_bsy; |
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181 | } |
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182 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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183 | break; |
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184 | } |
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185 | case SPI_DIVIDER: |
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186 | r_rdata = r_divider.read(); |
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187 | if (write) { |
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188 | #ifdef SOCLIB_MODULE_DEBUG |
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189 | std::cout << name() << " divider set to " << std::dec << wdata << std::endl; |
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190 | #endif |
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191 | r_divider = wdata; |
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192 | } |
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193 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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194 | break; |
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195 | case SPI_SS: |
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196 | r_rdata = r_ss.read(); |
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197 | if (write) { |
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198 | r_ss = wdata; |
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199 | } |
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200 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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201 | break; |
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202 | case SPI_DMA_BASE: |
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203 | r_rdata = r_buf_address.read(); |
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204 | if (write) { |
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205 | r_buf_address = (r_buf_address & (uint64_t)0xffffffff00000000) | wdata; |
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206 | } |
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207 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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208 | break; |
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209 | case SPI_DMA_BASEH: |
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210 | r_rdata = r_buf_address >> 32; |
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211 | if (write) { |
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212 | r_buf_address = (r_buf_address & (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); |
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213 | } |
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214 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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215 | break; |
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216 | case SPI_DMA_COUNT: |
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217 | r_rdata = (r_dma_count.read() << m_byte2burst_shift) | |
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218 | r_read; |
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219 | if (write) { |
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220 | r_read = (wdata & 0x1); |
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221 | r_dma_count = wdata >> m_byte2burst_shift; |
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222 | r_ctrl_char_len = vci_param::B * 8; |
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223 | } |
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224 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; |
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225 | break; |
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226 | default: |
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227 | r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; |
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228 | break; |
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229 | } |
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230 | } |
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231 | } |
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232 | break; |
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233 | } |
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234 | //////////////////// |
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235 | case T_RSP_READ: |
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236 | case T_RSP_WRITE: |
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237 | case T_ERROR_READ: |
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238 | case T_ERROR_WRITE: |
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239 | if (p_vci_target.rspack.read() ) { |
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240 | r_target_fsm = T_IDLE; |
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241 | } |
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242 | break; |
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243 | } // end switch target fsm |
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244 | |
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245 | |
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246 | |
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247 | |
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248 | ////////////////////////////////////////////////////////////////////////////// |
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249 | // the SPI FSM controls SPI signals |
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250 | ////////////////////////////////////////////////////////////////////////////// |
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251 | if (r_spi_bsy == false) |
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252 | r_spi_done = false; |
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253 | switch (r_spi_fsm) { |
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254 | case S_IDLE: |
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255 | r_spi_clk_counter = r_divider.read(); |
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256 | r_spi_clk = 0; |
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257 | r_spi_clk_previous = r_ctrl_cpha; |
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258 | r_spi_clk_ignore = r_ctrl_cpha; |
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259 | r_spi_bit_count = r_ctrl_char_len; |
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260 | if (r_dma_count != 0) { |
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261 | if (r_read.read()) |
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262 | r_spi_fsm = S_DMA_SEND_START; |
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263 | else |
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264 | r_spi_fsm = S_DMA_RECEIVE; |
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265 | } else if (r_spi_bsy.read() && !r_spi_done.read()) { |
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266 | r_spi_fsm = S_XMIT; |
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267 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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268 | } |
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269 | break; |
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270 | case S_DMA_RECEIVE: |
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271 | { |
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272 | r_spi_clk_counter = r_divider.read(); |
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273 | r_spi_clk = 0; |
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274 | r_spi_clk_previous = r_ctrl_cpha; |
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275 | r_spi_clk_ignore = r_ctrl_cpha; |
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276 | r_spi_bit_count = r_ctrl_char_len; |
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277 | if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) { |
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278 | if (r_dma_fifo_write.rok()) { |
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279 | typename vci_param::data_t v = r_dma_fifo_write.read(); |
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280 | r_dma_fifo_write.simple_get(); |
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281 | r_txrx[0] = v; |
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282 | r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; |
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283 | r_spi_fsm = S_XMIT; |
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284 | } else if (r_initiator_fsm == M_WRITE_END) { |
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285 | r_spi_fsm = S_IDLE; |
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286 | } |
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287 | } |
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288 | break; |
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289 | } |
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290 | case S_DMA_SEND_START: |
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291 | r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; |
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292 | r_spi_out = 1; |
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293 | r_txrx[0] = 0xffffffff; |
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294 | r_spi_fsm = S_XMIT; |
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295 | break; |
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296 | case S_DMA_SEND: |
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297 | r_spi_out = 1; |
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298 | r_spi_clk_counter = r_divider.read(); |
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299 | r_spi_clk = 0; |
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300 | r_spi_clk_previous = r_ctrl_cpha; |
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301 | r_spi_clk_ignore = r_ctrl_cpha; |
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302 | r_spi_bit_count = r_ctrl_char_len; |
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303 | if (r_initiator_fsm != M_READ_CMD) { |
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304 | if (r_dma_fifo_read.wok()) { |
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305 | r_dma_fifo_read.simple_put( |
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306 | (typename vci_param::data_t)r_txrx[0]); |
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307 | r_spi_word_count = r_spi_word_count - 1; |
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308 | r_txrx[0] = 0xffffffff; |
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309 | if ( r_spi_word_count == 0 ) { |
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310 | r_spi_fsm = S_DMA_SEND_END; |
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311 | } else { |
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312 | r_spi_fsm = S_XMIT; |
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313 | } |
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314 | } |
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315 | } |
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316 | break; |
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317 | case S_DMA_SEND_END: |
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318 | if (r_initiator_fsm == M_IDLE) |
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319 | r_spi_fsm = S_IDLE; |
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320 | break; |
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321 | case S_XMIT: |
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322 | { |
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323 | bool s_clk_sample; |
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324 | // on clock transition, sample input line, and shift data |
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325 | s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
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326 | if (!r_spi_clk_ignore) { |
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327 | if (r_spi_clk_previous == 0 && s_clk_sample == 1) { |
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328 | // low to high transition: shift and sample |
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329 | r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); |
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330 | r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; |
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331 | r_spi_bit_count = r_spi_bit_count - 1; |
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332 | } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { |
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333 | // high to low transition: change output, or stop |
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334 | if (r_spi_bit_count == 0) { |
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335 | if (r_initiator_fsm != M_IDLE) { |
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336 | if (r_read) |
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337 | r_spi_fsm = S_DMA_SEND; |
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338 | else |
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339 | r_spi_fsm = S_DMA_RECEIVE; |
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340 | } else { |
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341 | r_spi_fsm = S_IDLE; |
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342 | r_irq = r_ctrl_ie; |
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343 | r_spi_done = true; |
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344 | } |
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345 | #ifdef SOCLIB_MODULE_DEBUG0 |
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346 | std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; |
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347 | #endif |
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348 | } else { |
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349 | r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
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350 | } |
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351 | } |
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352 | } |
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353 | r_spi_clk_previous = s_clk_sample; |
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354 | // generate the SPI clock |
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355 | if (r_spi_clk_counter.read() == 0) { |
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356 | r_spi_clk_counter = r_divider.read(); |
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357 | r_spi_clk = !r_spi_clk.read(); |
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358 | r_spi_clk_ignore = false; |
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359 | } else { |
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360 | r_spi_clk_counter = r_spi_clk_counter.read() - 1; |
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361 | } |
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362 | break; |
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363 | } |
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364 | } |
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365 | ////////////////////////////////////////////////////////////////////////////// |
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366 | // The initiator FSM executes a loop, transfering one burst per iteration. |
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367 | // data comes from or goes to fifos, the other end of the fifos is |
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368 | // feed by or eaten by the SPI fsm. |
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369 | ////////////////////////////////////////////////////////////////////////////// |
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370 | |
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371 | switch( r_initiator_fsm.read() ) { |
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372 | //////////// |
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373 | case M_IDLE: // check buffer alignment to compute the number of bursts |
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374 | { |
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375 | if ( r_dma_count != 0 ) |
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376 | { |
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377 | // start transfer |
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378 | if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; |
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379 | else r_initiator_fsm = M_WRITE_WAIT; |
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380 | } |
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381 | break; |
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382 | } |
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383 | case M_READ_WAIT: // wait for the FIFO to be full |
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384 | if (!r_dma_fifo_read.wok()) { |
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385 | r_burst_word = m_words_per_burst - 1; |
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386 | r_initiator_fsm = M_READ_CMD; |
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387 | } |
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388 | break; |
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389 | //////////////// |
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390 | case M_READ_CMD: // Send a multi-flits VCI WRITE command |
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391 | { |
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392 | if ( p_vci_initiator.cmdack.read() ) |
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393 | { |
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394 | if ( r_burst_word == 0 ) // last flit |
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395 | { |
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396 | r_initiator_fsm = M_READ_RSP; |
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397 | } |
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398 | else // not the last flit |
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399 | { |
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400 | r_burst_word = r_burst_word.read() - 1; |
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401 | } |
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402 | |
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403 | r_dma_fifo_read.simple_get(); // consume one fifo word |
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404 | // compute next word address |
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405 | r_buf_address = r_buf_address.read() + vci_param::B; |
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406 | } |
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407 | break; |
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408 | } |
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409 | //////////////// |
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410 | case M_READ_RSP: // Wait a single flit VCI WRITE response |
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411 | { |
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412 | if ( p_vci_initiator.rspval.read() ) |
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413 | { |
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414 | if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
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415 | { |
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416 | r_burst_word = 0; |
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417 | r_dma_count = 0; |
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418 | r_dma_error = true; |
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419 | r_initiator_fsm = M_IDLE; |
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420 | #ifdef SOCLIB_MODULE_DEBUG |
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421 | std::cout << "vci_bd M_READ_ERROR" << std::endl; |
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422 | #endif |
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423 | } |
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424 | else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst |
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425 | { |
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426 | r_dma_count = 0; |
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427 | r_initiator_fsm = M_IDLE; |
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428 | r_dma_error = false; |
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429 | #ifdef SOCLIB_MODULE_DEBUG |
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430 | std::cout << "vci_bd M_READ_SUCCESS" << std::endl; |
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431 | #endif |
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432 | } |
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433 | else // keep on reading |
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434 | { |
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435 | r_dma_count = r_dma_count - 1; |
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436 | r_initiator_fsm = M_READ_WAIT; |
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437 | } |
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438 | } |
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439 | break; |
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440 | } |
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441 | /////////////////// |
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442 | case M_WRITE_WAIT: // wait for the FIFO to be empty |
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443 | if (!r_dma_fifo_write.rok()) { |
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444 | r_burst_word = m_words_per_burst - 1; |
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445 | r_dma_count = r_dma_count - 1; |
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446 | r_initiator_fsm = M_WRITE_CMD; |
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447 | } |
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448 | break; |
---|
449 | ///////////////// |
---|
450 | case M_WRITE_CMD: // This is actually a single flit VCI READ command |
---|
451 | { |
---|
452 | if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; |
---|
453 | break; |
---|
454 | } |
---|
455 | ///////////////// |
---|
456 | case M_WRITE_RSP: // This is actually a multi-words VCI READ response |
---|
457 | { |
---|
458 | if ( p_vci_initiator.rspval.read() ) |
---|
459 | { |
---|
460 | typename vci_param::data_t v = p_vci_initiator.rdata.read(); |
---|
461 | typename vci_param::data_t f = 0; |
---|
462 | // byte-swap |
---|
463 | for (int i = 0; i < (vci_param::B * 8); i += 8) { |
---|
464 | f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
465 | } |
---|
466 | r_dma_fifo_write.simple_put(f); |
---|
467 | r_burst_word = r_burst_word.read() - 1; |
---|
468 | if ( p_vci_initiator.reop.read() ) // last flit of the burst |
---|
469 | { |
---|
470 | r_buf_address = r_buf_address.read() + m_burst_size; |
---|
471 | |
---|
472 | if( (p_vci_initiator.rerror.read()&0x1) != 0 ) |
---|
473 | { |
---|
474 | r_dma_count = 0; |
---|
475 | r_dma_error = 1; |
---|
476 | r_initiator_fsm = M_WRITE_END; |
---|
477 | #ifdef SOCLIB_MODULE_DEBUG |
---|
478 | std::cout << "vci_bd M_WRITE_ERROR" << std::endl; |
---|
479 | #endif |
---|
480 | } |
---|
481 | else if ( r_dma_count.read() == 0) // last burst |
---|
482 | { |
---|
483 | r_dma_error = 0; |
---|
484 | r_initiator_fsm = M_WRITE_END; |
---|
485 | } |
---|
486 | else // not the last burst |
---|
487 | { |
---|
488 | r_initiator_fsm = M_WRITE_WAIT; |
---|
489 | } |
---|
490 | } |
---|
491 | } |
---|
492 | break; |
---|
493 | } |
---|
494 | ///////////////// |
---|
495 | case M_WRITE_END: // wait for the write to be complete |
---|
496 | { |
---|
497 | if (r_spi_fsm == S_IDLE) { // write complete |
---|
498 | r_initiator_fsm = M_IDLE; |
---|
499 | } |
---|
500 | break; |
---|
501 | } |
---|
502 | } // end switch r_initiator_fsm |
---|
503 | } // end transition |
---|
504 | |
---|
505 | ////////////////////// |
---|
506 | tmpl(void)::genMoore() |
---|
507 | { |
---|
508 | // p_vci_target port |
---|
509 | p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); |
---|
510 | p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); |
---|
511 | p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read(); |
---|
512 | p_vci_target.reop = true; |
---|
513 | |
---|
514 | switch(r_target_fsm) { |
---|
515 | case T_IDLE: |
---|
516 | p_vci_target.cmdack = true; |
---|
517 | p_vci_target.rspval = false; |
---|
518 | p_vci_target.rdata = 0; |
---|
519 | break; |
---|
520 | case T_RSP_READ: |
---|
521 | p_vci_target.cmdack = false; |
---|
522 | p_vci_target.rspval = true; |
---|
523 | p_vci_target.rdata = r_rdata; |
---|
524 | p_vci_target.rerror = VCI_READ_OK; |
---|
525 | break; |
---|
526 | case T_RSP_WRITE: |
---|
527 | p_vci_target.cmdack = false; |
---|
528 | p_vci_target.rspval = true; |
---|
529 | p_vci_target.rdata = 0; |
---|
530 | p_vci_target.rerror = VCI_WRITE_OK; |
---|
531 | break; |
---|
532 | case T_ERROR_READ: |
---|
533 | p_vci_target.cmdack = false; |
---|
534 | p_vci_target.rspval = true; |
---|
535 | p_vci_target.rdata = 0; |
---|
536 | p_vci_target.rerror = VCI_READ_ERROR; |
---|
537 | break; |
---|
538 | case T_ERROR_WRITE: |
---|
539 | p_vci_target.cmdack = false; |
---|
540 | p_vci_target.rspval = true; |
---|
541 | p_vci_target.rdata = 0; |
---|
542 | p_vci_target.rerror = VCI_WRITE_ERROR; |
---|
543 | break; |
---|
544 | } // end switch target fsm |
---|
545 | |
---|
546 | // p_vci_initiator port |
---|
547 | p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid; |
---|
548 | p_vci_initiator.trdid = 0; |
---|
549 | p_vci_initiator.contig = true; |
---|
550 | p_vci_initiator.cons = false; |
---|
551 | p_vci_initiator.wrap = false; |
---|
552 | p_vci_initiator.cfixed = false; |
---|
553 | p_vci_initiator.clen = 0; |
---|
554 | |
---|
555 | switch (r_initiator_fsm) { |
---|
556 | case M_WRITE_CMD: // It is actually a single flit VCI read command |
---|
557 | p_vci_initiator.rspack = false; |
---|
558 | p_vci_initiator.cmdval = true; |
---|
559 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
560 | p_vci_initiator.cmd = vci_param::CMD_READ; |
---|
561 | p_vci_initiator.pktid = TYPE_READ_DATA_UNC; |
---|
562 | p_vci_initiator.wdata = 0; |
---|
563 | p_vci_initiator.be = 0; |
---|
564 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
565 | p_vci_initiator.eop = true; |
---|
566 | break; |
---|
567 | case M_READ_CMD: // It is actually a multi-words VCI WRITE command |
---|
568 | { |
---|
569 | typename vci_param::data_t v = 0; |
---|
570 | typename vci_param::data_t f; |
---|
571 | p_vci_initiator.rspack = false; |
---|
572 | p_vci_initiator.cmdval = true; |
---|
573 | p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); |
---|
574 | p_vci_initiator.cmd = vci_param::CMD_WRITE; |
---|
575 | p_vci_initiator.pktid = TYPE_WRITE; |
---|
576 | p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(m_burst_size); |
---|
577 | f = r_dma_fifo_read.read(); |
---|
578 | // byte-swap |
---|
579 | for (int i = 0; i < (vci_param::B * 8); i += 8) { |
---|
580 | v |= ((f >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); |
---|
581 | } |
---|
582 | p_vci_initiator.wdata = v; |
---|
583 | p_vci_initiator.eop = ( r_burst_word.read() == 0); |
---|
584 | if (vci_param::B == 8) |
---|
585 | { |
---|
586 | p_vci_initiator.be = 0xFF; |
---|
587 | } |
---|
588 | else |
---|
589 | { |
---|
590 | p_vci_initiator.be = 0xF; |
---|
591 | } |
---|
592 | break; |
---|
593 | } |
---|
594 | case M_READ_RSP: |
---|
595 | case M_WRITE_RSP: |
---|
596 | p_vci_initiator.rspack = true; |
---|
597 | p_vci_initiator.cmdval = false; |
---|
598 | break; |
---|
599 | default: |
---|
600 | p_vci_initiator.rspack = false; |
---|
601 | p_vci_initiator.cmdval = false; |
---|
602 | break; |
---|
603 | } |
---|
604 | |
---|
605 | // SPI signals |
---|
606 | p_spi_ss = ((r_ss & 0x1) == 0); |
---|
607 | switch(r_spi_fsm) { |
---|
608 | default: |
---|
609 | p_spi_mosi = r_spi_out; |
---|
610 | p_spi_clk = 0; |
---|
611 | break; |
---|
612 | case S_XMIT: |
---|
613 | { |
---|
614 | bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; |
---|
615 | p_spi_clk = r_spi_clk ^ r_ctrl_cpol; |
---|
616 | if (s_clk_sample == 0) { |
---|
617 | // clock low: get data directly from shift register |
---|
618 | // as r_spi_out may be delayed by one clock cycle |
---|
619 | p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; |
---|
620 | } else { |
---|
621 | // clock high: get data from saved value, as the shift register |
---|
622 | // may have changed |
---|
623 | p_spi_mosi = r_spi_out; |
---|
624 | } |
---|
625 | break; |
---|
626 | } |
---|
627 | } |
---|
628 | |
---|
629 | // IRQ signal |
---|
630 | p_irq = r_irq; |
---|
631 | } // end GenMoore() |
---|
632 | |
---|
633 | ////////////////////////////////////////////////////////////////////////////// |
---|
634 | tmpl(/**/)::VciSpi( sc_core::sc_module_name name, |
---|
635 | const soclib::common::MappingTable &mt, |
---|
636 | const soclib::common::IntTab &srcid, |
---|
637 | const soclib::common::IntTab &tgtid, |
---|
638 | const uint32_t burst_size) |
---|
639 | |
---|
640 | : caba::BaseModule(name), |
---|
641 | m_seglist(mt.getSegmentList(tgtid)), |
---|
642 | m_srcid(mt.indexForId(srcid)), |
---|
643 | m_burst_size(burst_size), |
---|
644 | m_words_per_burst(burst_size / vci_param::B), |
---|
645 | m_byte2burst_shift(soclib::common::uint32_log2(burst_size)), |
---|
646 | p_clk("p_clk"), |
---|
647 | p_resetn("p_resetn"), |
---|
648 | p_vci_initiator("p_vci_initiator"), |
---|
649 | p_vci_target("p_vci_target"), |
---|
650 | p_irq("p_irq"), |
---|
651 | p_spi_ss("p_spi_ss"), |
---|
652 | p_spi_clk("p_spi_clk"), |
---|
653 | p_spi_mosi("p_spi_mosi"), |
---|
654 | p_spi_miso("p_spi_miso"), |
---|
655 | |
---|
656 | r_dma_fifo_read("r_dma_fifo_read", burst_size / vci_param::B), // one cache line |
---|
657 | r_dma_fifo_write("r_dma_fifo_read", burst_size / vci_param::B) // one cache line |
---|
658 | { |
---|
659 | std::cout << " - Building VciSpi " << name << std::endl; |
---|
660 | |
---|
661 | SC_METHOD(transition); |
---|
662 | dont_initialize(); |
---|
663 | sensitive << p_clk.pos(); |
---|
664 | |
---|
665 | SC_METHOD(genMoore); |
---|
666 | dont_initialize(); |
---|
667 | sensitive << p_clk.neg(); |
---|
668 | |
---|
669 | size_t nbsegs = 0; |
---|
670 | std::list<soclib::common::Segment>::iterator seg; |
---|
671 | for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) |
---|
672 | { |
---|
673 | nbsegs++; |
---|
674 | |
---|
675 | if ( (seg->baseAddress() & 0x0000003F) != 0 ) |
---|
676 | { |
---|
677 | std::cout << "Error in component VciSpi : " << name |
---|
678 | << "The base address of segment " << seg->name() |
---|
679 | << " must be multiple of 64 bytes" << std::endl; |
---|
680 | exit(1); |
---|
681 | } |
---|
682 | if ( seg->size() < 64 ) |
---|
683 | { |
---|
684 | std::cout << "Error in component VciSpi : " << name |
---|
685 | << "The size of segment " << seg->name() |
---|
686 | << " cannot be smaller than 64 bytes" << std::endl; |
---|
687 | exit(1); |
---|
688 | } |
---|
689 | std::cout << " => segment " << seg->name() |
---|
690 | << " / base = " << std::hex << seg->baseAddress() |
---|
691 | << " / size = " << seg->size() << std::endl; |
---|
692 | } |
---|
693 | |
---|
694 | if( nbsegs == 0 ) |
---|
695 | { |
---|
696 | std::cout << "Error in component VciSpi : " << name |
---|
697 | << " No segment allocated" << std::endl; |
---|
698 | exit(1); |
---|
699 | } |
---|
700 | |
---|
701 | if( (burst_size != 8 ) && |
---|
702 | (burst_size != 16) && |
---|
703 | (burst_size != 32) && |
---|
704 | (burst_size != 64) ) |
---|
705 | { |
---|
706 | std::cout << "Error in component VciSpi : " << name |
---|
707 | << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; |
---|
708 | exit(1); |
---|
709 | } |
---|
710 | |
---|
711 | if ( (vci_param::B != 4) and (vci_param::B != 8) ) |
---|
712 | { |
---|
713 | std::cout << "Error in component VciSpi : " << name |
---|
714 | << " The VCI data fields must have 32 bits or 64 bits" << std::endl; |
---|
715 | exit(1); |
---|
716 | } |
---|
717 | |
---|
718 | } // end constructor |
---|
719 | |
---|
720 | tmpl(/**/)::~VciSpi() |
---|
721 | { |
---|
722 | } |
---|
723 | |
---|
724 | |
---|
725 | ////////////////////////// |
---|
726 | tmpl(void)::print_trace() |
---|
727 | { |
---|
728 | const char* initiator_str[] = |
---|
729 | { |
---|
730 | "M_IDLE", |
---|
731 | |
---|
732 | "M_READ_WAIT", |
---|
733 | "M_READ_CMD", |
---|
734 | "M_READ_RSP", |
---|
735 | |
---|
736 | "M_WRITE_WAIT", |
---|
737 | "M_WRITE_CMD", |
---|
738 | "M_WRITE_RSP", |
---|
739 | "M_WRITE_END", |
---|
740 | }; |
---|
741 | const char* target_str[] = |
---|
742 | { |
---|
743 | "T_IDLE", |
---|
744 | "T_RSP_READ", |
---|
745 | "T_RSP_WRITE", |
---|
746 | "T_ERROR_READ", |
---|
747 | "T_ERROR_WRITE", |
---|
748 | }; |
---|
749 | const char* spi_str[] = |
---|
750 | { |
---|
751 | "S_IDLE", |
---|
752 | "S_DMA_RECEIVE", |
---|
753 | "S_DMA_SEND_START", |
---|
754 | "S_DMA_SEND", |
---|
755 | "S_DMA_SEND_END", |
---|
756 | "S_XMIT", |
---|
757 | }; |
---|
758 | |
---|
759 | std::cout << name() << " _TGT : " << target_str[r_target_fsm.read()] |
---|
760 | << std::endl; |
---|
761 | std::cout << name() << " _SPI : " << spi_str[r_spi_fsm.read()] |
---|
762 | << " clk_counter " << r_spi_clk_counter.read() |
---|
763 | << " r_spi_bit_count " << r_spi_bit_count.read() |
---|
764 | << " r_spi_bsy " << (int)r_spi_bsy.read() << std::endl; |
---|
765 | std::cout << name() << " _SPI : " |
---|
766 | << " r_spi_clk " << r_spi_clk.read() |
---|
767 | << " cpol " << r_ctrl_cpol.read() |
---|
768 | << " cpha " << r_ctrl_cpha.read() |
---|
769 | << " r_spi_clk_ignore " << r_spi_clk_ignore.read() |
---|
770 | << " r_txrx 0x" << std::hex |
---|
771 | << r_txrx[1].read() << " " << r_txrx[0].read() |
---|
772 | |
---|
773 | << std::endl; |
---|
774 | std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] |
---|
775 | << " buf = " << std::hex << r_buf_address.read() |
---|
776 | << " burst = " << r_burst_word.read() |
---|
777 | << " count = " << r_dma_count.read() |
---|
778 | << " spi_count = " << r_spi_word_count.read() |
---|
779 | <<std::endl; |
---|
780 | } |
---|
781 | |
---|
782 | }} // end namespace |
---|
783 | |
---|
784 | // Local Variables: |
---|
785 | // tab-width: 4 |
---|
786 | // c-basic-offset: 4 |
---|
787 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
788 | // indent-tabs-mode: nil |
---|
789 | // End: |
---|
790 | |
---|
791 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
792 | |
---|