[123] | 1 | |
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[77] | 2 | /* -*- c++ -*- |
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[123] | 3 | * File : vci_synthetic_initiator.cpp |
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| 4 | * Date : 23/12/2010 |
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[77] | 5 | * Copyright : UPMC / LIP6 |
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| 6 | * Authors : Christophe Choichillon |
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[131] | 7 | * Version : 2.1 |
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[77] | 8 | * |
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| 9 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 10 | * |
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| 11 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 12 | * |
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| 13 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 14 | * under the terms of the GNU Lesser General Public License as published |
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| 15 | * by the Free Software Foundation; version 2.1 of the License. |
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| 16 | * |
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| 17 | * SoCLib is distributed in the hope that it will be useful, but |
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 20 | * Lesser General Public License for more details. |
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| 21 | * |
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| 22 | * You should have received a copy of the GNU Lesser General Public |
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| 23 | * License along with SoCLib; if not, write to the Free Software |
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| 24 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 25 | * 02110-1301 USA |
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| 26 | * |
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| 27 | * SOCLIB_LGPL_HEADER_END |
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| 28 | * |
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| 29 | * Maintainers: christophe.choichillon@lip6.fr |
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| 30 | */ |
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| 31 | |
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[78] | 32 | #include "../include/vci_synthetic_initiator.h" |
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[106] | 33 | #include <iostream> |
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[77] | 34 | |
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| 35 | |
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[122] | 36 | #define DETERMINISTIC |
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[77] | 37 | |
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| 38 | namespace soclib { namespace caba { |
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| 39 | |
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| 40 | |
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[78] | 41 | #define tmpl(x) template<typename vci_param> x VciSyntheticInitiator<vci_param> |
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[77] | 42 | |
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[78] | 43 | //using soclib::common::uint32_log2; |
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| 44 | |
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[77] | 45 | //////////////////////////////// |
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| 46 | // Constructor |
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| 47 | //////////////////////////////// |
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| 48 | |
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[78] | 49 | tmpl(/**/)::VciSyntheticInitiator( |
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[77] | 50 | sc_module_name name, |
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[102] | 51 | const soclib::common::MappingTable &mt, |
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| 52 | const soclib::common::IntTab &vci_index, |
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| 53 | const uint32_t length, // Packet length (flit numbers) |
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[128] | 54 | const uint32_t rho, // Offered load * 1000 |
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[102] | 55 | const uint32_t depth, // Fifo depth |
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| 56 | const uint32_t xmesh, |
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| 57 | const uint32_t ymesh, |
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| 58 | const uint32_t bc_period, // Broadcast period, if no broadcast => 0 |
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| 59 | const uint32_t xmin, |
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| 60 | const uint32_t xmax, |
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| 61 | const uint32_t ymin, |
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| 62 | const uint32_t ymax |
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[78] | 63 | ) |
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[77] | 64 | |
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| 65 | : soclib::caba::BaseModule(name), |
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| 66 | |
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| 67 | p_clk("clk"), |
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| 68 | p_resetn("resetn"), |
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| 69 | p_vci("vci_ini"), |
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| 70 | |
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[98] | 71 | m_srcid( mt.indexForId(vci_index) ), |
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[77] | 72 | // FIFOs |
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[81] | 73 | m_length(length), |
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| 74 | m_rho(rho), |
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| 75 | m_depth(depth), |
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| 76 | m_xmesh(xmesh), |
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| 77 | m_ymesh(ymesh), |
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| 78 | m_bc_period(bc_period), |
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| 79 | m_xmin(xmin), |
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| 80 | m_xmax(xmax), |
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| 81 | m_ymin(ymin), |
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| 82 | m_ymax(ymax), |
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[131] | 83 | r_date_fifo("r_date_fifo", m_depth), |
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| 84 | r_bc_fifo("r_bc_fifo", m_depth), |
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| 85 | r_cmd_fsm("r_cmd_fsm"), |
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| 86 | r_cmd_address("r_cmd_address"), |
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| 87 | r_cmd_trdid("r_cmd_trdid"), |
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| 88 | r_cmd_count("r_cmd_count"), |
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| 89 | r_cmd_seed("r_cmd_seed"), |
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| 90 | //r_bc_fsm("r_bc_fsm"), |
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| 91 | //r_bc_date("r_bc_date"), |
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| 92 | r_bc_nrsp("r_bc_nrsp"), |
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| 93 | r_cpt_cycles("r_cpt_cycles"), |
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| 94 | r_cpt_period("r_cpt_period"), |
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| 95 | r_nb_single("r_nb_single"), |
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| 96 | r_latency_single("r_latency_single"), |
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| 97 | r_nb_bc("r_nb_bc"), |
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| 98 | r_latency_bc("r_latency_bc") |
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[126] | 99 | { |
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[77] | 100 | |
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[131] | 101 | r_pending_fsm = new sc_signal<bool>[m_tab_size]; |
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| 102 | r_pending_date = new sc_signal<uint64_t>[m_tab_size]; |
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[77] | 103 | |
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| 104 | SC_METHOD(transition); |
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| 105 | dont_initialize(); |
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| 106 | sensitive << p_clk.pos(); |
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| 107 | |
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| 108 | SC_METHOD(genMoore); |
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| 109 | dont_initialize(); |
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| 110 | sensitive << p_clk.neg(); |
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| 111 | |
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| 112 | } // end constructor |
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| 113 | |
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| 114 | |
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| 115 | ///////////////////////////////// |
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[78] | 116 | tmpl(/**/)::~VciSyntheticInitiator() |
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[77] | 117 | ///////////////////////////////// |
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| 118 | { |
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[131] | 119 | delete r_pending_fsm; |
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| 120 | delete r_pending_date; |
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[77] | 121 | } |
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| 122 | |
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[81] | 123 | /////////////////////////////////// |
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[115] | 124 | tmpl(uint32_t)::destAdress() |
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[81] | 125 | /////////////////////////////////// |
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| 126 | { |
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[115] | 127 | return (uint32_t) (rand() % (m_xmesh * m_ymesh)) ; |
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[81] | 128 | } |
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| 129 | |
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[98] | 130 | |
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| 131 | /////////////////////////////////// |
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[115] | 132 | tmpl(uint32_t)::destAdress(uint32_t *rand_seed) |
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[98] | 133 | /////////////////////////////////// |
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[115] | 134 | { |
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| 135 | return (uint32_t) (rand_r(rand_seed) % (m_xmesh * m_ymesh)) ; |
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| 136 | } |
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[98] | 137 | |
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[106] | 138 | |
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[77] | 139 | ////////////////////////////////// |
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[106] | 140 | tmpl(void)::print_trace() |
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| 141 | ////////////////////////////////// |
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| 142 | { |
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[123] | 143 | const char* state_cmd_str[] = { "IDLE", |
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| 144 | "SINGLE_SEND", |
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| 145 | "BC_SEND"}; |
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[106] | 146 | |
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[123] | 147 | const char* state_bc_rsp_str[] = {"IDLE", |
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| 148 | "WAIT_RSP"}; |
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| 149 | |
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[106] | 150 | std::cout << "Vci_Synthetic_Initiator " << name() |
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[131] | 151 | << " : " << std::dec << r_cpt_cycles.read() << " cycles " |
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[123] | 152 | << " : state_cmd_fsm = " << state_cmd_str[r_cmd_fsm] |
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[131] | 153 | << " : state_rsp_fsm = " << state_bc_rsp_str[r_pending_fsm[0].read()] |
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[128] | 154 | << " Adresse to send : " << std::hex << r_cmd_address.read() |
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[123] | 155 | << " Number of broadcast to receive : " << std::dec << r_bc_nrsp.read() |
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[131] | 156 | << " Number of packets sent : " << std::dec << r_nb_single.read() << " " << r_cmd_trdid.read() << std::endl; |
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[123] | 157 | for(int i = 0; i < (1<<vci_param::T) ; i++){ |
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[131] | 158 | std::cout << "ID : " << i << " " << (uint64_t)(r_pending_date[i].read()) << std::endl; |
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[123] | 159 | } |
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[106] | 160 | } |
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| 161 | |
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| 162 | ////////////////////////////////// |
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| 163 | tmpl(void)::printStats() |
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| 164 | ////////////////////////////////// |
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| 165 | { |
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[131] | 166 | std::cout << name() << " : "<< std::dec << r_cpt_cycles.read() << " cycles, " << r_nb_single.read() << " packets sent" << std::endl; |
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[122] | 167 | if(m_bc_period) |
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[126] | 168 | std::cout << ((double)r_latency_bc.read()/(double)r_nb_bc.read()) << std::endl; |
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[106] | 169 | } |
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| 170 | |
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| 171 | ////////////////////////////////// |
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[77] | 172 | tmpl(void)::transition() |
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[106] | 173 | ////////////////////////////////// |
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[77] | 174 | { |
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| 175 | // RESET |
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[128] | 176 | if ( ! p_resetn.read() ) |
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| 177 | { |
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[98] | 178 | // Initializing seed for random numbers generation |
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[128] | 179 | |
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[122] | 180 | #ifndef DETERMINISTIC |
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[98] | 181 | srand(time(NULL)); |
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[115] | 182 | #endif |
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[77] | 183 | |
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[98] | 184 | // Initializing FSMs |
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[123] | 185 | r_cmd_fsm = VCI_IDLE; |
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[131] | 186 | //r_bc_fsm = false; |
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[128] | 187 | for(size_t i=0 ; i<m_tab_size ; i++) r_pending_fsm[i] = false; |
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[77] | 188 | |
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[98] | 189 | // Initializing FIFOs |
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[128] | 190 | r_date_fifo.init(); |
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| 191 | r_bc_fifo.init(); |
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[77] | 192 | |
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[128] | 193 | // Initializing the instrumentation registers |
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| 194 | r_latency_single = 0 ; |
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| 195 | r_nb_single = 0; |
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| 196 | r_latency_bc = 0 ; |
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| 197 | r_nb_bc = 0; |
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| 198 | r_cpt_cycles = 0; |
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| 199 | r_cpt_period = 0; |
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[122] | 200 | |
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[128] | 201 | r_cmd_seed = (uint32_t)m_srcid; |
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[77] | 202 | |
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| 203 | return; |
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| 204 | } |
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| 205 | |
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[128] | 206 | bool fifo_put = false; |
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| 207 | bool fifo_get = false; |
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| 208 | bool fifo_bc; |
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[77] | 209 | |
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[127] | 210 | uint32_t m_local_seed ; |
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[106] | 211 | |
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[128] | 212 | ////////////////// |
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| 213 | // VCI CMD FSM |
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| 214 | ////////////////// |
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[123] | 215 | switch ( r_cmd_fsm.read() ) { |
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[78] | 216 | case VCI_IDLE: |
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[77] | 217 | { |
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[128] | 218 | if (r_date_fifo.rok()) |
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| 219 | { |
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[131] | 220 | if ( r_bc_fifo.read() == true ) // its a broadcast request |
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[128] | 221 | { |
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[131] | 222 | if ( r_pending_fsm[0].read() == false ) // no current broadcast |
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[128] | 223 | { |
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[131] | 224 | r_cmd_fsm = VCI_BC_SEND ; |
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| 225 | r_cmd_address = 0x3 | (0x7c1f << vci_param::N-20) ; |
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[128] | 226 | } |
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| 227 | } |
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| 228 | else // its a single request |
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| 229 | { |
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| 230 | int id = -1; |
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[131] | 231 | for(int i = 1; i < m_tab_size; i++){ // ID 0 reserved for broadcast transactions |
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[128] | 232 | if(r_pending_fsm[i].read() == false) |
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| 233 | { |
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| 234 | id = i; |
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[123] | 235 | break; |
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| 236 | } |
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| 237 | } |
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[128] | 238 | if(id != -1){ |
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[123] | 239 | r_cmd_fsm = VCI_SINGLE_SEND ; |
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[128] | 240 | r_cmd_count = 0; |
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| 241 | r_cmd_trdid = id; |
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[123] | 242 | } |
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[122] | 243 | #ifdef DETERMINISTIC |
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[128] | 244 | m_local_seed = r_cmd_seed.read(); |
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| 245 | r_cmd_address = destAdress(&m_local_seed) << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); |
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| 246 | r_cmd_seed = m_local_seed; |
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[115] | 247 | #else |
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[128] | 248 | r_cmd_address = destAdress() << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); |
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[115] | 249 | #endif |
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[98] | 250 | } |
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| 251 | } |
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[77] | 252 | break; |
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| 253 | } |
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[78] | 254 | case VCI_SINGLE_SEND: |
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[77] | 255 | { |
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[128] | 256 | if ( p_vci.cmdack.read()) |
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| 257 | { |
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[131] | 258 | r_cmd_count = r_cmd_count.read() + 1; |
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[128] | 259 | if (r_cmd_count.read() == m_length-1) |
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| 260 | { |
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| 261 | r_nb_single = r_nb_single.read() + 1; |
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| 262 | r_cmd_fsm = VCI_SINGLE_REGISTER ; |
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[98] | 263 | } |
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| 264 | } |
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[77] | 265 | break; |
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| 266 | } |
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[128] | 267 | case VCI_SINGLE_REGISTER: |
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| 268 | { |
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[131] | 269 | r_pending_date[r_cmd_trdid.read()] = (uint64_t)(r_date_fifo.read()); |
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[128] | 270 | r_pending_fsm[r_cmd_trdid.read()] = true; |
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| 271 | fifo_get = true; |
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| 272 | r_cmd_fsm = VCI_IDLE; |
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| 273 | } |
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[123] | 274 | case VCI_BC_SEND: |
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[77] | 275 | { |
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[128] | 276 | if (p_vci.cmdack.read()) |
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| 277 | { |
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[131] | 278 | //r_bc_fsm = true; |
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[123] | 279 | r_bc_nrsp = (m_xmax - m_xmin) * (m_ymax - m_ymin) ; |
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[131] | 280 | //r_bc_date = (uint64_t)(r_date_fifo.read()); |
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| 281 | r_pending_fsm[0] = true; |
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| 282 | r_pending_date[0] = (uint64_t)(r_date_fifo.read()); |
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[128] | 283 | fifo_get = true; |
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| 284 | r_cmd_fsm = VCI_IDLE; |
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[123] | 285 | break; |
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[81] | 286 | } |
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[77] | 287 | } |
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[123] | 288 | } // end switch vci_fsm |
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| 289 | |
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[128] | 290 | ///////////////////// |
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| 291 | // BC_FSM |
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| 292 | ///////////////////// |
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[131] | 293 | //if ( r_pending_fsm[0].read() && p_vci.rspval.read() ) |
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| 294 | //{ |
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| 295 | // if ( p_vci.rtrdid.read() == 0 ) r_bc_nrsp = r_bc_nrsp.read() - 1; |
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| 296 | // if (r_bc_nrsp.read() == 1) |
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| 297 | // { |
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| 298 | // //r_bc_fsm = false; |
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| 299 | // r_pending_fsm[0] = false ; |
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| 300 | // r_latency_bc = r_latency_bc.read() + (r_cpt_cycles.read() - r_pending_date[0].read()); |
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| 301 | // } |
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| 302 | //} |
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[77] | 303 | |
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[128] | 304 | /////////////////// |
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| 305 | // PENDING FSMs |
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| 306 | ////////////////// |
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[131] | 307 | if(p_vci.rspval.read()) |
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[128] | 308 | { |
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[131] | 309 | if(p_vci.rtrdid.read() == 0) // not a broadcast |
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[128] | 310 | { |
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[131] | 311 | assert( ( r_pending_fsm[0].read() == true ) && |
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| 312 | "illegal broadcast response received"); |
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| 313 | r_bc_nrsp = r_bc_nrsp.read() - 1 ; |
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| 314 | if(r_bc_nrsp.read() == 1) |
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| 315 | { |
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| 316 | r_pending_fsm[0] = false; |
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| 317 | r_latency_bc = r_latency_bc.read() + (r_cpt_cycles.read() - r_pending_date[0].read()); |
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| 318 | } |
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| 319 | } |
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| 320 | else |
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| 321 | { |
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[128] | 322 | assert( ( r_pending_fsm[(int)p_vci.rtrdid.read()] == true ) && |
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[131] | 323 | "illegal single response received"); |
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[128] | 324 | r_pending_fsm[p_vci.rtrdid.read()] = false; |
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| 325 | r_latency_single = r_latency_single.read() + |
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| 326 | (r_cpt_cycles.read() - r_pending_date[(int)p_vci.rtrdid.read()].read()); |
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[123] | 327 | } |
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| 328 | } |
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[77] | 329 | |
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[128] | 330 | //////////////////////// |
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| 331 | // traffic regulator |
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| 332 | //////////////////////// |
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| 333 | if ( m_bc_period && (r_cpt_period.read() > m_bc_period) ) |
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| 334 | { |
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| 335 | fifo_put = true ; |
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| 336 | fifo_bc = true; |
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[129] | 337 | if (r_date_fifo.wok()) |
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| 338 | { |
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| 339 | r_nb_bc = r_nb_bc.read() + 1; |
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| 340 | r_cpt_period = 0; |
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| 341 | } |
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[81] | 342 | } |
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[128] | 343 | else if( ( (uint64_t)(m_rho*r_cpt_cycles.read()) > (uint64_t)(m_length*r_nb_single.read()*1000)) ) |
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| 344 | { |
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| 345 | fifo_put = true ; |
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| 346 | fifo_bc = false; |
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| 347 | if (r_date_fifo.wok()) r_nb_single = r_nb_single.read() + 1; |
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| 348 | } |
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[81] | 349 | |
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[131] | 350 | if ( m_bc_period && (r_cpt_period.read() > m_bc_period) && r_date_fifo.wok() ) |
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| 351 | r_cpt_period = 0; |
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[129] | 352 | else |
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[131] | 353 | r_cpt_period = r_cpt_period.read() + 1; |
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[129] | 354 | |
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[128] | 355 | //////////////////////// |
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| 356 | // update fifos |
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| 357 | //////////////////////// |
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[131] | 358 | if (fifo_put){ |
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| 359 | if (fifo_get){ |
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[128] | 360 | r_date_fifo.put_and_get(r_cpt_cycles.read()); |
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| 361 | r_bc_fifo.put_and_get(fifo_bc); |
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[77] | 362 | } else { |
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[131] | 363 | r_date_fifo.simple_put(r_cpt_cycles.read()); |
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[128] | 364 | r_bc_fifo.simple_put(fifo_bc); |
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[77] | 365 | } |
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| 366 | } else { |
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[131] | 367 | if (fifo_get){ |
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[128] | 368 | r_date_fifo.simple_get(); |
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| 369 | r_bc_fifo.simple_get(); |
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[77] | 370 | } |
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| 371 | } |
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[98] | 372 | |
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[128] | 373 | /////////////////////////// |
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| 374 | // increment local time |
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| 375 | /////////////////////////// |
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| 376 | r_cpt_cycles = r_cpt_cycles.read() + 1; |
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[77] | 377 | |
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[81] | 378 | return; |
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| 379 | |
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[77] | 380 | } // end transition() |
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| 381 | |
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| 382 | ///////////////////////////// |
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| 383 | tmpl(void)::genMoore() |
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[128] | 384 | ///////////////////////////// |
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[77] | 385 | { |
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| 386 | //////////////////////////////////////////////////////////// |
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[98] | 387 | // Command signals on the p_vci port |
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[77] | 388 | //////////////////////////////////////////////////////////// |
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[98] | 389 | p_vci.cmd = vci_param::CMD_WRITE; |
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[81] | 390 | p_vci.be = 0xF; |
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[123] | 391 | p_vci.srcid = m_srcid; |
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[81] | 392 | p_vci.cons = false; |
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| 393 | p_vci.wrap = false; |
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| 394 | p_vci.contig = true; |
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| 395 | p_vci.clen = 0; |
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| 396 | p_vci.cfixed = false; |
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[123] | 397 | p_vci.rspack = true; |
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[77] | 398 | |
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| 399 | |
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[123] | 400 | switch ( r_cmd_fsm.read() ) { |
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[77] | 401 | |
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[78] | 402 | ////////////////// |
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| 403 | case VCI_IDLE: |
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| 404 | { |
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[81] | 405 | p_vci.cmdval = false; |
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| 406 | p_vci.address = 0; |
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| 407 | p_vci.plen = 0; |
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| 408 | p_vci.wdata = 0; |
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| 409 | p_vci.trdid = 0; |
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[131] | 410 | p_vci.pktid = 0; |
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[81] | 411 | p_vci.eop = false; |
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[78] | 412 | break; |
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| 413 | } |
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| 414 | ////////////////// |
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| 415 | case VCI_SINGLE_SEND: |
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| 416 | { |
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[98] | 417 | p_vci.cmdval = true; |
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[131] | 418 | p_vci.address = (addr_t)(r_cmd_address.read() + (r_cmd_count.read()*4)); |
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[98] | 419 | p_vci.plen = m_length*4; |
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| 420 | p_vci.wdata = 0; |
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[131] | 421 | p_vci.trdid = r_cmd_trdid.read(); |
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| 422 | p_vci.pktid = 0; |
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| 423 | if (r_cmd_count.read() == m_length - 1 ) { |
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[98] | 424 | p_vci.eop = true; |
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| 425 | } else { |
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| 426 | p_vci.eop = false; |
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| 427 | } |
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[78] | 428 | break; |
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| 429 | } |
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| 430 | /////////////////// |
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| 431 | case VCI_BC_SEND: |
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| 432 | { |
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[98] | 433 | p_vci.cmdval = true; |
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[128] | 434 | p_vci.address = (addr_t) r_cmd_address.read(); |
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[98] | 435 | p_vci.plen = 4; |
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| 436 | p_vci.wdata = 0; |
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| 437 | p_vci.trdid = 0; |
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[131] | 438 | p_vci.pktid = 0; |
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[98] | 439 | p_vci.eop = true; |
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[78] | 440 | break; |
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| 441 | } |
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[131] | 442 | ////////////////// |
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| 443 | case VCI_SINGLE_REGISTER: |
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| 444 | { |
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| 445 | p_vci.cmdval = false; |
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| 446 | p_vci.address = 0; |
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| 447 | p_vci.plen = 0; |
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| 448 | p_vci.wdata = 0; |
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| 449 | p_vci.trdid = 0; |
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| 450 | p_vci.pktid = 0; |
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| 451 | p_vci.eop = false; |
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| 452 | break; |
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| 453 | } |
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[123] | 454 | } // end switch vci_cmd_fsm |
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[77] | 455 | |
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| 456 | } // end genMoore() |
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| 457 | |
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| 458 | }} // end name space |
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