[123] | 1 | |
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[77] | 2 | /* -*- c++ -*- |
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[123] | 3 | * File : vci_synthetic_initiator.cpp |
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| 4 | * Date : 23/12/2010 |
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[77] | 5 | * Copyright : UPMC / LIP6 |
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| 6 | * Authors : Christophe Choichillon |
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[131] | 7 | * Version : 2.1 |
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[77] | 8 | * |
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| 9 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 10 | * |
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| 11 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 12 | * |
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| 13 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 14 | * under the terms of the GNU Lesser General Public License as published |
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| 15 | * by the Free Software Foundation; version 2.1 of the License. |
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| 16 | * |
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| 17 | * SoCLib is distributed in the hope that it will be useful, but |
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 20 | * Lesser General Public License for more details. |
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| 21 | * |
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| 22 | * You should have received a copy of the GNU Lesser General Public |
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| 23 | * License along with SoCLib; if not, write to the Free Software |
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| 24 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 25 | * 02110-1301 USA |
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| 26 | * |
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| 27 | * SOCLIB_LGPL_HEADER_END |
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| 28 | * |
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| 29 | * Maintainers: christophe.choichillon@lip6.fr |
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| 30 | */ |
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| 31 | |
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[78] | 32 | #include "../include/vci_synthetic_initiator.h" |
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[106] | 33 | #include <iostream> |
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[77] | 34 | |
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| 35 | |
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[135] | 36 | //#define DETERMINISTIC |
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[145] | 37 | #define RANDOM_PERIOD |
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[77] | 38 | |
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| 39 | namespace soclib { namespace caba { |
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| 40 | |
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| 41 | |
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[78] | 42 | #define tmpl(x) template<typename vci_param> x VciSyntheticInitiator<vci_param> |
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[77] | 43 | |
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[78] | 44 | //using soclib::common::uint32_log2; |
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| 45 | |
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[77] | 46 | //////////////////////////////// |
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| 47 | // Constructor |
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| 48 | //////////////////////////////// |
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| 49 | |
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[78] | 50 | tmpl(/**/)::VciSyntheticInitiator( |
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[77] | 51 | sc_module_name name, |
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[102] | 52 | const soclib::common::MappingTable &mt, |
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| 53 | const soclib::common::IntTab &vci_index, |
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| 54 | const uint32_t length, // Packet length (flit numbers) |
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[128] | 55 | const uint32_t rho, // Offered load * 1000 |
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[102] | 56 | const uint32_t depth, // Fifo depth |
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| 57 | const uint32_t xmesh, |
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| 58 | const uint32_t ymesh, |
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| 59 | const uint32_t bc_period, // Broadcast period, if no broadcast => 0 |
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| 60 | const uint32_t xmin, |
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| 61 | const uint32_t xmax, |
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| 62 | const uint32_t ymin, |
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| 63 | const uint32_t ymax |
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[78] | 64 | ) |
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[77] | 65 | |
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| 66 | : soclib::caba::BaseModule(name), |
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| 67 | |
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| 68 | p_clk("clk"), |
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| 69 | p_resetn("resetn"), |
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| 70 | p_vci("vci_ini"), |
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[135] | 71 | // FIFOs |
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[98] | 72 | m_srcid( mt.indexForId(vci_index) ), |
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[81] | 73 | m_length(length), |
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| 74 | m_rho(rho), |
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| 75 | m_depth(depth), |
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| 76 | m_xmesh(xmesh), |
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| 77 | m_ymesh(ymesh), |
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| 78 | m_bc_period(bc_period), |
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| 79 | m_xmin(xmin), |
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| 80 | m_xmax(xmax), |
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| 81 | m_ymin(ymin), |
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| 82 | m_ymax(ymax), |
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[131] | 83 | r_date_fifo("r_date_fifo", m_depth), |
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| 84 | r_bc_fifo("r_bc_fifo", m_depth), |
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| 85 | r_cmd_fsm("r_cmd_fsm"), |
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| 86 | r_cmd_address("r_cmd_address"), |
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| 87 | r_cmd_trdid("r_cmd_trdid"), |
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| 88 | r_cmd_count("r_cmd_count"), |
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| 89 | r_cmd_seed("r_cmd_seed"), |
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| 90 | r_bc_nrsp("r_bc_nrsp"), |
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| 91 | r_cpt_cycles("r_cpt_cycles"), |
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| 92 | r_cpt_period("r_cpt_period"), |
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| 93 | r_nb_single("r_nb_single"), |
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| 94 | r_latency_single("r_latency_single"), |
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| 95 | r_nb_bc("r_nb_bc"), |
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[146] | 96 | r_latency_bc("r_latency_bc"), |
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| 97 | r_time_to_next_bc("r_time_to_next_bc") |
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[126] | 98 | { |
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[77] | 99 | |
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[131] | 100 | r_pending_fsm = new sc_signal<bool>[m_tab_size]; |
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| 101 | r_pending_date = new sc_signal<uint64_t>[m_tab_size]; |
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[77] | 102 | |
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| 103 | SC_METHOD(transition); |
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| 104 | dont_initialize(); |
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| 105 | sensitive << p_clk.pos(); |
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| 106 | |
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| 107 | SC_METHOD(genMoore); |
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| 108 | dont_initialize(); |
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| 109 | sensitive << p_clk.neg(); |
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| 110 | |
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| 111 | } // end constructor |
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| 112 | |
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| 113 | |
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| 114 | ///////////////////////////////// |
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[78] | 115 | tmpl(/**/)::~VciSyntheticInitiator() |
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[77] | 116 | ///////////////////////////////// |
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| 117 | { |
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[131] | 118 | delete r_pending_fsm; |
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| 119 | delete r_pending_date; |
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[77] | 120 | } |
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| 121 | |
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[81] | 122 | /////////////////////////////////// |
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[115] | 123 | tmpl(uint32_t)::destAdress() |
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[81] | 124 | /////////////////////////////////// |
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| 125 | { |
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[115] | 126 | return (uint32_t) (rand() % (m_xmesh * m_ymesh)) ; |
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[81] | 127 | } |
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| 128 | |
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[98] | 129 | |
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| 130 | /////////////////////////////////// |
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[115] | 131 | tmpl(uint32_t)::destAdress(uint32_t *rand_seed) |
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[98] | 132 | /////////////////////////////////// |
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[115] | 133 | { |
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| 134 | return (uint32_t) (rand_r(rand_seed) % (m_xmesh * m_ymesh)) ; |
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| 135 | } |
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[98] | 136 | |
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[77] | 137 | ////////////////////////////////// |
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[145] | 138 | tmpl(double)::getLatencySingle() |
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| 139 | ////////////////////////////////// |
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| 140 | { |
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| 141 | if (m_rho) |
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| 142 | return (double)(r_latency_single.read())/(double)(r_nb_single.read()); |
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| 143 | else |
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| 144 | return 0; |
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| 145 | |
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| 146 | } |
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| 147 | |
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| 148 | ////////////////////////////////// |
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| 149 | tmpl(double)::getLatencyBC() |
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| 150 | ////////////////////////////////// |
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| 151 | { |
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[180] | 152 | double latency = (double)r_latency_bc.read(); |
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| 153 | double nb = (double)r_nb_bc.read(); |
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| 154 | std::cout << "Latency BC : " <<std::dec << latency << " nb_bc : " << nb << std::endl; |
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[145] | 155 | if(m_bc_period) |
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[180] | 156 | return (latency/nb); |
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[145] | 157 | else |
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| 158 | return 0; |
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| 159 | |
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| 160 | } |
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| 161 | |
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| 162 | ////////////////////////////////// |
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[106] | 163 | tmpl(void)::print_trace() |
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| 164 | ////////////////////////////////// |
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| 165 | { |
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[123] | 166 | const char* state_cmd_str[] = { "IDLE", |
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| 167 | "SINGLE_SEND", |
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| 168 | "BC_SEND"}; |
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[106] | 169 | |
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[123] | 170 | const char* state_bc_rsp_str[] = {"IDLE", |
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| 171 | "WAIT_RSP"}; |
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| 172 | |
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[106] | 173 | std::cout << "Vci_Synthetic_Initiator " << name() |
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[131] | 174 | << " : " << std::dec << r_cpt_cycles.read() << " cycles " |
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[123] | 175 | << " : state_cmd_fsm = " << state_cmd_str[r_cmd_fsm] |
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[131] | 176 | << " : state_rsp_fsm = " << state_bc_rsp_str[r_pending_fsm[0].read()] |
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[128] | 177 | << " Adresse to send : " << std::hex << r_cmd_address.read() |
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[146] | 178 | << " Number of BC_RSP to receive : " << std::dec << r_bc_nrsp.read() |
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[145] | 179 | << " Number of packets sent : " << std::dec << r_nb_single.read() << " " << r_cmd_trdid.read() |
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[146] | 180 | << " Number of BC sent : " << r_nb_bc.read() |
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[180] | 181 | << " Cycles to the next BC : " << r_time_to_next_bc.read() |
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| 182 | << " FIFO status : " << r_date_fifo.filled_status() << std::endl; |
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[123] | 183 | for(int i = 0; i < (1<<vci_param::T) ; i++){ |
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[131] | 184 | std::cout << "ID : " << i << " " << (uint64_t)(r_pending_date[i].read()) << std::endl; |
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[123] | 185 | } |
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[106] | 186 | } |
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| 187 | |
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| 188 | ////////////////////////////////// |
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| 189 | tmpl(void)::printStats() |
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| 190 | ////////////////////////////////// |
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| 191 | { |
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[131] | 192 | std::cout << name() << " : "<< std::dec << r_cpt_cycles.read() << " cycles, " << r_nb_single.read() << " packets sent" << std::endl; |
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[135] | 193 | if (m_rho) |
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| 194 | { |
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| 195 | std::cout << "Average latency : " << (double)(r_latency_single.read())/(double)(r_nb_single.read()) << std::endl; |
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| 196 | } |
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[122] | 197 | if(m_bc_period) |
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[132] | 198 | { |
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| 199 | std::cout << "Number of broadcast sent and received : " << r_nb_bc.read() << std::endl; |
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[135] | 200 | std::cout << "Average latency : " << ((double)r_latency_bc.read()/(double)r_nb_bc.read()) << std::endl; |
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[132] | 201 | } |
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[106] | 202 | } |
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| 203 | |
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| 204 | ////////////////////////////////// |
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[77] | 205 | tmpl(void)::transition() |
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[106] | 206 | ////////////////////////////////// |
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[77] | 207 | { |
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| 208 | // RESET |
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[128] | 209 | if ( ! p_resetn.read() ) |
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| 210 | { |
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[98] | 211 | // Initializing seed for random numbers generation |
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[128] | 212 | |
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[180] | 213 | //#ifndef DETERMINISTIC |
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| 214 | // srand(time(NULL)); |
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| 215 | //#endif |
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[77] | 216 | |
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[98] | 217 | // Initializing FSMs |
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[123] | 218 | r_cmd_fsm = VCI_IDLE; |
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[128] | 219 | for(size_t i=0 ; i<m_tab_size ; i++) r_pending_fsm[i] = false; |
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[77] | 220 | |
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[98] | 221 | // Initializing FIFOs |
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[128] | 222 | r_date_fifo.init(); |
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| 223 | r_bc_fifo.init(); |
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[77] | 224 | |
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[128] | 225 | // Initializing the instrumentation registers |
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[135] | 226 | r_latency_single = 0; |
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[128] | 227 | r_nb_single = 0; |
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[135] | 228 | r_latency_bc = 0; |
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[128] | 229 | r_nb_bc = 0; |
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| 230 | r_cpt_cycles = 0; |
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| 231 | r_cpt_period = 0; |
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[122] | 232 | |
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[135] | 233 | r_cmd_seed = (uint32_t)m_srcid; |
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[180] | 234 | |
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| 235 | //std::cout << name() << " " << std::dec << m_bc_period << std::endl; |
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[77] | 236 | |
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[180] | 237 | if (m_bc_period){ |
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| 238 | uint32_t a = (uint32_t)(rand()%(2*m_bc_period)); |
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| 239 | //std::cout << name() << " " << std::dec << a << std::endl; |
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| 240 | r_time_to_next_bc = a; |
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| 241 | } else { |
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| 242 | //std::cout << "c'est 0 " << std::endl; |
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| 243 | r_time_to_next_bc = 0; |
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| 244 | } |
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[146] | 245 | |
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[77] | 246 | return; |
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| 247 | } |
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| 248 | |
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[128] | 249 | bool fifo_put = false; |
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| 250 | bool fifo_get = false; |
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[135] | 251 | bool fifo_bc = false; |
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[77] | 252 | |
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[135] | 253 | |
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| 254 | #ifdef DETERMINISTIC |
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[127] | 255 | uint32_t m_local_seed ; |
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[135] | 256 | #endif |
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[106] | 257 | |
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[128] | 258 | ////////////////// |
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| 259 | // VCI CMD FSM |
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| 260 | ////////////////// |
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[123] | 261 | switch ( r_cmd_fsm.read() ) { |
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[78] | 262 | case VCI_IDLE: |
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[77] | 263 | { |
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[128] | 264 | if (r_date_fifo.rok()) |
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| 265 | { |
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[131] | 266 | if ( r_bc_fifo.read() == true ) // its a broadcast request |
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[128] | 267 | { |
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[131] | 268 | if ( r_pending_fsm[0].read() == false ) // no current broadcast |
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[128] | 269 | { |
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[180] | 270 | //std::cout << name() << "SENDING BC" << std::endl; |
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[131] | 271 | r_cmd_fsm = VCI_BC_SEND ; |
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| 272 | r_cmd_address = 0x3 | (0x7c1f << vci_param::N-20) ; |
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[128] | 273 | } |
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| 274 | } |
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| 275 | else // its a single request |
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| 276 | { |
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| 277 | int id = -1; |
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[135] | 278 | for(size_t i = 1; i < m_tab_size; i++){ // ID 0 reserved for broadcast transactions |
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[190] | 279 | if( r_pending_fsm[i].read() == false ) |
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[128] | 280 | { |
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[135] | 281 | id = (int)i; |
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[123] | 282 | break; |
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| 283 | } |
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| 284 | } |
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[128] | 285 | if(id != -1){ |
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[123] | 286 | r_cmd_fsm = VCI_SINGLE_SEND ; |
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[128] | 287 | r_cmd_count = 0; |
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| 288 | r_cmd_trdid = id; |
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[123] | 289 | } |
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[122] | 290 | #ifdef DETERMINISTIC |
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[128] | 291 | m_local_seed = r_cmd_seed.read(); |
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| 292 | r_cmd_address = destAdress(&m_local_seed) << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); |
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| 293 | r_cmd_seed = m_local_seed; |
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[115] | 294 | #else |
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[128] | 295 | r_cmd_address = destAdress() << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); |
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[115] | 296 | #endif |
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[98] | 297 | } |
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| 298 | } |
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[77] | 299 | break; |
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| 300 | } |
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[78] | 301 | case VCI_SINGLE_SEND: |
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[77] | 302 | { |
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[128] | 303 | if ( p_vci.cmdack.read()) |
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| 304 | { |
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[131] | 305 | r_cmd_count = r_cmd_count.read() + 1; |
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[128] | 306 | if (r_cmd_count.read() == m_length-1) |
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| 307 | { |
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[135] | 308 | //r_nb_single = r_nb_single.read() + 1; |
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[128] | 309 | r_cmd_fsm = VCI_SINGLE_REGISTER ; |
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[98] | 310 | } |
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| 311 | } |
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[77] | 312 | break; |
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| 313 | } |
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[128] | 314 | case VCI_SINGLE_REGISTER: |
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| 315 | { |
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[131] | 316 | r_pending_date[r_cmd_trdid.read()] = (uint64_t)(r_date_fifo.read()); |
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[128] | 317 | r_pending_fsm[r_cmd_trdid.read()] = true; |
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| 318 | fifo_get = true; |
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| 319 | r_cmd_fsm = VCI_IDLE; |
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[190] | 320 | break; |
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| 321 | } |
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[123] | 322 | case VCI_BC_SEND: |
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[77] | 323 | { |
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[128] | 324 | if (p_vci.cmdack.read()) |
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| 325 | { |
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[180] | 326 | //std::cout << std::dec << r_cpt_cycles.read() << "ns " << name() << " BC SEND " << r_nb_bc.read() << " " << r_time_to_next_bc.read() << std::endl; |
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[123] | 327 | r_bc_nrsp = (m_xmax - m_xmin) * (m_ymax - m_ymin) ; |
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[131] | 328 | r_pending_fsm[0] = true; |
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| 329 | r_pending_date[0] = (uint64_t)(r_date_fifo.read()); |
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[128] | 330 | fifo_get = true; |
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| 331 | r_cmd_fsm = VCI_IDLE; |
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[123] | 332 | break; |
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[81] | 333 | } |
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[77] | 334 | } |
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[123] | 335 | } // end switch vci_fsm |
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| 336 | |
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[132] | 337 | |
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[128] | 338 | /////////////////// |
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| 339 | // PENDING FSMs |
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| 340 | ////////////////// |
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[131] | 341 | if(p_vci.rspval.read()) |
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[128] | 342 | { |
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[131] | 343 | if(p_vci.rtrdid.read() == 0) // not a broadcast |
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[128] | 344 | { |
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[190] | 345 | assert( ( r_pending_fsm[0].read() == true ) && |
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[131] | 346 | "illegal broadcast response received"); |
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| 347 | r_bc_nrsp = r_bc_nrsp.read() - 1 ; |
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| 348 | if(r_bc_nrsp.read() == 1) |
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| 349 | { |
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| 350 | r_pending_fsm[0] = false; |
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| 351 | r_latency_bc = r_latency_bc.read() + (r_cpt_cycles.read() - r_pending_date[0].read()); |
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[180] | 352 | //std::cout << std::dec << r_cpt_cycles.read() << "ns " << name() << " BC done " << std::endl; |
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[131] | 353 | } |
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| 354 | } |
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| 355 | else |
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| 356 | { |
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[128] | 357 | assert( ( r_pending_fsm[(int)p_vci.rtrdid.read()] == true ) && |
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[131] | 358 | "illegal single response received"); |
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[128] | 359 | r_pending_fsm[p_vci.rtrdid.read()] = false; |
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| 360 | r_latency_single = r_latency_single.read() + |
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| 361 | (r_cpt_cycles.read() - r_pending_date[(int)p_vci.rtrdid.read()].read()); |
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[123] | 362 | } |
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| 363 | } |
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[77] | 364 | |
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[128] | 365 | //////////////////////// |
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| 366 | // traffic regulator |
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| 367 | //////////////////////// |
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[146] | 368 | if ( m_bc_period && (r_cpt_period.read() > r_time_to_next_bc.read()) ) |
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[128] | 369 | { |
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| 370 | fifo_put = true ; |
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| 371 | fifo_bc = true; |
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[129] | 372 | if (r_date_fifo.wok()) |
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| 373 | { |
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| 374 | r_nb_bc = r_nb_bc.read() + 1; |
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[180] | 375 | // r_cpt_period = 0; |
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| 376 | //#ifdef RANDOM_PERIOD |
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| 377 | // r_time_to_next_bc = (uint32_t)(rand()%(2*m_bc_period)); |
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| 378 | //#endif |
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[129] | 379 | } |
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[81] | 380 | } |
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[128] | 381 | else if( ( (uint64_t)(m_rho*r_cpt_cycles.read()) > (uint64_t)(m_length*r_nb_single.read()*1000)) ) |
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| 382 | { |
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| 383 | fifo_put = true ; |
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| 384 | fifo_bc = false; |
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| 385 | if (r_date_fifo.wok()) r_nb_single = r_nb_single.read() + 1; |
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| 386 | } |
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[81] | 387 | |
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[146] | 388 | if ( m_bc_period && (r_cpt_period.read() > r_time_to_next_bc.read()) && r_date_fifo.wok() ) |
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| 389 | { |
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[145] | 390 | #ifdef RANDOM_PERIOD |
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[146] | 391 | r_time_to_next_bc = (uint32_t)(rand()%(2*m_bc_period)); |
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| 392 | #endif |
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[131] | 393 | r_cpt_period = 0; |
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[146] | 394 | } |
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[129] | 395 | else |
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[131] | 396 | r_cpt_period = r_cpt_period.read() + 1; |
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[129] | 397 | |
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[128] | 398 | //////////////////////// |
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| 399 | // update fifos |
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| 400 | //////////////////////// |
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[131] | 401 | if (fifo_put){ |
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| 402 | if (fifo_get){ |
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[128] | 403 | r_date_fifo.put_and_get(r_cpt_cycles.read()); |
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| 404 | r_bc_fifo.put_and_get(fifo_bc); |
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[77] | 405 | } else { |
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[131] | 406 | r_date_fifo.simple_put(r_cpt_cycles.read()); |
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[128] | 407 | r_bc_fifo.simple_put(fifo_bc); |
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[77] | 408 | } |
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| 409 | } else { |
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[131] | 410 | if (fifo_get){ |
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[128] | 411 | r_date_fifo.simple_get(); |
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| 412 | r_bc_fifo.simple_get(); |
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[77] | 413 | } |
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| 414 | } |
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[98] | 415 | |
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[128] | 416 | /////////////////////////// |
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| 417 | // increment local time |
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| 418 | /////////////////////////// |
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| 419 | r_cpt_cycles = r_cpt_cycles.read() + 1; |
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[77] | 420 | |
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[81] | 421 | return; |
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| 422 | |
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[77] | 423 | } // end transition() |
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| 424 | |
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| 425 | ///////////////////////////// |
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| 426 | tmpl(void)::genMoore() |
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[128] | 427 | ///////////////////////////// |
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[77] | 428 | { |
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| 429 | //////////////////////////////////////////////////////////// |
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[98] | 430 | // Command signals on the p_vci port |
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[77] | 431 | //////////////////////////////////////////////////////////// |
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[98] | 432 | p_vci.cmd = vci_param::CMD_WRITE; |
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[81] | 433 | p_vci.be = 0xF; |
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[123] | 434 | p_vci.srcid = m_srcid; |
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[81] | 435 | p_vci.cons = false; |
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| 436 | p_vci.wrap = false; |
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| 437 | p_vci.contig = true; |
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| 438 | p_vci.clen = 0; |
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| 439 | p_vci.cfixed = false; |
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[123] | 440 | p_vci.rspack = true; |
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[77] | 441 | |
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| 442 | |
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[123] | 443 | switch ( r_cmd_fsm.read() ) { |
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[77] | 444 | |
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[78] | 445 | ////////////////// |
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| 446 | case VCI_IDLE: |
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| 447 | { |
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[81] | 448 | p_vci.cmdval = false; |
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| 449 | p_vci.address = 0; |
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| 450 | p_vci.plen = 0; |
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| 451 | p_vci.wdata = 0; |
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| 452 | p_vci.trdid = 0; |
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[131] | 453 | p_vci.pktid = 0; |
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[81] | 454 | p_vci.eop = false; |
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[78] | 455 | break; |
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| 456 | } |
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| 457 | ////////////////// |
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| 458 | case VCI_SINGLE_SEND: |
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| 459 | { |
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[98] | 460 | p_vci.cmdval = true; |
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[131] | 461 | p_vci.address = (addr_t)(r_cmd_address.read() + (r_cmd_count.read()*4)); |
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[98] | 462 | p_vci.plen = m_length*4; |
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| 463 | p_vci.wdata = 0; |
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[131] | 464 | p_vci.trdid = r_cmd_trdid.read(); |
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| 465 | p_vci.pktid = 0; |
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| 466 | if (r_cmd_count.read() == m_length - 1 ) { |
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[98] | 467 | p_vci.eop = true; |
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| 468 | } else { |
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| 469 | p_vci.eop = false; |
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| 470 | } |
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[78] | 471 | break; |
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| 472 | } |
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| 473 | /////////////////// |
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| 474 | case VCI_BC_SEND: |
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| 475 | { |
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[98] | 476 | p_vci.cmdval = true; |
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[128] | 477 | p_vci.address = (addr_t) r_cmd_address.read(); |
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[98] | 478 | p_vci.plen = 4; |
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| 479 | p_vci.wdata = 0; |
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| 480 | p_vci.trdid = 0; |
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[131] | 481 | p_vci.pktid = 0; |
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[98] | 482 | p_vci.eop = true; |
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[78] | 483 | break; |
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| 484 | } |
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[131] | 485 | ////////////////// |
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| 486 | case VCI_SINGLE_REGISTER: |
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| 487 | { |
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| 488 | p_vci.cmdval = false; |
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| 489 | p_vci.address = 0; |
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| 490 | p_vci.plen = 0; |
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| 491 | p_vci.wdata = 0; |
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| 492 | p_vci.trdid = 0; |
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| 493 | p_vci.pktid = 0; |
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| 494 | p_vci.eop = false; |
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| 495 | break; |
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| 496 | } |
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[123] | 497 | } // end switch vci_cmd_fsm |
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[77] | 498 | |
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| 499 | } // end genMoore() |
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| 500 | |
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| 501 | }} // end name space |
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