[148] | 1 | /* -*- c++ -*- |
---|
| 2 | * File : vci_vdspin_initiator_wrapper.cpp |
---|
| 3 | * Copyright (c) UPMC, Lip6 |
---|
| 4 | * Authors : Alain Greiner |
---|
| 5 | * |
---|
| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
---|
| 7 | * |
---|
| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
---|
| 9 | * |
---|
| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
---|
| 11 | * under the terms of the GNU Lesser General Public License as published |
---|
| 12 | * by the Free Software Foundation; version 2.1 of the License. |
---|
| 13 | * |
---|
| 14 | * SoCLib is distributed in the hope that it will be useful, but |
---|
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 17 | * Lesser General Public License for more details. |
---|
| 18 | * |
---|
| 19 | * You should have received a copy of the GNU Lesser General Public |
---|
| 20 | * License along with SoCLib; if not, write to the Free Software |
---|
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
---|
| 22 | * 02110-1301 USA |
---|
| 23 | * |
---|
| 24 | * SOCLIB_LGPL_HEADER_END |
---|
| 25 | */ |
---|
| 26 | |
---|
| 27 | #include "../include/vci_vdspin_initiator_wrapper.h" |
---|
| 28 | |
---|
| 29 | namespace soclib { namespace caba { |
---|
| 30 | |
---|
| 31 | #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> |
---|
| 32 | |
---|
| 33 | //////////////////////////////////////////////////////////://////////////////////////////// |
---|
| 34 | tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name name, |
---|
| 35 | size_t cmd_fifo_depth, |
---|
| 36 | size_t rsp_fifo_depth) |
---|
| 37 | : soclib::caba::BaseModule(name), |
---|
| 38 | p_clk("p_clk"), |
---|
| 39 | p_resetn("p_resetn"), |
---|
| 40 | p_dspin_out("p_dspin_out"), |
---|
| 41 | p_dspin_in("p_dspin_in"), |
---|
| 42 | p_vci("p_vci"), |
---|
| 43 | r_cmd_fsm("r_cmd_fsm"), |
---|
| 44 | r_rsp_fsm("r_rsp_fsm"), |
---|
| 45 | r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), |
---|
| 46 | r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) |
---|
| 47 | { |
---|
| 48 | SC_METHOD (transition); |
---|
| 49 | dont_initialize(); |
---|
| 50 | sensitive << p_clk.pos(); |
---|
| 51 | SC_METHOD (genMoore); |
---|
| 52 | dont_initialize(); |
---|
| 53 | sensitive << p_clk.neg(); |
---|
| 54 | |
---|
| 55 | assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); |
---|
| 56 | assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); |
---|
| 57 | assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); |
---|
| 58 | assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); |
---|
| 59 | assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); |
---|
| 60 | assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); |
---|
| 61 | assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); |
---|
| 62 | assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); |
---|
| 63 | |
---|
| 64 | } // end constructor |
---|
| 65 | |
---|
| 66 | ///////////////////////// |
---|
| 67 | tmpl(void)::transition() |
---|
| 68 | { |
---|
| 69 | sc_uint<dspin_cmd_width> cmd_fifo_data; |
---|
| 70 | bool cmd_fifo_write; |
---|
| 71 | bool cmd_fifo_read; |
---|
| 72 | |
---|
| 73 | sc_uint<dspin_rsp_width> rsp_fifo_data; |
---|
| 74 | bool rsp_fifo_write; |
---|
| 75 | bool rsp_fifo_read; |
---|
| 76 | |
---|
| 77 | if (p_resetn == false) |
---|
| 78 | { |
---|
| 79 | r_fifo_cmd.init(); |
---|
| 80 | r_fifo_rsp.init(); |
---|
| 81 | r_cmd_fsm = CMD_IDLE; |
---|
| 82 | r_rsp_fsm = RSP_IDLE; |
---|
| 83 | return; |
---|
| 84 | } // end reset |
---|
| 85 | |
---|
| 86 | ///////////////////////////////////////////////////////////// |
---|
| 87 | // VCI command packet to DSPIN command packet |
---|
| 88 | // The VCI packet is analysed, translated, |
---|
| 89 | // and the DSPIN packet is stored in the fifo_cmd |
---|
| 90 | ///////////////////////////////////////////////////////////// |
---|
| 91 | // - A N flits VCI write command packet is translated |
---|
| 92 | // to a N+2 flits DSPIN command. |
---|
| 93 | // - A single flit VCI read command packet is translated |
---|
| 94 | // to a 2 flits DSPIN command. |
---|
| 95 | // - A single flit VCI broadcast packet is translated to |
---|
| 96 | // a 2 flits DSPIN command. |
---|
| 97 | ////////////////////////////////////////////////////////////// |
---|
| 98 | |
---|
| 99 | // cmd_fifo_read |
---|
| 100 | cmd_fifo_read = p_dspin_out.read.read(); |
---|
| 101 | |
---|
| 102 | // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data |
---|
| 103 | switch(r_cmd_fsm) { |
---|
| 104 | case CMD_IDLE: // write first DSPIN flit into fifo_cmd |
---|
| 105 | { |
---|
| 106 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
---|
| 107 | { |
---|
| 108 | cmd_fifo_write = true; |
---|
| 109 | sc_uint<dspin_cmd_width> address = (sc_uint<dspin_cmd_width>)p_vci.address.read(); |
---|
| 110 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
---|
| 111 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
---|
| 112 | if ( address & 0x3 ) // VCI broacast command |
---|
| 113 | { |
---|
| 114 | r_cmd_fsm = CMD_BROADCAST; |
---|
| 115 | cmd_fifo_data = ((address & 0xFFFFF00000) >> 1) | |
---|
| 116 | (srcid << 5) | (trdid << 1) | 0x0000000001; |
---|
| 117 | } |
---|
| 118 | else // VCI READ or WRITE command |
---|
| 119 | { |
---|
| 120 | r_cmd_fsm = CMD_RW; |
---|
| 121 | cmd_fifo_data = (address >> 1) & 0x788888888E; |
---|
| 122 | } |
---|
| 123 | } |
---|
| 124 | else |
---|
| 125 | { |
---|
| 126 | cmd_fifo_write = false; |
---|
| 127 | } |
---|
| 128 | break; |
---|
| 129 | } |
---|
| 130 | case CMD_BROADCAST: // write second DSPIN flit in case of broadcast |
---|
| 131 | { |
---|
| 132 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
---|
| 133 | { |
---|
| 134 | cmd_fifo_write = true; |
---|
| 135 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
---|
| 136 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
---|
| 137 | cmd_fifo_data = (data & 0x00FFFFFFFF) | ((be & 0x3) << 32) | 0x8000000000; |
---|
| 138 | r_cmd_fsm = CMD_IDLE; |
---|
| 139 | } |
---|
| 140 | else |
---|
| 141 | { |
---|
| 142 | cmd_fifo_write = false; |
---|
| 143 | } |
---|
| 144 | break; |
---|
| 145 | } |
---|
| 146 | case CMD_RW: // write second DSPIN flit in case of read/write |
---|
| 147 | { |
---|
| 148 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
---|
| 149 | { |
---|
| 150 | cmd_fifo_write = true; |
---|
| 151 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
---|
| 152 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
---|
| 153 | sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); |
---|
| 154 | sc_uint<dspin_cmd_width> plen = (sc_uint<dspin_cmd_width>)p_vci.plen.read(); |
---|
| 155 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
---|
| 156 | cmd_fifo_data = ((be & 0xF) << 1) | |
---|
| 157 | ((trdid & 0xFF) << 5) | |
---|
| 158 | ((plen & 0xFF) << 13) | |
---|
| 159 | ((cmd & 0x3) << 23) | |
---|
| 160 | ((srcid & 0x3FFF) << 25) | |
---|
| 161 | 0x1000000000; |
---|
| 162 | if( (cmd == vci_param::CMD_READ) || |
---|
| 163 | (cmd == vci_param::CMD_LOCKED_READ) ) r_cmd_fsm = CMD_IDLE; |
---|
| 164 | else r_cmd_fsm = CMD_WDATA; |
---|
| 165 | } |
---|
| 166 | else |
---|
| 167 | { |
---|
| 168 | cmd_fifo_write = false; |
---|
| 169 | } |
---|
| 170 | break; |
---|
| 171 | } |
---|
| 172 | case CMD_WDATA: |
---|
| 173 | { |
---|
| 174 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
---|
| 175 | { |
---|
| 176 | cmd_fifo_write = true; |
---|
| 177 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
---|
| 178 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
---|
| 179 | cmd_fifo_data = (data & 0xFFFFFFFF) | ((be & 0xF) << 32); |
---|
| 180 | if ( p_vci.eop.read() ) |
---|
| 181 | { |
---|
| 182 | cmd_fifo_data = cmd_fifo_data | 0x8000000000; |
---|
| 183 | r_cmd_fsm = CMD_IDLE; |
---|
| 184 | } |
---|
| 185 | } |
---|
| 186 | else |
---|
| 187 | { |
---|
| 188 | cmd_fifo_write = false; |
---|
| 189 | } |
---|
| 190 | break; |
---|
| 191 | } |
---|
| 192 | } // end switch r_cmd_fsm |
---|
| 193 | |
---|
| 194 | // fifo_cmd |
---|
| 195 | if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } |
---|
| 196 | if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } |
---|
| 197 | if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } |
---|
| 198 | |
---|
| 199 | ////////////////////////////////////////////////////////////// |
---|
| 200 | // DSPIN response packet to VCI response packet |
---|
| 201 | // The DSPIN packet is stored in the fifo_rsp |
---|
| 202 | // The FIFO output is analysed and translated to a VCI packet |
---|
| 203 | ////////////////////////////////////////////////////////////// |
---|
| 204 | // - A N+2 flits DSPIN read response packet is translated |
---|
| 205 | // to a N flits VCI response. |
---|
| 206 | // - A single flit DSPIN write response packet is translated |
---|
| 207 | // to a single flit VCI response. |
---|
| 208 | ////////////////////////////////////////////////////////////// |
---|
| 209 | |
---|
| 210 | // rsp_fifo_write, rsp_fifo_data |
---|
| 211 | rsp_fifo_write = p_dspin_in.write.read(); |
---|
| 212 | rsp_fifo_data = p_dspin_in.data.read(); |
---|
| 213 | |
---|
| 214 | // r_rsp_fsm, rsp_fifo_read |
---|
| 215 | switch(r_rsp_fsm) { |
---|
| 216 | case RSP_IDLE: |
---|
| 217 | { |
---|
| 218 | if( r_fifo_rsp.rok() && p_vci.rspack ) |
---|
| 219 | { |
---|
| 220 | rsp_fifo_read = true; |
---|
| 221 | if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) // read response |
---|
| 222 | { |
---|
| 223 | r_rsp_buf = r_fifo_rsp.read(); |
---|
| 224 | r_rsp_fsm = RSP_READ; |
---|
| 225 | } |
---|
| 226 | } |
---|
| 227 | else |
---|
| 228 | { |
---|
| 229 | rsp_fifo_read = false; |
---|
| 230 | } |
---|
| 231 | |
---|
| 232 | break; |
---|
| 233 | } |
---|
| 234 | case RSP_READ: |
---|
| 235 | { |
---|
| 236 | if( r_fifo_rsp.rok() && p_vci.rspack ) |
---|
| 237 | { |
---|
| 238 | rsp_fifo_read = true; |
---|
| 239 | if ( (r_fifo_rsp.read() & 0x100000000) ) r_rsp_fsm = RSP_IDLE; |
---|
| 240 | } |
---|
| 241 | else |
---|
| 242 | { |
---|
| 243 | rsp_fifo_read = false; |
---|
| 244 | } |
---|
| 245 | break; |
---|
| 246 | } |
---|
| 247 | } // end switch r_rsp_fsm |
---|
| 248 | |
---|
| 249 | // fifo_rsp |
---|
| 250 | if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } |
---|
| 251 | if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } |
---|
| 252 | if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } |
---|
| 253 | |
---|
| 254 | }; // end transition |
---|
| 255 | |
---|
| 256 | ////////////////////// |
---|
| 257 | tmpl(void)::genMoore() |
---|
| 258 | { |
---|
| 259 | // VCI CMD interface |
---|
| 260 | if ( r_cmd_fsm.read() == CMD_IDLE ) p_vci.cmdack = false; |
---|
| 261 | else p_vci.cmdack = r_fifo_cmd.wok(); |
---|
| 262 | |
---|
| 263 | // VCI RSP interface |
---|
| 264 | if ( r_rsp_fsm.read() == RSP_IDLE ) |
---|
| 265 | { |
---|
| 266 | if ( r_fifo_rsp.rok() && (r_fifo_rsp.read() & 0x000020000) ) // valid RSP WRITE |
---|
| 267 | { |
---|
| 268 | p_vci.rspval = true; |
---|
| 269 | p_vci.rdata = 0; |
---|
| 270 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_fifo_rsp.read() & 0x0FFFC0000) >> 18); |
---|
| 271 | p_vci.rtrdid = (sc_uint<vci_param::T>)((r_fifo_rsp.read() & 0x00000FF00) >> 8); |
---|
| 272 | p_vci.rpktid = 0; |
---|
| 273 | p_vci.rerror = (sc_uint<vci_param::E>)((r_fifo_rsp.read() & 0x000030000) >> 16); |
---|
| 274 | p_vci.reop = true; |
---|
| 275 | } |
---|
| 276 | else |
---|
| 277 | { |
---|
| 278 | p_vci.rspval = false; |
---|
| 279 | } |
---|
| 280 | } |
---|
| 281 | else // Next flit of a RSP READ |
---|
| 282 | { |
---|
| 283 | if ( r_fifo_rsp.rok() ) // valid RSP READ |
---|
| 284 | { |
---|
| 285 | p_vci.rspval = true; |
---|
| 286 | p_vci.rdata = (sc_uint<4*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); |
---|
| 287 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); |
---|
| 288 | p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); |
---|
| 289 | p_vci.rpktid = 0; |
---|
| 290 | p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); |
---|
| 291 | p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); |
---|
| 292 | } |
---|
| 293 | else |
---|
| 294 | { |
---|
| 295 | p_vci.rspval = false; |
---|
| 296 | } |
---|
| 297 | } |
---|
| 298 | |
---|
| 299 | // DSPIN_OUT interface |
---|
| 300 | p_dspin_out.write = r_fifo_cmd.rok(); |
---|
| 301 | p_dspin_out.data = r_fifo_cmd.read(); |
---|
| 302 | |
---|
| 303 | // DSPIN_IN interface |
---|
| 304 | p_dspin_in.read = r_fifo_rsp.wok(); |
---|
| 305 | |
---|
| 306 | }; // end genMoore |
---|
| 307 | |
---|
| 308 | }} // end namespace |
---|
| 309 | |
---|
| 310 | // Local Variables: |
---|
| 311 | // tab-width: 4 |
---|
| 312 | // c-basic-offset: 4 |
---|
| 313 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 314 | // indent-tabs-mode: nil |
---|
| 315 | // End: |
---|
| 316 | |
---|
| 317 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|