[148] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_vdspin_initiator_wrapper.cpp |
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| 3 | * Copyright (c) UPMC, Lip6 |
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| 4 | * Authors : Alain Greiner |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 7 | * |
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| 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 9 | * |
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| 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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| 13 | * |
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| 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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| 23 | * |
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| 24 | * SOCLIB_LGPL_HEADER_END |
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| 25 | */ |
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| 26 | |
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| 27 | #include "../include/vci_vdspin_initiator_wrapper.h" |
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| 28 | |
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| 29 | namespace soclib { namespace caba { |
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| 30 | |
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| 31 | #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> |
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| 32 | |
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| 33 | //////////////////////////////////////////////////////////://////////////////////////////// |
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| 34 | tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name name, |
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| 35 | size_t cmd_fifo_depth, |
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| 36 | size_t rsp_fifo_depth) |
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| 37 | : soclib::caba::BaseModule(name), |
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| 38 | p_clk("p_clk"), |
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| 39 | p_resetn("p_resetn"), |
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| 40 | p_dspin_out("p_dspin_out"), |
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| 41 | p_dspin_in("p_dspin_in"), |
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| 42 | p_vci("p_vci"), |
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| 43 | r_cmd_fsm("r_cmd_fsm"), |
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| 44 | r_rsp_fsm("r_rsp_fsm"), |
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| 45 | r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), |
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| 46 | r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) |
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| 47 | { |
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| 48 | SC_METHOD (transition); |
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| 49 | dont_initialize(); |
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| 50 | sensitive << p_clk.pos(); |
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| 51 | SC_METHOD (genMoore); |
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| 52 | dont_initialize(); |
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| 53 | sensitive << p_clk.neg(); |
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| 54 | |
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| 55 | assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); |
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| 56 | assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); |
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| 57 | assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); |
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| 58 | assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); |
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| 59 | assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); |
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| 60 | assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); |
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| 61 | assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); |
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| 62 | assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); |
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| 63 | |
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| 64 | } // end constructor |
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| 65 | |
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| 66 | ///////////////////////// |
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| 67 | tmpl(void)::transition() |
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| 68 | { |
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| 69 | sc_uint<dspin_cmd_width> cmd_fifo_data; |
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| 70 | bool cmd_fifo_write; |
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| 71 | bool cmd_fifo_read; |
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| 72 | |
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| 73 | sc_uint<dspin_rsp_width> rsp_fifo_data; |
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| 74 | bool rsp_fifo_write; |
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| 75 | bool rsp_fifo_read; |
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| 76 | |
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| 77 | if (p_resetn == false) |
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| 78 | { |
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| 79 | r_fifo_cmd.init(); |
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| 80 | r_fifo_rsp.init(); |
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| 81 | r_cmd_fsm = CMD_IDLE; |
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| 82 | r_rsp_fsm = RSP_IDLE; |
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| 83 | return; |
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| 84 | } // end reset |
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| 85 | |
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| 86 | ///////////////////////////////////////////////////////////// |
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| 87 | // VCI command packet to DSPIN command packet |
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| 88 | // The VCI packet is analysed, translated, |
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| 89 | // and the DSPIN packet is stored in the fifo_cmd |
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| 90 | ///////////////////////////////////////////////////////////// |
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| 91 | // - A N flits VCI write command packet is translated |
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| 92 | // to a N+2 flits DSPIN command. |
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| 93 | // - A single flit VCI read command packet is translated |
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| 94 | // to a 2 flits DSPIN command. |
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| 95 | // - A single flit VCI broadcast packet is translated to |
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| 96 | // a 2 flits DSPIN command. |
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[150] | 97 | // A DSPIN flit is written in the fifo_cmd in all states |
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| 98 | // but a VCI flit is consumed only in the CMD_READ, |
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| 99 | // CMD_BROACAST, and CMD_WDATA states. |
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[148] | 100 | ////////////////////////////////////////////////////////////// |
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| 101 | |
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| 102 | // cmd_fifo_read |
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| 103 | cmd_fifo_read = p_dspin_out.read.read(); |
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| 104 | |
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| 105 | // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data |
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[150] | 106 | cmd_fifo_write = false; // default value |
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| 107 | |
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[148] | 108 | switch(r_cmd_fsm) { |
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| 109 | case CMD_IDLE: // write first DSPIN flit into fifo_cmd |
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| 110 | { |
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| 111 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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| 112 | { |
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| 113 | cmd_fifo_write = true; |
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| 114 | sc_uint<dspin_cmd_width> address = (sc_uint<dspin_cmd_width>)p_vci.address.read(); |
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| 115 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
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| 116 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
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[150] | 117 | sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); |
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| 118 | |
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| 119 | bool is_broadcast = ( (address & 0x3) != 0); |
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| 120 | bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ)); |
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| 121 | |
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| 122 | if ( vci_param::N == 40 ) address = address >> 1; |
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| 123 | else address = address << (39 - vci_param::N); |
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| 124 | |
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| 125 | if ( is_broadcast ) // VCI broacast command |
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[148] | 126 | { |
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| 127 | r_cmd_fsm = CMD_BROADCAST; |
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[150] | 128 | cmd_fifo_data = (address & 0x7FFFF80000) | |
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| 129 | ((srcid << 5) & 0x000007FFE0) | |
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| 130 | ((trdid << 1) & 0x000000001E) | |
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| 131 | 0x0000000001; |
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[148] | 132 | } |
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[150] | 133 | else if (is_read ) // VCI READ command |
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[148] | 134 | { |
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[150] | 135 | r_cmd_fsm = CMD_READ; |
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| 136 | cmd_fifo_data = address & 0x7FFFFFFFFE; |
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[148] | 137 | } |
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[150] | 138 | else // VCI WRITE command |
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| 139 | { |
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| 140 | r_cmd_fsm = CMD_WRITE; |
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| 141 | cmd_fifo_data = address & 0x7FFFFFFFFE; |
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| 142 | } |
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[148] | 143 | } |
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| 144 | break; |
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| 145 | } |
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| 146 | case CMD_BROADCAST: // write second DSPIN flit in case of broadcast |
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| 147 | { |
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| 148 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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| 149 | { |
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| 150 | cmd_fifo_write = true; |
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| 151 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
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| 152 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[150] | 153 | cmd_fifo_data = (data & 0x00FFFFFFFF) | |
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| 154 | ((be << 32) & 0x0300000000) | |
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| 155 | 0x8000000000; |
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[148] | 156 | r_cmd_fsm = CMD_IDLE; |
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| 157 | } |
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| 158 | break; |
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| 159 | } |
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[150] | 160 | case CMD_READ: // write second DSPIN flit in case of read/write |
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| 161 | case CMD_WRITE: |
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[148] | 162 | { |
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| 163 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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| 164 | { |
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| 165 | cmd_fifo_write = true; |
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| 166 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
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| 167 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
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| 168 | sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); |
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| 169 | sc_uint<dspin_cmd_width> plen = (sc_uint<dspin_cmd_width>)p_vci.plen.read(); |
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| 170 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[150] | 171 | cmd_fifo_data = ((be << 1 ) & 0x000000001E) | |
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| 172 | ((trdid << 5 ) & 0x0000001FE0) | |
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| 173 | ((plen << 13) & 0x00001FE000) | |
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| 174 | ((cmd << 23) & 0x0001800000) | |
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| 175 | ((srcid << 25) & 0x7FFE000000) ; |
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| 176 | if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000 ; |
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| 177 | if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000 ; |
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| 178 | |
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| 179 | if( r_cmd_fsm == CMD_READ ) // read command |
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| 180 | { |
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| 181 | r_cmd_fsm = CMD_IDLE; |
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| 182 | cmd_fifo_data = cmd_fifo_data | 0x8000000000 ; |
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| 183 | } |
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| 184 | else // write command |
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| 185 | { |
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| 186 | r_cmd_fsm = CMD_WDATA; |
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| 187 | } |
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[148] | 188 | } |
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| 189 | break; |
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| 190 | } |
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| 191 | case CMD_WDATA: |
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| 192 | { |
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| 193 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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| 194 | { |
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| 195 | cmd_fifo_write = true; |
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| 196 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
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| 197 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[150] | 198 | cmd_fifo_data = (data & 0x00FFFFFFFF) | |
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| 199 | ((be << 32) & 0x0F00000000) ; |
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| 200 | |
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[148] | 201 | if ( p_vci.eop.read() ) |
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| 202 | { |
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| 203 | cmd_fifo_data = cmd_fifo_data | 0x8000000000; |
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| 204 | r_cmd_fsm = CMD_IDLE; |
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| 205 | } |
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| 206 | } |
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| 207 | break; |
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| 208 | } |
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| 209 | } // end switch r_cmd_fsm |
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| 210 | |
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| 211 | // fifo_cmd |
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| 212 | if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } |
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| 213 | if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } |
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| 214 | if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } |
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| 215 | |
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| 216 | ////////////////////////////////////////////////////////////// |
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| 217 | // DSPIN response packet to VCI response packet |
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| 218 | // The DSPIN packet is stored in the fifo_rsp |
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| 219 | // The FIFO output is analysed and translated to a VCI packet |
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| 220 | ////////////////////////////////////////////////////////////// |
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[150] | 221 | // - A N+1 flits DSPIN read response packet is translated |
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[148] | 222 | // to a N flits VCI response. |
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| 223 | // - A single flit DSPIN write response packet is translated |
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| 224 | // to a single flit VCI response. |
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[150] | 225 | // A valid DSPIN flit in the fifo_rsp is always consumed |
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| 226 | // in the CMD_IDLE state, but no VCI flit is transmitted. |
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| 227 | // The VCI flits are sent in the RSP_READ & RSP_WRITE states. |
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[148] | 228 | ////////////////////////////////////////////////////////////// |
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| 229 | |
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| 230 | // rsp_fifo_write, rsp_fifo_data |
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| 231 | rsp_fifo_write = p_dspin_in.write.read(); |
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| 232 | rsp_fifo_data = p_dspin_in.data.read(); |
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| 233 | |
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| 234 | // r_rsp_fsm, rsp_fifo_read |
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[150] | 235 | rsp_fifo_read = false; // default value |
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| 236 | |
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[148] | 237 | switch(r_rsp_fsm) { |
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| 238 | case RSP_IDLE: |
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| 239 | { |
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[150] | 240 | if( r_fifo_rsp.rok() ) |
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[148] | 241 | { |
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| 242 | rsp_fifo_read = true; |
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[150] | 243 | r_rsp_buf = r_fifo_rsp.read(); |
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| 244 | if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) r_rsp_fsm = RSP_READ; |
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| 245 | else r_rsp_fsm = RSP_WRITE; |
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[148] | 246 | } |
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| 247 | break; |
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| 248 | } |
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| 249 | case RSP_READ: |
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| 250 | { |
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[150] | 251 | if( r_fifo_rsp.rok() && p_vci.rspack.read() ) |
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[148] | 252 | { |
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| 253 | rsp_fifo_read = true; |
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| 254 | if ( (r_fifo_rsp.read() & 0x100000000) ) r_rsp_fsm = RSP_IDLE; |
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| 255 | } |
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| 256 | break; |
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| 257 | } |
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[150] | 258 | case RSP_WRITE: |
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| 259 | { |
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| 260 | if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE; |
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| 261 | } |
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[148] | 262 | } // end switch r_rsp_fsm |
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| 263 | |
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| 264 | // fifo_rsp |
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| 265 | if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } |
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| 266 | if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } |
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| 267 | if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } |
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| 268 | |
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| 269 | }; // end transition |
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| 270 | |
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| 271 | ////////////////////// |
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| 272 | tmpl(void)::genMoore() |
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| 273 | { |
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| 274 | // VCI CMD interface |
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[150] | 275 | if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) |
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| 276 | { |
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| 277 | p_vci.cmdack = false; |
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| 278 | } |
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| 279 | else |
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| 280 | { |
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| 281 | p_vci.cmdack = r_fifo_cmd.wok(); |
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| 282 | } |
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[148] | 283 | |
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| 284 | // VCI RSP interface |
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| 285 | if ( r_rsp_fsm.read() == RSP_IDLE ) |
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| 286 | { |
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[150] | 287 | p_vci.rspval = false; |
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[148] | 288 | } |
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[150] | 289 | else if ( r_rsp_fsm.read() == RSP_WRITE ) |
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| 290 | { |
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| 291 | p_vci.rspval = true; |
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| 292 | p_vci.rdata = 0; |
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| 293 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); |
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| 294 | p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); |
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| 295 | p_vci.rpktid = 0; |
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| 296 | p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); |
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| 297 | p_vci.reop = true; |
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| 298 | } |
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| 299 | else if ( r_rsp_fsm.read() == RSP_READ ) |
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| 300 | { |
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| 301 | p_vci.rspval = true; |
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| 302 | p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); |
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| 303 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); |
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| 304 | p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8); |
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| 305 | p_vci.rpktid = 0; |
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| 306 | p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16); |
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| 307 | p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); |
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| 308 | } |
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[148] | 309 | |
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| 310 | // DSPIN_OUT interface |
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| 311 | p_dspin_out.write = r_fifo_cmd.rok(); |
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| 312 | p_dspin_out.data = r_fifo_cmd.read(); |
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| 313 | |
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| 314 | // DSPIN_IN interface |
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| 315 | p_dspin_in.read = r_fifo_rsp.wok(); |
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| 316 | |
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| 317 | }; // end genMoore |
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| 318 | |
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[150] | 319 | ///////////////////////// |
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| 320 | tmpl(void)::print_trace() |
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| 321 | { |
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| 322 | const char* cmd_str[] = { |
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| 323 | "CMD_IDLE ", |
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| 324 | "CMD_BROADCAST", |
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| 325 | "CMD_READ ", |
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| 326 | "CMD_WRITE ", |
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| 327 | "CMD_WDATA ", |
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| 328 | }; |
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| 329 | const char* rsp_str[] = { |
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| 330 | "RSP_IDLE ", |
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| 331 | "RSP_READ ", |
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| 332 | "RSP_WRITE ", |
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| 333 | }; |
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| 334 | |
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| 335 | std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()] |
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| 336 | << " | " << rsp_str[r_rsp_fsm.read()] |
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| 337 | << " | fifo_cmd = " << r_fifo_cmd.filled_status() |
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| 338 | << " | fifo_rsp = " << r_fifo_rsp.filled_status() |
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| 339 | << std::endl; |
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| 340 | } |
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| 341 | |
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[148] | 342 | }} // end namespace |
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| 343 | |
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| 344 | // Local Variables: |
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| 345 | // tab-width: 4 |
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| 346 | // c-basic-offset: 4 |
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| 347 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 348 | // indent-tabs-mode: nil |
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| 349 | // End: |
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| 350 | |
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| 351 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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