[148] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_vdspin_initiator_wrapper.cpp |
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| 3 | * Copyright (c) UPMC, Lip6 |
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| 4 | * Authors : Alain Greiner |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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[284] | 7 | * |
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[148] | 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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[284] | 9 | * |
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[148] | 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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[284] | 13 | * |
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[148] | 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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[284] | 18 | * |
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[148] | 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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[284] | 23 | * |
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[148] | 24 | * SOCLIB_LGPL_HEADER_END |
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[287] | 25 | * |
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| 26 | * Maintainers: alexandre.joannou@lip6.fr |
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| 27 | * |
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[148] | 28 | */ |
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| 29 | |
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| 30 | #include "../include/vci_vdspin_initiator_wrapper.h" |
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| 31 | |
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| 32 | namespace soclib { namespace caba { |
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| 33 | |
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| 34 | #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> |
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| 35 | |
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[287] | 36 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 37 | tmpl(/**/)::VciVdspinInitiatorWrapper( sc_module_name name, |
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| 38 | size_t cmd_fifo_depth, |
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| 39 | size_t rsp_fifo_depth ) |
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| 40 | : soclib::caba::BaseModule(name), |
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| 41 | p_clk("p_clk"), |
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| 42 | p_resetn("p_resetn"), |
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| 43 | p_dspin_out("p_dspin_out"), |
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| 44 | p_dspin_in("p_dspin_in"), |
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| 45 | p_vci("p_vci"), |
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| 46 | r_cmd_fsm("r_cmd_fsm"), |
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| 47 | r_rsp_fsm("r_rsp_fsm"), |
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| 48 | r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), |
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| 49 | r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) |
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[284] | 50 | { |
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| 51 | SC_METHOD (transition); |
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| 52 | dont_initialize(); |
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| 53 | sensitive << p_clk.pos(); |
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[287] | 54 | |
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[284] | 55 | SC_METHOD (genMoore); |
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| 56 | dont_initialize(); |
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| 57 | sensitive << p_clk.neg(); |
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[148] | 58 | |
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[284] | 59 | assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); |
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| 60 | assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); |
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| 61 | assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); |
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[287] | 62 | assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); |
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| 63 | assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); |
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| 64 | assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); |
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| 65 | assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); |
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| 66 | assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); |
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| 67 | assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); |
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[148] | 68 | |
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[284] | 69 | } // end constructor |
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[148] | 70 | |
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| 71 | ///////////////////////// |
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| 72 | tmpl(void)::transition() |
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| 73 | { |
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[284] | 74 | sc_uint<dspin_cmd_width> cmd_fifo_data; |
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[287] | 75 | bool cmd_fifo_write; |
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| 76 | bool cmd_fifo_read; |
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[148] | 77 | |
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[284] | 78 | sc_uint<dspin_rsp_width> rsp_fifo_data; |
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[287] | 79 | bool rsp_fifo_write; |
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| 80 | bool rsp_fifo_read; |
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[148] | 81 | |
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[284] | 82 | if (p_resetn == false) |
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[287] | 83 | { |
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[284] | 84 | r_fifo_cmd.init(); |
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| 85 | r_fifo_rsp.init(); |
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| 86 | r_cmd_fsm = CMD_IDLE; |
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| 87 | r_rsp_fsm = RSP_IDLE; |
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| 88 | return; |
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| 89 | } // end reset |
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[148] | 90 | |
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[284] | 91 | ///////////////////////////////////////////////////////////// |
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| 92 | // VCI command packet to DSPIN command packet |
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| 93 | // The VCI packet is analysed, translated, |
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| 94 | // and the DSPIN packet is stored in the fifo_cmd |
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| 95 | ///////////////////////////////////////////////////////////// |
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| 96 | // - A N flits VCI write command packet is translated |
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| 97 | // to a N+2 flits DSPIN command. |
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| 98 | // - A single flit VCI read command packet is translated |
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| 99 | // to a 2 flits DSPIN command. |
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| 100 | // - A single flit VCI broadcast packet is translated to |
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| 101 | // a 2 flits DSPIN command. |
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| 102 | // A DSPIN flit is written in the fifo_cmd in all states |
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| 103 | // but a VCI flit is consumed only in the CMD_READ, |
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| 104 | // CMD_BROACAST, and CMD_WDATA states. |
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| 105 | ////////////////////////////////////////////////////////////// |
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[148] | 106 | |
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[284] | 107 | // cmd_fifo_read |
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| 108 | cmd_fifo_read = p_dspin_out.read.read(); |
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[148] | 109 | |
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[284] | 110 | // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data |
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| 111 | cmd_fifo_write = false; // default value |
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[150] | 112 | |
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[284] | 113 | switch(r_cmd_fsm) { |
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| 114 | case CMD_IDLE: // write first DSPIN flit into fifo_cmd |
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[148] | 115 | { |
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[284] | 116 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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[148] | 117 | { |
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[284] | 118 | cmd_fifo_write = true; |
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[148] | 119 | sc_uint<dspin_cmd_width> address = (sc_uint<dspin_cmd_width>)p_vci.address.read(); |
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| 120 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
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| 121 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
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[150] | 122 | sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); |
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| 123 | |
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| 124 | bool is_broadcast = ( (address & 0x3) != 0); |
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| 125 | bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ)); |
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| 126 | |
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| 127 | if ( vci_param::N == 40 ) address = address >> 1; |
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[284] | 128 | else address = address << (39 - vci_param::N); |
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[150] | 129 | |
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[287] | 130 | if ( is_broadcast ) // VCI broacast command |
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[148] | 131 | { |
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| 132 | r_cmd_fsm = CMD_BROADCAST; |
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[186] | 133 | cmd_fifo_data = (address & 0x7FFFF80000LL) | |
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[284] | 134 | ((srcid << 5) & 0x000007FFE0LL) | |
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| 135 | ((trdid << 1) & 0x000000001ELL) | |
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| 136 | 0x0000000001LL; |
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[148] | 137 | } |
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[287] | 138 | else if (is_read ) // VCI READ command |
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[148] | 139 | { |
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[284] | 140 | r_cmd_fsm = CMD_READ; |
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[186] | 141 | cmd_fifo_data = address & 0x7FFFFFFFFELL; |
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[284] | 142 | } |
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[287] | 143 | else // VCI WRITE command |
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[150] | 144 | { |
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[284] | 145 | r_cmd_fsm = CMD_WRITE; |
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[186] | 146 | cmd_fifo_data = address & 0x7FFFFFFFFELL; |
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[284] | 147 | } |
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| 148 | } |
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| 149 | break; |
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| 150 | } |
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[287] | 151 | case CMD_BROADCAST: // write second DSPIN flit in case of broadcast |
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[284] | 152 | { |
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| 153 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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[148] | 154 | { |
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| 155 | cmd_fifo_write = true; |
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| 156 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
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| 157 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[284] | 158 | cmd_fifo_data = (data & 0x00FFFFFFFFLL) | |
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[186] | 159 | ((be << 32) & 0x0300000000LL) | |
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[284] | 160 | 0x8000000000LL; |
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[148] | 161 | r_cmd_fsm = CMD_IDLE; |
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| 162 | } |
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| 163 | break; |
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| 164 | } |
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[287] | 165 | case CMD_READ: // write second DSPIN flit in case of read/write |
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[150] | 166 | case CMD_WRITE: |
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[148] | 167 | { |
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[284] | 168 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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[148] | 169 | { |
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[284] | 170 | cmd_fifo_write = true; |
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[148] | 171 | sc_uint<dspin_cmd_width> srcid = (sc_uint<dspin_cmd_width>)p_vci.srcid.read(); |
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[284] | 172 | sc_uint<dspin_cmd_width> pktid = (sc_uint<dspin_cmd_width>)p_vci.pktid.read(); |
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[148] | 173 | sc_uint<dspin_cmd_width> trdid = (sc_uint<dspin_cmd_width>)p_vci.trdid.read(); |
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| 174 | sc_uint<dspin_cmd_width> cmd = (sc_uint<dspin_cmd_width>)p_vci.cmd.read(); |
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| 175 | sc_uint<dspin_cmd_width> plen = (sc_uint<dspin_cmd_width>)p_vci.plen.read(); |
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| 176 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[284] | 177 | cmd_fifo_data = ((be << 1 ) & 0x000000001ELL) | |
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| 178 | ((pktid << 5 ) & 0x00000001E0LL) | |
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| 179 | ((trdid << 9 ) & 0x0000001E00LL) | |
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| 180 | ((plen << 13) & 0x00001FE000LL) | |
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| 181 | ((cmd << 23) & 0x0001800000LL) | |
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| 182 | ((srcid << 25) & 0x7FFE000000LL) ; |
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[186] | 183 | if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000LL ; |
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| 184 | if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000LL ; |
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[150] | 185 | |
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[287] | 186 | if( r_cmd_fsm == CMD_READ ) // read command |
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[150] | 187 | { |
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| 188 | r_cmd_fsm = CMD_IDLE; |
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[186] | 189 | cmd_fifo_data = cmd_fifo_data | 0x8000000000LL ; |
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[150] | 190 | } |
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[287] | 191 | else // write command |
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[150] | 192 | { |
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| 193 | r_cmd_fsm = CMD_WDATA; |
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| 194 | } |
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[284] | 195 | } |
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| 196 | break; |
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[148] | 197 | } |
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[284] | 198 | case CMD_WDATA: |
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[148] | 199 | { |
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[284] | 200 | if( p_vci.cmdval && r_fifo_cmd.wok() ) |
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[148] | 201 | { |
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[284] | 202 | cmd_fifo_write = true; |
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[148] | 203 | sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read(); |
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| 204 | sc_uint<dspin_cmd_width> be = (sc_uint<dspin_cmd_width>)p_vci.be.read(); |
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[284] | 205 | cmd_fifo_data = (data & 0x00FFFFFFFFLL) | |
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| 206 | ((be << 32) & 0x0F00000000LL) ; |
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| 207 | |
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[148] | 208 | if ( p_vci.eop.read() ) |
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| 209 | { |
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[186] | 210 | cmd_fifo_data = cmd_fifo_data | 0x8000000000LL; |
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[148] | 211 | r_cmd_fsm = CMD_IDLE; |
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| 212 | } |
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[284] | 213 | } |
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[148] | 214 | break; |
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| 215 | } |
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[284] | 216 | } // end switch r_cmd_fsm |
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[148] | 217 | |
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[284] | 218 | // fifo_cmd |
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| 219 | if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } |
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| 220 | if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } |
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| 221 | if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } |
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[148] | 222 | |
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[284] | 223 | ////////////////////////////////////////////////////////////// |
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| 224 | // DSPIN response packet to VCI response packet |
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| 225 | // The DSPIN packet is stored in the fifo_rsp |
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| 226 | // The FIFO output is analysed and translated to a VCI packet |
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| 227 | ////////////////////////////////////////////////////////////// |
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[287] | 228 | // - A N+1 flits DSPIN response packet is translated |
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[284] | 229 | // to a N flits VCI response. |
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[287] | 230 | // - A single flit DSPIN response packet is translated |
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| 231 | // to a single flit VCI response with RDATA = 0. |
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[284] | 232 | // A valid DSPIN flit in the fifo_rsp is always consumed |
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| 233 | // in the CMD_IDLE state, but no VCI flit is transmitted. |
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[287] | 234 | // The VCI flits are sent in the RSP_DSPIN_SINGLE_FLIT & |
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| 235 | // RSP_DSPIN_MULTI_FLIT states. |
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[284] | 236 | ////////////////////////////////////////////////////////////// |
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[148] | 237 | |
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[284] | 238 | // rsp_fifo_write, rsp_fifo_data |
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| 239 | rsp_fifo_write = p_dspin_in.write.read(); |
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| 240 | rsp_fifo_data = p_dspin_in.data.read(); |
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[150] | 241 | |
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[284] | 242 | // r_rsp_fsm, rsp_fifo_read |
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[287] | 243 | rsp_fifo_read = false; // default value |
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[284] | 244 | |
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[287] | 245 | switch(r_rsp_fsm) |
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| 246 | { |
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[284] | 247 | case RSP_IDLE: |
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[287] | 248 | { |
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| 249 | if( r_fifo_rsp.rok() ) |
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[148] | 250 | { |
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[287] | 251 | rsp_fifo_read = true; |
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| 252 | r_rsp_buf = r_fifo_rsp.read(); |
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| 253 | if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) |
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| 254 | r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; |
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| 255 | else |
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| 256 | r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; |
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| 257 | } |
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| 258 | break; |
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[284] | 259 | } |
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[287] | 260 | case RSP_DSPIN_SINGLE_FLIT: |
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[284] | 261 | { |
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[287] | 262 | if ( p_vci.rspack.read() ) |
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| 263 | r_rsp_fsm = RSP_IDLE; |
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| 264 | break; |
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[284] | 265 | } |
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[287] | 266 | case RSP_DSPIN_MULTI_FLIT: |
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| 267 | { |
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| 268 | if( r_fifo_rsp.rok() && p_vci.rspack.read() ) |
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[150] | 269 | { |
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[287] | 270 | rsp_fifo_read = true; |
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| 271 | if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) |
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| 272 | r_rsp_fsm = RSP_IDLE; |
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[150] | 273 | } |
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[287] | 274 | break; |
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| 275 | } |
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[284] | 276 | } // end switch r_rsp_fsm |
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[148] | 277 | |
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[284] | 278 | // fifo_rsp |
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| 279 | if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } |
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| 280 | if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } |
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| 281 | if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } |
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[148] | 282 | |
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| 283 | }; // end transition |
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| 284 | |
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| 285 | ////////////////////// |
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| 286 | tmpl(void)::genMoore() |
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| 287 | { |
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[284] | 288 | // VCI CMD interface |
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[287] | 289 | if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) |
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| 290 | { |
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| 291 | p_vci.cmdack = false; |
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| 292 | } |
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[284] | 293 | else |
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[287] | 294 | { |
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| 295 | p_vci.cmdack = r_fifo_cmd.wok(); |
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| 296 | } |
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[148] | 297 | |
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[284] | 298 | // VCI RSP interface |
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| 299 | if ( r_rsp_fsm.read() == RSP_IDLE ) |
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[287] | 300 | { |
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| 301 | p_vci.rspval = false; |
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| 302 | } |
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| 303 | else if ( r_rsp_fsm.read() == RSP_DSPIN_SINGLE_FLIT ) |
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| 304 | { |
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| 305 | p_vci.rspval = true; |
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| 306 | p_vci.rdata = 0; |
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| 307 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); |
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| 308 | p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8); |
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| 309 | p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12); |
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| 310 | p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16); |
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| 311 | p_vci.reop = true; |
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| 312 | } |
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| 313 | else if ( r_rsp_fsm.read() == RSP_DSPIN_MULTI_FLIT ) |
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| 314 | { |
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| 315 | p_vci.rspval = r_fifo_rsp.rok(); |
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| 316 | p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL); |
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| 317 | p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); |
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| 318 | p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8); |
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| 319 | p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12); |
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| 320 | p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16); |
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| 321 | p_vci.reop = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL); |
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| 322 | } |
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[148] | 323 | |
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[287] | 324 | // DSPIN_OUT interface |
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| 325 | p_dspin_out.write = r_fifo_cmd.rok(); |
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| 326 | p_dspin_out.data = r_fifo_cmd.read(); |
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[148] | 327 | |
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[287] | 328 | // DSPIN_IN interface |
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| 329 | p_dspin_in.read = r_fifo_rsp.wok(); |
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[148] | 330 | |
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| 331 | }; // end genMoore |
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| 332 | |
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[150] | 333 | ///////////////////////// |
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| 334 | tmpl(void)::print_trace() |
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| 335 | { |
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| 336 | const char* cmd_str[] = { |
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| 337 | "CMD_IDLE ", |
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| 338 | "CMD_BROADCAST", |
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| 339 | "CMD_READ ", |
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| 340 | "CMD_WRITE ", |
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| 341 | "CMD_WDATA ", |
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| 342 | }; |
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| 343 | const char* rsp_str[] = { |
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[287] | 344 | "RSP_IDLE ", |
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| 345 | "RSP_DSPIN_SINGLE_FLIT", |
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| 346 | "RSP_DSPIN_MULTI_FLIT ", |
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[150] | 347 | }; |
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| 348 | |
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| 349 | std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()] |
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[284] | 350 | << " | " << rsp_str[r_rsp_fsm.read()] |
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[150] | 351 | << " | fifo_cmd = " << r_fifo_cmd.filled_status() |
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| 352 | << " | fifo_rsp = " << r_fifo_rsp.filled_status() |
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| 353 | << std::endl; |
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| 354 | } |
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| 355 | |
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[148] | 356 | }} // end namespace |
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| 357 | |
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| 358 | // Local Variables: |
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| 359 | // tab-width: 4 |
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| 360 | // c-basic-offset: 4 |
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| 361 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 362 | // indent-tabs-mode: nil |
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| 363 | // End: |
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| 364 | |
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| 365 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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