[148] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_vdspin_target_wrapper.cpp |
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| 3 | * Copyright (c) UPMC, Lip6 |
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| 4 | * Author : Alain Greiner |
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| 5 | * |
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| 6 | * SOCLIB_LGPL_HEADER_BEGIN |
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[284] | 7 | * |
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[148] | 8 | * This file is part of SoCLib, GNU LGPLv2.1. |
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[284] | 9 | * |
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[148] | 10 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU Lesser General Public License as published |
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| 12 | * by the Free Software Foundation; version 2.1 of the License. |
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[284] | 13 | * |
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[148] | 14 | * SoCLib is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * Lesser General Public License for more details. |
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[284] | 18 | * |
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[148] | 19 | * You should have received a copy of the GNU Lesser General Public |
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| 20 | * License along with SoCLib; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 22 | * 02110-1301 USA |
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[284] | 23 | * |
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[148] | 24 | * SOCLIB_LGPL_HEADER_END |
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[287] | 25 | * |
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| 26 | * Maintainers: alexandre.joannou@lip6.fr |
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| 27 | * |
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[148] | 28 | */ |
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| 29 | |
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| 30 | #include "../include/vci_vdspin_target_wrapper.h" |
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| 31 | |
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[185] | 32 | using namespace soclib::common; |
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| 33 | |
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[148] | 34 | namespace soclib { namespace caba { |
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| 35 | |
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| 36 | #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> |
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| 37 | |
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[287] | 38 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | tmpl(/**/)::VciVdspinTargetWrapper( sc_module_name name, |
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| 40 | size_t cmd_fifo_depth, |
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| 41 | size_t rsp_fifo_depth ) |
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| 42 | : soclib::caba::BaseModule(name), |
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| 43 | p_clk("p_clk"), |
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| 44 | p_resetn("p_resetn"), |
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| 45 | p_dspin_out("p_dspin_out"), |
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| 46 | p_dspin_in("p_dspin_in"), |
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| 47 | p_vci("p_vci"), |
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| 48 | r_cmd_fsm("r_cmd_fsm"), |
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| 49 | r_rsp_fsm("r_rsp_fsm"), |
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| 50 | r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), |
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| 51 | r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) |
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| 52 | { |
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[284] | 53 | SC_METHOD (transition); |
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| 54 | dont_initialize(); |
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| 55 | sensitive << p_clk.pos(); |
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[287] | 56 | |
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[284] | 57 | SC_METHOD (genMoore); |
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| 58 | dont_initialize(); |
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| 59 | sensitive << p_clk.neg(); |
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[148] | 60 | |
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[287] | 61 | assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); |
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| 62 | assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); |
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| 63 | assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); |
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| 64 | assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); |
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| 65 | assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); |
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| 66 | assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); |
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| 67 | assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); |
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| 68 | assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); |
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| 69 | assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); |
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[148] | 70 | |
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[287] | 71 | } // end constructor |
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[148] | 72 | |
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| 73 | ///////////////////////// |
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| 74 | tmpl(void)::transition() |
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| 75 | { |
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[287] | 76 | sc_uint<dspin_cmd_width> cmd_fifo_data; |
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| 77 | bool cmd_fifo_write; |
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| 78 | bool cmd_fifo_read; |
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[148] | 79 | |
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[287] | 80 | sc_uint<dspin_rsp_width> rsp_fifo_data; |
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| 81 | bool rsp_fifo_write; |
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| 82 | bool rsp_fifo_read; |
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[148] | 83 | |
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[284] | 84 | if (p_resetn == false) |
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[287] | 85 | { |
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[284] | 86 | r_fifo_cmd.init(); |
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| 87 | r_fifo_rsp.init(); |
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| 88 | r_cmd_fsm = CMD_IDLE; |
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| 89 | r_rsp_fsm = RSP_IDLE; |
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| 90 | return; |
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| 91 | } // end reset |
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[148] | 92 | |
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[284] | 93 | ///////////////////////////////////////////////////////////// |
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| 94 | // VCI response packet to DSPIN response packet. |
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| 95 | // The VCI packet is analysed, translated, |
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| 96 | // and the DSPIN packet is stored in the fifo_rsp |
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| 97 | ///////////////////////////////////////////////////////////// |
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[287] | 98 | // - A single flit VCI response packet with a 0 RDATA value |
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| 99 | // is translated to a single flit DSPIN response. |
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| 100 | // - All other VCI responses are translated to a multi-flit |
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| 101 | // DSPIN response. |
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[284] | 102 | // In the RSP_IDLE state, the first DSPIN flit is written |
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| 103 | // in fifo_rsp , but no VCI flit is consumed. The VCI flits |
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[287] | 104 | // are consumed in the RSP_DSPIN_SINGLE_FLIT, or the |
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| 105 | // SP_DSPIN_MULTI_FLIT states. |
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[284] | 106 | ////////////////////////////////////////////////////////////// |
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[148] | 107 | |
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[284] | 108 | // rsp_fifo_read |
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| 109 | rsp_fifo_read = p_dspin_out.read.read(); |
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[148] | 110 | |
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[284] | 111 | // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data |
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[287] | 112 | rsp_fifo_write = false; // default value |
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[149] | 113 | |
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[287] | 114 | switch(r_rsp_fsm) |
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| 115 | { |
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[284] | 116 | case RSP_IDLE: // write first DSPIN flit into rsp_fifo |
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[287] | 117 | { |
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| 118 | if( p_vci.rspval.read() && r_fifo_rsp.wok() ) |
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[148] | 119 | { |
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[287] | 120 | bool is_single_flit = ( p_vci.reop.read() && ( p_vci.rdata.read() == 0) ); |
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| 121 | |
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| 122 | rsp_fifo_write = true; |
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| 123 | rsp_fifo_data = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) | |
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| 124 | (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) | |
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| 125 | (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 12) | |
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| 126 | (((sc_uint<dspin_rsp_width>)p_vci.rpktid.read()) << 8); |
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| 127 | if ( is_single_flit ) |
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[148] | 128 | { |
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[287] | 129 | rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 |
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| 130 | rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 |
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| 131 | r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; |
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[284] | 132 | } |
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[287] | 133 | else |
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| 134 | { |
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| 135 | rsp_fifo_data = rsp_fifo_data & 0x0FFFFFFFFLL; // EOP = 0 |
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| 136 | rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 |
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| 137 | r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; |
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| 138 | } |
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[148] | 139 | } |
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[287] | 140 | break; |
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| 141 | } |
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| 142 | case RSP_DSPIN_SINGLE_FLIT: |
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| 143 | { |
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| 144 | rsp_fifo_write = false; |
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| 145 | if ( r_fifo_rsp.wok() ) |
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| 146 | r_rsp_fsm = RSP_IDLE; |
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| 147 | break; |
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| 148 | } |
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| 149 | case RSP_DSPIN_MULTI_FLIT: // write DSPIN data flit |
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| 150 | { |
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| 151 | if( p_vci.rspval && r_fifo_rsp.wok() ) |
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[284] | 152 | { |
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[287] | 153 | rsp_fifo_write = true; |
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| 154 | rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read()); |
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| 155 | if ( p_vci.reop ) |
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[148] | 156 | { |
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[287] | 157 | rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 |
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| 158 | r_rsp_fsm = RSP_IDLE; |
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[148] | 159 | } |
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| 160 | } |
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[287] | 161 | break; |
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| 162 | } |
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[284] | 163 | } // end switch r_cmd_fsm |
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[148] | 164 | |
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[284] | 165 | // fifo_rsp |
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| 166 | if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } |
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| 167 | if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } |
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| 168 | if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } |
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| 169 | |
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[287] | 170 | ////////////////////////////////////////////////////////////// |
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[284] | 171 | // DSPIN command packet to VCI command packet |
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[287] | 172 | // The DSPIN packet is stored in the fifo_cmd |
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[284] | 173 | // The FIFO output is analysed and translated to a VCI packet |
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[287] | 174 | ////////////////////////////////////////////////////////////// |
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| 175 | // - A 2 flits DSPIN broadcast command is translated |
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| 176 | // to a 1 flit VCI broadcast command. |
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| 177 | // - A 2 flits DSPIN read command is translated |
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| 178 | // to a 1 flit VCI read command. |
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| 179 | // - A N+2 flits DSPIN write command is translated |
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| 180 | // to a N flits VCI write command. |
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| 181 | // The VCI flits are sent in the CMD_READ, CMD_WDATA |
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| 182 | // & CMD_BROADCAST states. |
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| 183 | // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store |
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| 184 | // the two first DSPIN flits (in case of write). |
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| 185 | ////////////////////////////////////////////////////////////// |
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[148] | 186 | |
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[284] | 187 | // cmd_fifo_write, cmd_fifo_data |
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| 188 | cmd_fifo_write = p_dspin_in.write.read(); |
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| 189 | cmd_fifo_data = p_dspin_in.data.read(); |
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[148] | 190 | |
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[284] | 191 | // r_cmd_fsm, cmd_fifo_read |
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[287] | 192 | cmd_fifo_read = false; // default value |
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[149] | 193 | |
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[287] | 194 | switch(r_cmd_fsm) |
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| 195 | { |
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[284] | 196 | case CMD_IDLE: |
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[287] | 197 | { |
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| 198 | if( r_fifo_cmd.rok() ) |
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[148] | 199 | { |
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[287] | 200 | bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); |
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[148] | 201 | |
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[287] | 202 | cmd_fifo_read = true; |
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| 203 | r_cmd_buf0 = r_fifo_cmd.read(); // save address |
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| 204 | |
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| 205 | if ( is_broadcast ) |
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| 206 | r_cmd_fsm = CMD_BROADCAST; |
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| 207 | else |
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| 208 | r_cmd_fsm = CMD_RW; |
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| 209 | } |
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| 210 | break; |
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[284] | 211 | } |
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| 212 | case CMD_BROADCAST: |
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| 213 | { |
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[287] | 214 | if( r_fifo_cmd.rok() && p_vci.cmdack ) |
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| 215 | { |
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| 216 | cmd_fifo_read = true; |
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| 217 | r_cmd_fsm = CMD_IDLE; |
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[148] | 218 | } |
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[287] | 219 | break; |
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| 220 | } |
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| 221 | case CMD_RW: |
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| 222 | { |
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| 223 | if( r_fifo_cmd.rok() ) |
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[148] | 224 | { |
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[287] | 225 | cmd_fifo_read = true; |
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| 226 | r_cmd_buf1 = r_fifo_cmd.read(); // save command parameters |
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| 227 | // read command if EOP |
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| 228 | if ( (r_fifo_cmd.read() & 0x8000000000LL) ) |
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| 229 | r_cmd_fsm = CMD_READ; |
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| 230 | else |
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| 231 | r_cmd_fsm = CMD_WDATA; |
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| 232 | r_flit_count = 0; |
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| 233 | } |
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| 234 | break; |
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[284] | 235 | } |
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[287] | 236 | case CMD_READ: |
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| 237 | { |
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| 238 | if ( p_vci.cmdack.read() ) |
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| 239 | r_cmd_fsm = CMD_IDLE; |
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| 240 | break; |
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| 241 | } |
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| 242 | case CMD_WDATA: |
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| 243 | { |
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| 244 | if( r_fifo_cmd.rok() && p_vci.cmdack.read() ) |
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[149] | 245 | { |
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[287] | 246 | if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 ) |
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| 247 | r_flit_count = r_flit_count + 1; |
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| 248 | cmd_fifo_read = true; |
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| 249 | if ( (r_fifo_cmd.read() & 0x8000000000LL) ) |
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| 250 | r_cmd_fsm = CMD_IDLE; |
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[149] | 251 | } |
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[287] | 252 | break; |
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[284] | 253 | } |
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| 254 | } // end switch r_cmd_fsm |
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[148] | 255 | |
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[284] | 256 | // fifo_cmd |
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| 257 | if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } |
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| 258 | if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } |
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| 259 | if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } |
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[148] | 260 | |
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| 261 | }; // end transition |
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| 262 | |
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| 263 | ////////////////////// |
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| 264 | tmpl(void)::genMoore() |
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| 265 | { |
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[284] | 266 | // VCI RSP interface |
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[287] | 267 | if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; |
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| 268 | else p_vci.rspack = r_fifo_rsp.wok(); |
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[148] | 269 | |
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[284] | 270 | // VCI CMD interface |
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| 271 | if ( (r_cmd_fsm.read() == CMD_IDLE) || (r_cmd_fsm.read() == CMD_RW) ) |
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[287] | 272 | { |
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| 273 | p_vci.cmdval = false; |
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| 274 | } |
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| 275 | else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast |
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| 276 | { |
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| 277 | if ( r_fifo_cmd.rok() ) |
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[148] | 278 | { |
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[287] | 279 | sc_uint<dspin_cmd_width> minmax = r_cmd_buf0.read() & 0x7FFFF80000LL; |
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| 280 | if ( vci_param::N == 40 ) minmax = (minmax << 1); |
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| 281 | else minmax = (minmax >> (39 - vci_param::N) ); |
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| 282 | p_vci.cmdval = true; |
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| 283 | p_vci.address = (sc_uint<vci_param::N>)minmax | 0x3; |
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| 284 | p_vci.cmd = vci_param::CMD_WRITE; |
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| 285 | p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); |
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| 286 | p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); |
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| 287 | p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf0.read() & 0x000007FFE0LL) >> 5); |
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| 288 | p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf0.read() & 0x000000001ELL) >> 1); |
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| 289 | p_vci.pktid = 0; |
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| 290 | p_vci.plen = vci_param::B; |
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| 291 | p_vci.contig = true; |
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| 292 | p_vci.cons = false; |
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| 293 | p_vci.eop = true; |
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[148] | 294 | } |
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[287] | 295 | else |
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[148] | 296 | { |
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[287] | 297 | p_vci.cmdval = false; |
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[148] | 298 | } |
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[287] | 299 | } |
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| 300 | else if ( r_cmd_fsm.read() == CMD_READ ) // VCI CMD read |
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| 301 | { |
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| 302 | sc_uint<vci_param::N> address; |
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| 303 | if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1); |
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| 304 | else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); |
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| 305 | p_vci.cmdval = true; |
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| 306 | p_vci.address = address; |
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| 307 | p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); |
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| 308 | p_vci.wdata = 0; |
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| 309 | p_vci.be = (sc_uint<vci_param::B>)((r_cmd_buf1.read() & 0x000000001ELL) >> 1); |
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| 310 | p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); |
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| 311 | p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); |
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| 312 | p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); |
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| 313 | p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); |
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| 314 | p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); |
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| 315 | p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); |
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| 316 | p_vci.eop = true; |
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| 317 | } |
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| 318 | else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write command |
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| 319 | { |
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| 320 | if ( r_fifo_cmd.rok() ) |
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[284] | 321 | { |
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[149] | 322 | sc_uint<vci_param::N> address; |
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| 323 | if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1); |
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[284] | 324 | else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); |
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[149] | 325 | p_vci.cmdval = true; |
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[287] | 326 | p_vci.address = address + (r_flit_count.read()*vci_param::B); |
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| 327 | p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); |
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| 328 | p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); |
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| 329 | p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); |
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| 330 | p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); |
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| 331 | p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); |
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| 332 | p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); |
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| 333 | p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); |
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[185] | 334 | p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); |
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| 335 | p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); |
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[287] | 336 | p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL); |
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| 337 | } |
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| 338 | else |
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[148] | 339 | { |
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[287] | 340 | p_vci.cmdval = false; |
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[148] | 341 | } |
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[287] | 342 | } |
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[148] | 343 | |
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[284] | 344 | // DSPIN_OUT interface |
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| 345 | p_dspin_out.write = r_fifo_rsp.rok(); |
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| 346 | p_dspin_out.data = r_fifo_rsp.read(); |
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[148] | 347 | |
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[284] | 348 | // DSPIN_IN interface |
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| 349 | p_dspin_in.read = r_fifo_cmd.wok(); |
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[148] | 350 | |
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| 351 | }; // end genMoore |
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| 352 | |
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[149] | 353 | ///////////////////////// |
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| 354 | tmpl(void)::print_trace() |
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| 355 | { |
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| 356 | const char* cmd_str[] = { |
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| 357 | "CMD_IDLE ", |
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| 358 | "CMD_BROADCAST", |
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| 359 | "CMD_RW ", |
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| 360 | "CMD_READ ", |
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| 361 | "CMD_WDATA ", |
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| 362 | }; |
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| 363 | const char* rsp_str[] = { |
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[287] | 364 | "RSP_IDLE ", |
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| 365 | "RSP_DSPIN_SINGLE_FLIT", |
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| 366 | "RSP_DSPIN_MULTI_FLIT ", |
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[149] | 367 | }; |
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| 368 | std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()] |
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[284] | 369 | << " | " << rsp_str[r_rsp_fsm.read()] |
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[149] | 370 | << " | fifo_cmd = " << r_fifo_cmd.filled_status() |
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| 371 | << " | fifo_rsp = " << r_fifo_rsp.filled_status() |
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[284] | 372 | << std::endl; |
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[149] | 373 | } |
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| 374 | |
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[148] | 375 | }} // end namespace |
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| 376 | |
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| 377 | // Local Variables: |
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| 378 | // tab-width: 4 |
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| 379 | // c-basic-offset: 4 |
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| 380 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 381 | // indent-tabs-mode: nil |
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| 382 | // End: |
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| 383 | |
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| 384 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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