source: trunk/modules @ 137

Name Size Rev Age Author Last Change
../
vci_block_device_tsar 20   14 years nipo Update DSX metadata
vci_block_device_tsar_v2 20   14 years nipo Update DSX metadata
vci_cc_vcache_wrapper2 20   14 years nipo Update DSX metadata
vci_cc_vcache_wrapper2_ring 20   14 years nipo Update DSX metadata
vci_cc_xcache_wrapper 20   14 years nipo Update DSX metadata
vci_dma_tsar 20   14 years nipo Update DSX metadata
vci_dma_tsar_v2 20   14 years nipo Update DSX metadata
vci_mem_cache 20   14 years nipo Update DSX metadata
vci_mem_cache_v1 32   14 years guthmull Add SC randomization to V1
vci_cc_vcache_wrapper2_multi 37   14 years gao Bug correction
vci_cc_vcache_wrapper_multi 40   14 years gao cc_vcache_multi added
vci_cc_xcache_wrapper_multi 47   14 years alain
vci_mem_cache_v2s 54   14 years bouyer Remove debug output
vci_mem_cache_v2 83   14 years guthmull Fix the masking of RERROR field
vci_mem_cache_v3 83   14 years guthmull Fix the masking of RERROR field
vci_cc_xcache_wrapper_v1 85   14 years simerabe removing duplicate ring_signals_2
vci_cc_vcache_wrapper_v1 119   14 years gao Modification for synthetisable reason
vci_cc_vcache_wrapper2_v1 130   14 years gao Cleanup fsm seperated from vci fsm to evite deadlock
vci_cc_xcache_wrapper_v4 134   14 years kane add multi write buffer in cc_xcache_v4
vci_mem_cache_v4 134   14 years kane add multi write buffer in cc_xcache_v4
vci_synthetic_initator 135   14 years choichil Initiator with bug correction in latency computing
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