[259] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache_v3.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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| 28 | */ |
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| 29 | /* |
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| 30 | * |
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| 31 | * Modifications done by Christophe Choichillon on the 7/04/2009: |
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| 32 | * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE |
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| 33 | * - Adding a new VCI target port for the CLEANUP network |
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| 34 | * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP |
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| 35 | * |
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| 36 | * Modifications to do : |
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| 37 | * - Adding new variables used by the CLEANUP FSM |
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| 38 | * |
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| 39 | */ |
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| 40 | |
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| 41 | #ifndef SOCLIB_CABA_MEM_CACHE_V3_H |
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| 42 | #define SOCLIB_CABA_MEM_CACHE_V3_H |
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| 43 | |
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| 44 | #include <inttypes.h> |
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| 45 | #include <systemc> |
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| 46 | #include <list> |
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| 47 | #include <cassert> |
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| 48 | #include <iostream> |
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| 49 | #include <fstream> |
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| 50 | #include "arithmetics.h" |
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| 51 | #include "alloc_elems.h" |
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| 52 | #include "caba_base_module.h" |
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| 53 | #include "vci_target.h" |
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| 54 | #include "vci_initiator.h" |
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| 55 | #include "generic_fifo.h" |
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| 56 | #include "mapping_table.h" |
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| 57 | #include "int_tab.h" |
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| 58 | #include "mem_cache_directory_v3.h" |
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| 59 | #include "xram_transaction_v3.h" |
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| 60 | #include "update_tab_v3.h" |
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| 61 | #include "atomic_tab_v3.h" |
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| 62 | #include "config.h" |
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| 63 | |
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| 64 | #define TRANSACTION_TAB_LINES CONFIG_MEMC_TRANSACTION_TAB_LINES // Number of lines in the transaction tab |
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| 65 | #define UPDATE_TAB_LINES CONFIG_MEMC_UPDATE_TAB_LINES // Number of lines in the update tab |
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| 66 | |
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| 67 | namespace soclib { namespace caba { |
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| 68 | using namespace sc_core; |
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| 69 | |
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| 70 | template<typename vci_param> |
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| 71 | class VciMemCacheV3 |
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| 72 | : public soclib::caba::BaseModule |
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| 73 | { |
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| 74 | typedef sc_dt::sc_uint<40> addr_t; |
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| 75 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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| 76 | typedef uint32_t data_t; |
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| 77 | typedef uint32_t tag_t; |
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| 78 | typedef uint32_t size_t; |
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| 79 | typedef uint32_t be_t; |
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| 80 | typedef uint32_t copy_t; |
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| 81 | |
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| 82 | /* States of the TGT_CMD fsm */ |
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| 83 | enum tgt_cmd_fsm_state_e{ |
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| 84 | TGT_CMD_IDLE, |
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| 85 | TGT_CMD_READ, |
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| 86 | TGT_CMD_READ_EOP, |
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| 87 | TGT_CMD_WRITE, |
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| 88 | TGT_CMD_ATOMIC, |
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| 89 | }; |
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| 90 | |
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| 91 | /* States of the TGT_RSP fsm */ |
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| 92 | enum tgt_rsp_fsm_state_e{ |
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| 93 | TGT_RSP_READ_IDLE, |
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| 94 | TGT_RSP_WRITE_IDLE, |
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| 95 | TGT_RSP_LLSC_IDLE, |
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| 96 | TGT_RSP_XRAM_IDLE, |
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| 97 | TGT_RSP_INIT_IDLE, |
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| 98 | TGT_RSP_CLEANUP_IDLE, |
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| 99 | TGT_RSP_READ, |
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| 100 | TGT_RSP_WRITE, |
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| 101 | TGT_RSP_LLSC, |
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| 102 | TGT_RSP_XRAM, |
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| 103 | TGT_RSP_INIT, |
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| 104 | TGT_RSP_CLEANUP, |
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| 105 | }; |
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| 106 | |
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| 107 | /* States of the INIT_CMD fsm */ |
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| 108 | enum init_cmd_fsm_state_e{ |
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| 109 | INIT_CMD_INVAL_IDLE, |
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| 110 | INIT_CMD_INVAL_NLINE, |
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| 111 | INIT_CMD_XRAM_BRDCAST, |
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| 112 | INIT_CMD_UPDT_IDLE, |
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| 113 | INIT_CMD_WRITE_BRDCAST, |
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| 114 | INIT_CMD_UPDT_NLINE, |
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| 115 | INIT_CMD_UPDT_INDEX, |
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| 116 | INIT_CMD_UPDT_DATA, |
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| 117 | INIT_CMD_SC_UPDT_IDLE, |
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| 118 | INIT_CMD_SC_BRDCAST, |
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| 119 | INIT_CMD_SC_UPDT_NLINE, |
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| 120 | INIT_CMD_SC_UPDT_INDEX, |
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| 121 | INIT_CMD_SC_UPDT_DATA, |
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| 122 | }; |
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| 123 | |
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| 124 | /* States of the INIT_RSP fsm */ |
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| 125 | enum init_rsp_fsm_state_e{ |
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| 126 | INIT_RSP_IDLE, |
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| 127 | INIT_RSP_UPT_LOCK, |
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| 128 | INIT_RSP_UPT_CLEAR, |
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| 129 | INIT_RSP_END, |
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| 130 | }; |
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| 131 | |
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| 132 | /* States of the READ fsm */ |
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| 133 | enum read_fsm_state_e{ |
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| 134 | READ_IDLE, |
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| 135 | READ_DIR_LOCK, |
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| 136 | READ_DIR_HIT, |
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| 137 | READ_HEAP_LOCK, |
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| 138 | READ_HEAP_WRITE, |
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| 139 | READ_HEAP_ERASE, |
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| 140 | READ_HEAP_LAST, |
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| 141 | READ_RSP, |
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| 142 | READ_TRT_LOCK, |
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| 143 | READ_TRT_SET, |
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| 144 | READ_XRAM_REQ, |
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| 145 | }; |
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| 146 | |
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| 147 | /* States of the WRITE fsm */ |
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| 148 | enum write_fsm_state_e{ |
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| 149 | WRITE_IDLE, |
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| 150 | WRITE_NEXT, |
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| 151 | WRITE_DIR_LOCK, |
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| 152 | WRITE_DIR_HIT_READ, |
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| 153 | WRITE_DIR_HIT, |
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| 154 | WRITE_DIR_HIT_RSP, |
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| 155 | WRITE_UPT_LOCK, |
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| 156 | WRITE_HEAP_LOCK, |
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| 157 | WRITE_UPT_REQ, |
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| 158 | WRITE_UPDATE, |
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| 159 | WRITE_UPT_DEC, |
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| 160 | WRITE_RSP, |
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| 161 | WRITE_TRT_LOCK, |
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| 162 | WRITE_TRT_DATA, |
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| 163 | WRITE_TRT_SET, |
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| 164 | WRITE_WAIT, |
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| 165 | WRITE_XRAM_REQ, |
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| 166 | WRITE_TRT_WRITE_LOCK, |
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| 167 | WRITE_INVAL_LOCK, |
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| 168 | WRITE_DIR_INVAL, |
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| 169 | WRITE_INVAL, |
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| 170 | WRITE_XRAM_SEND, |
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| 171 | WRITE_HEAP_ERASE, |
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| 172 | WRITE_HEAP_LAST, |
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| 173 | }; |
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| 174 | |
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| 175 | /* States of the IXR_RSP fsm */ |
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| 176 | enum ixr_rsp_fsm_state_e{ |
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| 177 | IXR_RSP_IDLE, |
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| 178 | IXR_RSP_ACK, |
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| 179 | IXR_RSP_TRT_ERASE, |
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| 180 | IXR_RSP_TRT_READ, |
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| 181 | }; |
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| 182 | |
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| 183 | /* States of the XRAM_RSP fsm */ |
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| 184 | enum xram_rsp_fsm_state_e{ |
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| 185 | XRAM_RSP_IDLE, |
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| 186 | XRAM_RSP_TRT_COPY, |
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| 187 | XRAM_RSP_TRT_DIRTY, |
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| 188 | XRAM_RSP_DIR_LOCK, |
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| 189 | XRAM_RSP_DIR_UPDT, |
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| 190 | XRAM_RSP_DIR_RSP, |
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| 191 | XRAM_RSP_INVAL_LOCK, |
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| 192 | XRAM_RSP_INVAL_WAIT, |
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| 193 | XRAM_RSP_INVAL, |
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| 194 | XRAM_RSP_WRITE_DIRTY, |
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| 195 | XRAM_RSP_HEAP_ERASE, |
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| 196 | XRAM_RSP_HEAP_LAST, |
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| 197 | }; |
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| 198 | |
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| 199 | /* States of the IXR_CMD fsm */ |
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| 200 | enum ixr_cmd_fsm_state_e{ |
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| 201 | IXR_CMD_READ_IDLE, |
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| 202 | IXR_CMD_WRITE_IDLE, |
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| 203 | IXR_CMD_LLSC_IDLE, |
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| 204 | IXR_CMD_XRAM_IDLE, |
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| 205 | IXR_CMD_READ_NLINE, |
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| 206 | IXR_CMD_WRITE_NLINE, |
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| 207 | IXR_CMD_LLSC_NLINE, |
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| 208 | IXR_CMD_XRAM_DATA, |
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| 209 | }; |
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| 210 | |
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| 211 | /* States of the LLSC fsm */ |
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| 212 | enum llsc_fsm_state_e{ |
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| 213 | LLSC_IDLE, |
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| 214 | LL_DIR_LOCK, |
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| 215 | LL_DIR_HIT, |
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| 216 | LL_RSP, |
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| 217 | SC_DIR_LOCK, |
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| 218 | SC_DIR_HIT, |
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| 219 | SC_UPT_LOCK, |
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| 220 | SC_WAIT, |
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| 221 | SC_HEAP_LOCK, |
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| 222 | SC_UPT_REQ, |
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| 223 | SC_UPDATE, |
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| 224 | SC_TRT_LOCK, |
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| 225 | SC_INVAL_LOCK, |
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| 226 | SC_DIR_INVAL, |
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| 227 | SC_INVAL, |
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| 228 | SC_XRAM_SEND, |
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| 229 | SC_HEAP_ERASE, |
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| 230 | SC_HEAP_LAST, |
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| 231 | SC_RSP_FALSE, |
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| 232 | SC_RSP_TRUE, |
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| 233 | LLSC_TRT_LOCK, |
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| 234 | LLSC_TRT_SET, |
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| 235 | LLSC_XRAM_REQ, |
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| 236 | }; |
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| 237 | |
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| 238 | /* States of the CLEANUP fsm */ |
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| 239 | enum cleanup_fsm_state_e{ |
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| 240 | CLEANUP_IDLE, |
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| 241 | CLEANUP_DIR_LOCK, |
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| 242 | CLEANUP_DIR_WRITE, |
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| 243 | CLEANUP_HEAP_LOCK, |
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| 244 | CLEANUP_HEAP_SEARCH, |
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| 245 | CLEANUP_HEAP_CLEAN, |
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| 246 | CLEANUP_HEAP_FREE, |
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| 247 | CLEANUP_UPT_LOCK, |
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| 248 | CLEANUP_UPT_WRITE, |
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| 249 | CLEANUP_WRITE_RSP, |
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| 250 | CLEANUP_RSP, |
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| 251 | }; |
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| 252 | |
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| 253 | /* States of the ALLOC_DIR fsm */ |
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| 254 | enum alloc_dir_fsm_state_e{ |
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| 255 | ALLOC_DIR_READ, |
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| 256 | ALLOC_DIR_WRITE, |
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| 257 | ALLOC_DIR_LLSC, |
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| 258 | ALLOC_DIR_CLEANUP, |
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| 259 | ALLOC_DIR_XRAM_RSP, |
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| 260 | }; |
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| 261 | |
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| 262 | /* States of the ALLOC_TRT fsm */ |
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| 263 | enum alloc_trt_fsm_state_e{ |
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| 264 | ALLOC_TRT_READ, |
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| 265 | ALLOC_TRT_WRITE, |
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| 266 | ALLOC_TRT_LLSC, |
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| 267 | ALLOC_TRT_XRAM_RSP, |
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| 268 | ALLOC_TRT_IXR_RSP, |
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| 269 | }; |
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| 270 | |
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| 271 | /* States of the ALLOC_UPT fsm */ |
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| 272 | enum alloc_upt_fsm_state_e{ |
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| 273 | ALLOC_UPT_WRITE, |
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| 274 | ALLOC_UPT_XRAM_RSP, |
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| 275 | ALLOC_UPT_INIT_RSP, |
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| 276 | ALLOC_UPT_CLEANUP, |
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| 277 | ALLOC_UPT_LLSC, |
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| 278 | }; |
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| 279 | |
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| 280 | /* States of the ALLOC_HEAP fsm */ |
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| 281 | enum alloc_heap_fsm_state_e{ |
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| 282 | ALLOC_HEAP_READ, |
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| 283 | ALLOC_HEAP_WRITE, |
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| 284 | ALLOC_HEAP_LLSC, |
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| 285 | ALLOC_HEAP_CLEANUP, |
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| 286 | ALLOC_HEAP_XRAM_RSP, |
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| 287 | }; |
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| 288 | |
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| 289 | uint32_t m_cpt_cycles; // Counter of cycles |
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| 290 | uint32_t m_cpt_read; // Number of READ transactions |
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| 291 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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| 292 | uint32_t m_cpt_write; // Number of WRITE transactions |
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| 293 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 294 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 295 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 296 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 297 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 298 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 299 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 300 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 301 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 302 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 303 | uint32_t m_cpt_sc; // Number of SC transactions |
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| 304 | uint32_t m_total_cycles; |
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| 305 | unsigned long m_waiting_cycles; // Number of TGT FSM waiting cycles |
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| 306 | double m_wait_threshold; // Trace threshold upon waiting cycles percentage |
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| 307 | |
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| 308 | protected: |
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| 309 | |
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| 310 | SC_HAS_PROCESS(VciMemCacheV3); |
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| 311 | |
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| 312 | public: |
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| 313 | sc_in<bool> p_clk; |
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| 314 | sc_in<bool> p_resetn; |
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| 315 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 316 | soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup; |
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| 317 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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| 318 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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| 319 | |
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| 320 | VciMemCacheV3( |
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| 321 | sc_module_name name, // Instance Name |
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| 322 | const soclib::common::MappingTable &mtp, // Mapping table for primary requets |
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| 323 | const soclib::common::MappingTable &mtc, // Mapping table for coherence requets |
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| 324 | const soclib::common::MappingTable &mtx, // Mapping table for XRAM |
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| 325 | const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) |
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| 326 | const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) |
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| 327 | const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) |
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| 328 | const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup |
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| 329 | size_t nways, // Number of ways per set |
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| 330 | size_t nsets, // Number of sets |
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| 331 | size_t nwords, // Number of words per line |
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| 332 | size_t heap_size=1024); // Size of the heap |
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| 333 | |
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| 334 | ~VciMemCacheV3(); |
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| 335 | |
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| 336 | void transition(); |
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| 337 | |
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| 338 | void genMoore(); |
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| 339 | |
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| 340 | void print_stats(); |
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| 341 | void clear_stats(); |
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| 342 | |
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| 343 | private: |
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| 344 | |
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| 345 | void print_log(); |
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| 346 | void print_trace_to_log_file(); |
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| 347 | |
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| 348 | // Component attributes |
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| 349 | const size_t m_initiators; // Number of initiators |
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| 350 | const size_t m_heap_size; // Size of the heap |
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| 351 | const size_t m_ways; // Number of ways in a set |
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| 352 | const size_t m_sets; // Number of cache sets |
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| 353 | const size_t m_words; // Number of words in a line |
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| 354 | const size_t m_srcid_ixr; // Srcid for requests to XRAM |
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| 355 | const size_t m_srcid_ini; // Srcid for requests to processors |
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| 356 | std::list<soclib::common::Segment> m_seglist; // memory cached into the cache |
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| 357 | std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache |
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| 358 | vci_addr_t *m_coherence_table; // address(srcid) |
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| 359 | AtomicTab m_atomic_tab; // atomic access table |
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| 360 | TransactionTab m_transaction_tab; // xram transaction table |
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| 361 | UpdateTab m_update_tab; // pending update & invalidate |
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| 362 | CacheDirectory m_cache_directory; // data cache directory |
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| 363 | HeapDirectory m_heap_directory; // heap directory |
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| 364 | |
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| 365 | data_t ***m_cache_data; // data array[set][way][word] |
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| 366 | std::ofstream m_log; |
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| 367 | size_t m_tm_start; |
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| 368 | long long m_debug_start; |
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| 369 | size_t m_tm_end; |
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| 370 | size_t m_period; |
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| 371 | |
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| 372 | |
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| 373 | // adress masks |
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| 374 | const soclib::common::AddressMaskingTable<vci_addr_t> m_x; |
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| 375 | const soclib::common::AddressMaskingTable<vci_addr_t> m_y; |
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| 376 | const soclib::common::AddressMaskingTable<vci_addr_t> m_z; |
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| 377 | const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; |
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| 378 | |
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| 379 | // broadcast address |
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| 380 | vci_addr_t broadcast_addr; |
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| 381 | |
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| 382 | ////////////////////////////////////////////////// |
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| 383 | // Others registers |
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| 384 | ////////////////////////////////////////////////// |
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| 385 | size_t m_copy_threshold; |
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| 386 | sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line |
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| 387 | |
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| 388 | ////////////////////////////////////////////////// |
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| 389 | // Registers controlled by the TGT_CMD fsm |
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| 390 | ////////////////////////////////////////////////// |
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| 391 | |
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| 392 | // Fifo between TGT_CMD fsm and READ fsm |
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| 393 | GenericFifo<uint64_t> m_cmd_read_addr_fifo; |
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| 394 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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| 395 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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| 396 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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| 397 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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| 398 | |
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| 399 | // Fifo between TGT_CMD fsm and WRITE fsm |
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| 400 | GenericFifo<uint64_t> m_cmd_write_addr_fifo; |
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| 401 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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| 402 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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| 403 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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| 404 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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| 405 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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| 406 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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| 407 | |
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| 408 | // Fifo between TGT_CMD fsm and LLSC fsm |
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| 409 | GenericFifo<uint64_t> m_cmd_llsc_addr_fifo; |
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| 410 | GenericFifo<bool> m_cmd_llsc_sc_fifo; |
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| 411 | GenericFifo<size_t> m_cmd_llsc_srcid_fifo; |
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| 412 | GenericFifo<size_t> m_cmd_llsc_trdid_fifo; |
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| 413 | GenericFifo<size_t> m_cmd_llsc_pktid_fifo; |
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| 414 | GenericFifo<data_t> m_cmd_llsc_wdata_fifo; |
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| 415 | |
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| 416 | sc_signal<int> r_tgt_cmd_fsm; |
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| 417 | |
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| 418 | sc_signal<size_t> r_index; |
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| 419 | size_t nseg; |
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| 420 | size_t ncseg; |
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| 421 | soclib::common::Segment **m_seg; |
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| 422 | soclib::common::Segment **m_cseg; |
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| 423 | /////////////////////////////////////////////////////// |
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| 424 | // Registers controlled by the READ fsm |
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| 425 | /////////////////////////////////////////////////////// |
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| 426 | |
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| 427 | sc_signal<int> r_read_fsm; // FSM state |
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| 428 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
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| 429 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
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| 430 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
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| 431 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
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| 432 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
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| 433 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
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| 434 | sc_signal<bool> r_read_inst; // it is an instruction line |
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| 435 | sc_signal<size_t> r_read_count; // number of copies |
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| 436 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
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| 437 | sc_signal<data_t> *r_read_data; // data (one cache line) |
---|
| 438 | sc_signal<size_t> r_read_way; // associative way (in cache) |
---|
| 439 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
---|
| 440 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
---|
| 441 | sc_signal<bool> r_read_last_free; // Last free entry |
---|
| 442 | |
---|
| 443 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 444 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
---|
| 445 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
---|
| 446 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 447 | |
---|
| 448 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
---|
| 449 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
---|
| 450 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 451 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 452 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 453 | sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line) |
---|
| 454 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
---|
| 455 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
---|
| 456 | |
---|
| 457 | /////////////////////////////////////////////////////////////// |
---|
| 458 | // Registers controlled by the WRITE fsm |
---|
| 459 | /////////////////////////////////////////////////////////////// |
---|
| 460 | |
---|
| 461 | sc_signal<int> r_write_fsm; // FSM state |
---|
| 462 | sc_signal<addr_t> r_write_address; // first word address |
---|
| 463 | sc_signal<size_t> r_write_word_index; // first word index in line |
---|
| 464 | sc_signal<size_t> r_write_word_count; // number of words in line |
---|
| 465 | sc_signal<size_t> r_write_srcid; // transaction srcid |
---|
| 466 | sc_signal<size_t> r_write_trdid; // transaction trdid |
---|
| 467 | sc_signal<size_t> r_write_pktid; // transaction pktid |
---|
| 468 | sc_signal<data_t> *r_write_data; // data (one cache line) |
---|
| 469 | sc_signal<be_t> *r_write_be; // one byte enable per word |
---|
| 470 | sc_signal<bool> r_write_byte; // is it a byte write |
---|
| 471 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
---|
| 472 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
---|
| 473 | sc_signal<bool> r_write_inst; // instruction bit |
---|
| 474 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
---|
| 475 | sc_signal<size_t> r_write_copy; // first owner of the line |
---|
| 476 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
---|
| 477 | sc_signal<size_t> r_write_count; // number of copies |
---|
| 478 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
---|
| 479 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
---|
| 480 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
---|
| 481 | sc_signal<size_t> r_write_way; // way of the line |
---|
| 482 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
---|
| 483 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
---|
| 484 | |
---|
| 485 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 486 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
---|
| 487 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
---|
| 488 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
---|
| 489 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
---|
| 490 | |
---|
| 491 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
---|
| 492 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
---|
| 493 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
---|
| 494 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
---|
| 495 | sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data |
---|
| 496 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 497 | |
---|
| 498 | // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
| 499 | sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request |
---|
| 500 | sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request |
---|
| 501 | sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index |
---|
| 502 | sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table |
---|
| 503 | sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line) |
---|
| 504 | sc_signal<bool> *r_write_to_init_cmd_we; // word enable |
---|
| 505 | sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line |
---|
| 506 | sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line |
---|
| 507 | GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 508 | GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 509 | |
---|
| 510 | // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) |
---|
| 511 | sc_signal<bool> r_write_to_init_rsp_req; // valid request |
---|
| 512 | sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table |
---|
| 513 | |
---|
| 514 | ///////////////////////////////////////////////////////// |
---|
| 515 | // Registers controlled by INIT_RSP fsm |
---|
| 516 | ////////////////////////////////////////////////////////// |
---|
| 517 | |
---|
| 518 | sc_signal<int> r_init_rsp_fsm; // FSM state |
---|
| 519 | sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table |
---|
| 520 | sc_signal<size_t> r_init_rsp_srcid; // pending write srcid |
---|
| 521 | sc_signal<size_t> r_init_rsp_trdid; // pending write trdid |
---|
| 522 | sc_signal<size_t> r_init_rsp_pktid; // pending write pktid |
---|
| 523 | sc_signal<addr_t> r_init_rsp_nline; // pending write nline |
---|
| 524 | |
---|
| 525 | // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) |
---|
| 526 | sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request |
---|
| 527 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 528 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 529 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 530 | |
---|
| 531 | /////////////////////////////////////////////////////// |
---|
| 532 | // Registers controlled by CLEANUP fsm |
---|
| 533 | /////////////////////////////////////////////////////// |
---|
| 534 | |
---|
| 535 | sc_signal<int> r_cleanup_fsm; // FSM state |
---|
| 536 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
---|
| 537 | sc_signal<size_t> r_cleanup_trdid; // transaction trdid |
---|
| 538 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
---|
| 539 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
---|
| 540 | |
---|
| 541 | sc_signal<copy_t> r_cleanup_copy; // first copy |
---|
| 542 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
---|
| 543 | sc_signal<copy_t> r_cleanup_count; // number of copies |
---|
| 544 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
---|
| 545 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
---|
| 546 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
---|
| 547 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
---|
| 548 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
---|
| 549 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
---|
| 550 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
---|
| 551 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
---|
| 552 | sc_signal<bool> r_cleanup_inst; // inst bit (in directory) |
---|
| 553 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
---|
| 554 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
---|
| 555 | |
---|
| 556 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
---|
| 557 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
---|
| 558 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
---|
| 559 | sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp |
---|
| 560 | |
---|
| 561 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
---|
| 562 | |
---|
| 563 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
---|
| 564 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
---|
| 565 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
---|
| 566 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
---|
| 567 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
| 568 | |
---|
| 569 | /////////////////////////////////////////////////////// |
---|
| 570 | // Registers controlled by LLSC fsm |
---|
| 571 | /////////////////////////////////////////////////////// |
---|
| 572 | |
---|
| 573 | sc_signal<int> r_llsc_fsm; // FSM state |
---|
| 574 | sc_signal<data_t> r_llsc_data; // read data word |
---|
| 575 | sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy |
---|
| 576 | sc_signal<bool> r_llsc_copy_inst; // Type of the first copy |
---|
| 577 | sc_signal<size_t> r_llsc_count; // number of copies |
---|
| 578 | sc_signal<size_t> r_llsc_ptr; // pointer to the heap |
---|
| 579 | sc_signal<size_t> r_llsc_next_ptr; // next pointer to the heap |
---|
| 580 | sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory) |
---|
| 581 | sc_signal<bool> r_llsc_dirty; // dirty bit (in directory) |
---|
| 582 | sc_signal<bool> r_llsc_inst; // inst bit |
---|
| 583 | sc_signal<size_t> r_llsc_way; // way in directory |
---|
| 584 | sc_signal<size_t> r_llsc_set; // set in directory |
---|
| 585 | sc_signal<data_t> r_llsc_tag; // cache line tag (in directory) |
---|
| 586 | sc_signal<size_t> r_llsc_trt_index; // Transaction Table index |
---|
| 587 | sc_signal<size_t> r_llsc_upt_index; // Update Table index |
---|
| 588 | |
---|
| 589 | // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read) |
---|
| 590 | sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request |
---|
| 591 | sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index |
---|
| 592 | sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 593 | sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request |
---|
| 594 | sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data |
---|
| 595 | |
---|
| 596 | |
---|
| 597 | // Buffer between LLSC fsm and TGT_RSP fsm |
---|
| 598 | sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request |
---|
| 599 | sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word |
---|
| 600 | sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 601 | sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 602 | sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 603 | |
---|
| 604 | // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
---|
| 605 | sc_signal<bool> r_llsc_to_init_cmd_multi_req; // valid request |
---|
| 606 | sc_signal<bool> r_llsc_to_init_cmd_brdcast_req; // brdcast request |
---|
| 607 | sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index |
---|
| 608 | sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table |
---|
| 609 | sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word) |
---|
| 610 | sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line |
---|
| 611 | GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 612 | GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 613 | |
---|
| 614 | // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry) |
---|
| 615 | sc_signal<bool> r_llsc_to_init_rsp_req; // valid request |
---|
| 616 | sc_signal<size_t> r_llsc_to_init_rsp_upt_index; // index in update table |
---|
| 617 | |
---|
| 618 | //////////////////////////////////////////////////// |
---|
| 619 | // Registers controlled by the IXR_RSP fsm |
---|
| 620 | //////////////////////////////////////////////////// |
---|
| 621 | |
---|
| 622 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 623 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 624 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
| 625 | |
---|
| 626 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
| 627 | sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
| 628 | |
---|
| 629 | //////////////////////////////////////////////////// |
---|
| 630 | // Registers controlled by the XRAM_RSP fsm |
---|
| 631 | //////////////////////////////////////////////////// |
---|
| 632 | |
---|
| 633 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 634 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 635 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 636 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 637 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 638 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 639 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 640 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 641 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 642 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 643 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 644 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 645 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 646 | sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data |
---|
| 647 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
| 648 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
| 649 | |
---|
| 650 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
| 651 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 652 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 653 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 654 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 655 | sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 656 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 657 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response |
---|
| 658 | |
---|
| 659 | // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) |
---|
| 660 | sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request |
---|
| 661 | sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request |
---|
| 662 | sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index; |
---|
| 663 | sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry |
---|
| 664 | GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 665 | GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
| 666 | |
---|
| 667 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
---|
| 668 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
---|
| 669 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
---|
| 670 | sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data |
---|
| 671 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
---|
| 672 | |
---|
| 673 | //////////////////////////////////////////////////// |
---|
| 674 | // Registers controlled by the IXR_CMD fsm |
---|
| 675 | //////////////////////////////////////////////////// |
---|
| 676 | |
---|
| 677 | sc_signal<int> r_ixr_cmd_fsm; |
---|
| 678 | sc_signal<size_t> r_ixr_cmd_cpt; |
---|
| 679 | |
---|
| 680 | //////////////////////////////////////////////////// |
---|
| 681 | // Registers controlled by TGT_RSP fsm |
---|
| 682 | //////////////////////////////////////////////////// |
---|
| 683 | |
---|
| 684 | sc_signal<int> r_tgt_rsp_fsm; |
---|
| 685 | sc_signal<size_t> r_tgt_rsp_cpt; |
---|
| 686 | |
---|
| 687 | //////////////////////////////////////////////////// |
---|
| 688 | // Registers controlled by INIT_CMD fsm |
---|
| 689 | //////////////////////////////////////////////////// |
---|
| 690 | |
---|
| 691 | sc_signal<int> r_init_cmd_fsm; |
---|
| 692 | sc_signal<size_t> r_init_cmd_cpt; |
---|
| 693 | sc_signal<bool> r_init_cmd_inst; |
---|
| 694 | |
---|
| 695 | //////////////////////////////////////////////////// |
---|
| 696 | // Registers controlled by ALLOC_DIR fsm |
---|
| 697 | //////////////////////////////////////////////////// |
---|
| 698 | |
---|
| 699 | sc_signal<int> r_alloc_dir_fsm; |
---|
| 700 | |
---|
| 701 | //////////////////////////////////////////////////// |
---|
| 702 | // Registers controlled by ALLOC_TRT fsm |
---|
| 703 | //////////////////////////////////////////////////// |
---|
| 704 | |
---|
| 705 | sc_signal<int> r_alloc_trt_fsm; |
---|
| 706 | |
---|
| 707 | //////////////////////////////////////////////////// |
---|
| 708 | // Registers controlled by ALLOC_UPT fsm |
---|
| 709 | //////////////////////////////////////////////////// |
---|
| 710 | |
---|
| 711 | sc_signal<int> r_alloc_upt_fsm; |
---|
| 712 | |
---|
| 713 | //////////////////////////////////////////////////// |
---|
| 714 | // Registers controlled by ALLOC_HEAP fsm |
---|
| 715 | //////////////////////////////////////////////////// |
---|
| 716 | |
---|
| 717 | sc_signal<int> r_alloc_heap_fsm; |
---|
| 718 | |
---|
| 719 | }; // end class VciMemCacheV3 |
---|
| 720 | |
---|
| 721 | }} |
---|
| 722 | |
---|
| 723 | #endif |
---|
| 724 | |
---|
| 725 | // Local Variables: |
---|
| 726 | // tab-width: 4 |
---|
| 727 | // c-basic-offset: 4 |
---|
| 728 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 729 | // indent-tabs-mode: nil |
---|
| 730 | // End: |
---|
| 731 | |
---|
| 732 | // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
---|
| 733 | |
---|