|
Last change
on this file since 294 was
140,
checked in by kane, 14 years ago
|
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yAjout du multi_cache : plusieurs processeur peuvent ce partager le même cache L1.
2 remarques, (1) deux nouveaux paramètres : nb_cpu, nb_cache. Pour avoir un cache dont le comportement est identique à la version d'avant, mettre ces paramètres à 1.
(2) le port d'interruption est maintenant un tableau dépendant du nombre de processeur.
Voir le fichier "platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp" pour plus de détails.
--Cette ligne, et les suivantes ci-dessous, seront ignorées--
M platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c
A platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile
M platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile
M platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp
M modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
M modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
M modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
M modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
M modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
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File size:
773 bytes
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| Line | |
|---|
| 1 | #include "common.h" |
|---|
| 2 | #include "stdio.h" |
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| 3 | #include "system.h" |
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| 4 | #include "stdio.h" |
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| 5 | |
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| 6 | #ifdef SIMHELPER_BASE |
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| 7 | #include "soclib/simhelper.h" |
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| 8 | #endif |
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| 9 | |
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| 10 | static uint32_t lock; |
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| 11 | static uint32_t nb_thread; |
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| 12 | |
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| 13 | void system_start (void) |
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| 14 | { |
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| 15 | lock_lock(&lock); |
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| 16 | nb_thread ++; |
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| 17 | lock_unlock(&lock); |
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| 18 | |
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| 19 | printf("CPU %d\n",procnum()); |
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| 20 | } |
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| 21 | |
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| 22 | void system_stop (char* file, int line, int x) |
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| 23 | { |
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| 24 | printf("Exit(%d) in file \"%s\", line %d\n",x,file,line); |
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| 25 | |
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| 26 | lock_lock(&lock); |
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| 27 | uint32_t num_thread = --nb_thread; |
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| 28 | lock_unlock(&lock); |
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| 29 | |
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| 30 | // Last thread ? |
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| 31 | if (num_thread == 0) |
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| 32 | { |
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| 33 | #ifdef SIMHELPER_BASE |
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| 34 | soclib_io_set |
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| 35 | (base(SIMHELPER), |
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| 36 | SIMHELPER_SC_STOP, |
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| 37 | 0); |
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| 38 | #else |
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| 39 | # warning "No simhelper, exit will do a trap and an infinite loop" |
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| 40 | #endif |
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| 41 | } |
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| 42 | |
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| 43 | pause(); |
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| 44 | |
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| 45 | while(1); |
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| 46 | } |
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| 47 | |
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