[97] | 1 | |
---|
[103] | 2 | #include <stdint.h> |
---|
[97] | 3 | #include <systemc> |
---|
| 4 | #include <sys/time.h> |
---|
| 5 | #include <iostream> |
---|
| 6 | #include <cstdlib> |
---|
| 7 | #include <cstdarg> |
---|
| 8 | |
---|
[103] | 9 | #include "arithmetics.h" |
---|
[97] | 10 | #include "mapping_table.h" |
---|
| 11 | #include "alloc_elems.h" |
---|
[103] | 12 | #include "vci_simple_ram.h" |
---|
[99] | 13 | #include "vci_local_ring_fast.h" |
---|
| 14 | #include "virtual_dspin_router.h" |
---|
[97] | 15 | #include "vci_synthetic_initiator.h" |
---|
| 16 | |
---|
| 17 | // MESH SIZE |
---|
| 18 | #define X_MAX 2 |
---|
| 19 | #define Y_MAX 2 |
---|
| 20 | #define N_CLUSTERS X_MAX*Y_MAX |
---|
| 21 | // FLIT_WIDTH |
---|
| 22 | #define WIDTH_CMD 40 |
---|
| 23 | #define WIDTH_RSP 33 |
---|
| 24 | // Face of each DSPIN Router |
---|
| 25 | #define NORTH 0 |
---|
| 26 | #define SOUTH 1 |
---|
| 27 | #define EAST 2 |
---|
| 28 | #define WEST 3 |
---|
| 29 | #define LOCAL 4 |
---|
[105] | 30 | // VCI parameters |
---|
| 31 | #define cell_width 4 |
---|
| 32 | #define plen_width 8 |
---|
| 33 | #define address_width 32 |
---|
| 34 | #define error_width 1 |
---|
| 35 | #define clen_width 1 |
---|
| 36 | #define rflag_width 1 |
---|
| 37 | #define srcid_width 11 |
---|
| 38 | #define pktid_width 4 |
---|
| 39 | #define trdid_width 4 |
---|
| 40 | #define wrplen_width 1 |
---|
| 41 | // Adress of targets |
---|
| 42 | #define TARGET_ADDR 0x00000000 |
---|
| 43 | #define TARGET_SIZE 0x400 |
---|
[97] | 44 | |
---|
| 45 | |
---|
| 46 | int _main(int argc, char *argv[]) |
---|
| 47 | { |
---|
| 48 | using namespace sc_core; |
---|
| 49 | // Avoid repeating these everywhere |
---|
| 50 | using soclib::common::IntTab; |
---|
| 51 | using soclib::common::Segment; |
---|
| 52 | |
---|
[99] | 53 | using soclib::common::uint32_log2; |
---|
| 54 | |
---|
[97] | 55 | // Define VCI parameters |
---|
[105] | 56 | typedef soclib::caba::VciParams<cell_width, |
---|
| 57 | plen_width, |
---|
| 58 | address_width, |
---|
| 59 | error_width, |
---|
| 60 | clen_width, |
---|
| 61 | rflag_width, |
---|
| 62 | srcid_width, |
---|
| 63 | pktid_width, |
---|
| 64 | trdid_width, |
---|
| 65 | wrplen_width> vci_param; |
---|
[97] | 66 | |
---|
[105] | 67 | //soclib::common::Loader loader(); |
---|
[97] | 68 | // Mapping table primary network |
---|
[105] | 69 | soclib::common::MappingTable maptab0(address_width, IntTab(srcid_width-1 ,1), IntTab(srcid_width-1 ,1), 0xFFC0000); |
---|
| 70 | soclib::common::MappingTable maptab1(address_width, IntTab(srcid_width-1 ,1), IntTab(srcid_width-1 ,1), 0xFFC0000); |
---|
| 71 | for(int i = 0 ; i < Y_MAX ; i++){ |
---|
| 72 | for(int j = 0 ; j < X_MAX ; j++){ |
---|
| 73 | std::ostringstream str0; |
---|
| 74 | std::ostringstream str1; |
---|
| 75 | str0 << "Target_c0_" << (i*X_MAX+j) ; |
---|
| 76 | str1 << "Target_c1_" << (i*X_MAX+j) ; |
---|
| 77 | maptab0.add(Segment(str0.str(), TARGET_ADDR + ((i*X_MAX+j) << (address_width-srcid_width+1)), TARGET_SIZE, IntTab((i*X_MAX+j),0), false)); |
---|
| 78 | maptab1.add(Segment(str1.str(), TARGET_ADDR + ((i*X_MAX+j) << (address_width-srcid_width+1)), TARGET_SIZE, IntTab((i*X_MAX+j),0), false)); |
---|
| 79 | } |
---|
| 80 | } |
---|
[97] | 81 | |
---|
| 82 | |
---|
[103] | 83 | std::cout << maptab0 << std::endl; |
---|
[97] | 84 | // Signals |
---|
| 85 | |
---|
| 86 | sc_clock signal_clk("clk"); |
---|
| 87 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 88 | |
---|
[105] | 89 | soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c0 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c0", 2, N_CLUSTERS); |
---|
| 90 | soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c1 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c1", 2, N_CLUSTERS); |
---|
[99] | 91 | /////////////////////////////////////////////////////////////// |
---|
| 92 | // VDSPIN Signals : one level for in and out, one level for X length in the mesh, |
---|
| 93 | // one level for Y length in the mesh, last level for each port of the router |
---|
| 94 | /////////////////////////////////////////////////////////////// |
---|
[103] | 95 | soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c0 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_0", 2, Y_MAX, X_MAX, 5 ); |
---|
| 96 | soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c1 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_1", 2, Y_MAX, X_MAX, 5 ); |
---|
| 97 | soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c0 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_0", 2, Y_MAX, X_MAX, 5 ); |
---|
| 98 | soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c1 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_2", 2, Y_MAX, X_MAX, 5 ); |
---|
[97] | 99 | |
---|
| 100 | //soclib::caba::VciSignals<vci_param> * signal_vci_tgt_proc = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_tgt_proc", N_CLUSTERS); |
---|
| 101 | |
---|
| 102 | // N_CLUSTERS ring. |
---|
[99] | 103 | soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c0 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ; |
---|
| 104 | soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c1 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ; |
---|
| 105 | for(int i = 0 ; i < N_CLUSTERS ; i++){ // ringid, fifo, fifo, nb_init, nb_tgt |
---|
[105] | 106 | std::cout << "Passe " << i << " pour instanciation ring" << std::endl; |
---|
| 107 | std::ostringstream str0; |
---|
| 108 | std::ostringstream str1; |
---|
| 109 | str0 << "cluster_c0_" << i ; |
---|
| 110 | str1 << "cluster_c1_" << i ; |
---|
| 111 | new(&local_ring_c0[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str0.str().c_str() ,maptab0, IntTab(i), 2, 18, 1, 1); |
---|
| 112 | new(&local_ring_c1[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str1.str().c_str() ,maptab1, IntTab(i), 2, 18, 1, 1); |
---|
[99] | 113 | } |
---|
| 114 | |
---|
[97] | 115 | // Virtual dspin routers |
---|
| 116 | soclib::caba::VirtualDspinRouter<WIDTH_CMD> ** routers_cmd = (soclib::caba::VirtualDspinRouter<WIDTH_CMD> **) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_CMD> *) * Y_MAX); |
---|
| 117 | soclib::caba::VirtualDspinRouter<WIDTH_RSP> ** routers_rsp = (soclib::caba::VirtualDspinRouter<WIDTH_RSP> **) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_RSP> *) * Y_MAX); |
---|
| 118 | |
---|
| 119 | for(int i = 0; i < Y_MAX; i++ ){ |
---|
| 120 | routers_cmd[i] = (soclib::caba::VirtualDspinRouter<WIDTH_CMD> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_CMD>) * X_MAX); |
---|
| 121 | routers_rsp[i] = (soclib::caba::VirtualDspinRouter<WIDTH_RSP> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_RSP>) * X_MAX); |
---|
[105] | 122 | for(int j = 0; j < X_MAX; j++){ |
---|
| 123 | std::cout << "Passe " << i << j << " pour instanciation vdspin" << std::endl; |
---|
| 124 | new(&routers_cmd[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_CMD> ("VDspinRouterCMD" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); |
---|
| 125 | new(&routers_rsp[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_RSP> ("VDspinRouterRSP" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); |
---|
[97] | 126 | } |
---|
| 127 | } |
---|
| 128 | |
---|
| 129 | |
---|
| 130 | /////////////////////////////////////////////////////////////// |
---|
| 131 | // Components |
---|
| 132 | /////////////////////////////////////////////////////////////// |
---|
| 133 | |
---|
| 134 | // N_CLUSTERS VCI Synthetic Initiator (1 initiator per cluster/network) |
---|
[99] | 135 | soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c0 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS); |
---|
| 136 | soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c1 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS); |
---|
| 137 | for(int i = 0 ; i < Y_MAX; i++) |
---|
[103] | 138 | for(int j = 0 ; j < X_MAX ; j++){ |
---|
[105] | 139 | std::cout << "Passe " << i << j << " pour instanciation synthetic_init" << std::endl; |
---|
| 140 | std::ostringstream str0; |
---|
| 141 | std::ostringstream str1; |
---|
| 142 | str0 << "Initiator_c0_" << (i*X_MAX+j) ; |
---|
| 143 | str1 << "Initiator_c1_" << (i*X_MAX+j) ; |
---|
| 144 | new(&initiator_c0[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str0.str().c_str() , maptab0, IntTab(i*X_MAX+j,0), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); |
---|
| 145 | new(&initiator_c1[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str1.str().c_str() , maptab0, IntTab(i*X_MAX+j,0), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); |
---|
[103] | 146 | } |
---|
[99] | 147 | |
---|
[103] | 148 | soclib::caba::VciSimpleRam<vci_param> * ram_c0 = (soclib::caba::VciSimpleRam<vci_param> *) malloc(sizeof(soclib::caba::VciSimpleRam<vci_param>) * N_CLUSTERS); |
---|
| 149 | soclib::caba::VciSimpleRam<vci_param> * ram_c1 = (soclib::caba::VciSimpleRam<vci_param> *) malloc(sizeof(soclib::caba::VciSimpleRam<vci_param>) * N_CLUSTERS); |
---|
| 150 | for(int i = 0 ; i < Y_MAX ; i++) |
---|
| 151 | for(int j = 0 ; j < X_MAX ; j++){ |
---|
[105] | 152 | std::cout << "Passe " << i << j << " pour instanciation Ram" << std::endl; |
---|
| 153 | std::ostringstream str0; |
---|
| 154 | std::ostringstream str1; |
---|
| 155 | str0 << "Ram_c0_" << (i*X_MAX+j) ; |
---|
| 156 | str1 << "Ram_c1_" << (i*X_MAX+j) ; |
---|
| 157 | new(&ram_c0[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> (str0.str().c_str() , IntTab(i*X_MAX+j,0), maptab0, soclib::common::Loader(), 0); |
---|
| 158 | new(&ram_c1[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> (str1.str().c_str() , IntTab(i*X_MAX+j,0), maptab1, soclib::common::Loader(), 0); |
---|
[103] | 159 | } |
---|
| 160 | |
---|
[97] | 161 | /////////////////////////////////////////////////////////////// |
---|
| 162 | // Connection of Synthetic Initiator to each local ring per cluster |
---|
| 163 | /////////////////////////////////////////////////////////////// |
---|
| 164 | for(int i = 0 ; i < N_CLUSTERS ; i++){ |
---|
[99] | 165 | local_ring_c0[i].p_clk(signal_clk); |
---|
| 166 | local_ring_c0[i].p_resetn(signal_resetn); |
---|
[103] | 167 | local_ring_c0[i].p_to_initiator[0](signal_vci_ini_synth_c0[0][i]); |
---|
| 168 | local_ring_c0[i].p_to_target[0](signal_vci_ini_synth_c0[1][i]); |
---|
[99] | 169 | initiator_c0[i].p_clk(signal_clk); |
---|
| 170 | initiator_c0[i].p_resetn(signal_resetn); |
---|
[103] | 171 | initiator_c0[i].p_vci(signal_vci_ini_synth_c0[0][i]); |
---|
| 172 | ram_c0[i].p_clk(signal_clk); |
---|
| 173 | ram_c0[i].p_resetn(signal_resetn); |
---|
| 174 | ram_c0[i].p_vci(signal_vci_ini_synth_c0[1][i]); |
---|
[99] | 175 | local_ring_c1[i].p_clk(signal_clk); |
---|
| 176 | local_ring_c1[i].p_resetn(signal_resetn); |
---|
[103] | 177 | local_ring_c1[i].p_to_initiator[0](signal_vci_ini_synth_c1[0][i]); |
---|
| 178 | local_ring_c1[i].p_to_target[0](signal_vci_ini_synth_c1[1][i]); |
---|
[99] | 179 | initiator_c1[i].p_clk(signal_clk); |
---|
| 180 | initiator_c1[i].p_resetn(signal_resetn); |
---|
[103] | 181 | initiator_c1[i].p_vci(signal_vci_ini_synth_c1[0][i]); |
---|
| 182 | ram_c1[i].p_clk(signal_clk); |
---|
| 183 | ram_c1[i].p_resetn(signal_resetn); |
---|
| 184 | ram_c1[i].p_vci(signal_vci_ini_synth_c1[1][i]); |
---|
[97] | 185 | } |
---|
| 186 | |
---|
| 187 | /////////////////////////////////////////////////////////////// |
---|
[99] | 188 | // Connection of each VDspin Router to each local ring and |
---|
| 189 | // neighbors VDspin Router |
---|
[97] | 190 | /////////////////////////////////////////////////////////////// |
---|
| 191 | for(int i = 0; i < Y_MAX ; i++){ |
---|
| 192 | for(int j = 0; j < X_MAX ; j++){ |
---|
| 193 | routers_cmd[i][j].p_clk(signal_clk); |
---|
| 194 | routers_cmd[i][j].p_resetn(signal_resetn); |
---|
[99] | 195 | routers_rsp[i][j].p_clk(signal_clk); |
---|
| 196 | routers_rsp[i][j].p_resetn(signal_resetn); |
---|
| 197 | local_ring_c0[i*X_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c0[0][i][j][LOCAL]); |
---|
| 198 | local_ring_c0[i*X_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c0[1][i][j][LOCAL] ); |
---|
| 199 | local_ring_c0[i*X_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c0[0][i][j][LOCAL]); |
---|
| 200 | local_ring_c0[i*X_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c0[1][i][j][LOCAL] ); |
---|
| 201 | local_ring_c1[i*X_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c1[0][i][j][LOCAL]); |
---|
| 202 | local_ring_c1[i*X_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c1[1][i][j][LOCAL] ); |
---|
| 203 | local_ring_c1[i*X_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c1[0][i][j][LOCAL]); |
---|
| 204 | local_ring_c1[i*X_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c1[1][i][j][LOCAL] ); |
---|
[103] | 205 | for(int k = 0; k < 5; k++){ |
---|
[97] | 206 | if(i == 0){ |
---|
| 207 | if(j == 0){ |
---|
| 208 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); |
---|
| 209 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); |
---|
| 210 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); |
---|
| 211 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); |
---|
[99] | 212 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); |
---|
| 213 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); |
---|
| 214 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); |
---|
| 215 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); |
---|
[97] | 216 | } else { |
---|
[99] | 217 | if(k == WEST){ |
---|
| 218 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i][j-1][EAST]); |
---|
| 219 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i][j-1][EAST]); |
---|
| 220 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i][j-1][EAST]); |
---|
| 221 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i][j-1][EAST]); |
---|
| 222 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i][j-1][EAST]); |
---|
| 223 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i][j-1][EAST]); |
---|
| 224 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i][j-1][EAST]); |
---|
| 225 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i][j-1][EAST]); |
---|
| 226 | } else { |
---|
| 227 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); |
---|
| 228 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); |
---|
| 229 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); |
---|
| 230 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); |
---|
| 231 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); |
---|
| 232 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); |
---|
| 233 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); |
---|
| 234 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); |
---|
| 235 | } |
---|
[97] | 236 | } |
---|
| 237 | } else { |
---|
[99] | 238 | if(k == SOUTH){ |
---|
| 239 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i-1][j][NORTH]); |
---|
| 240 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i-1][j][NORTH]); |
---|
| 241 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i-1][j][NORTH]); |
---|
| 242 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i-1][j][NORTH]); |
---|
| 243 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i-1][j][NORTH]); |
---|
| 244 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i-1][j][NORTH]); |
---|
| 245 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i-1][j][NORTH]); |
---|
| 246 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i-1][j][NORTH]); |
---|
| 247 | } else if(k == WEST){ |
---|
| 248 | if(j == 0){ |
---|
| 249 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); |
---|
| 250 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); |
---|
| 251 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); |
---|
| 252 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); |
---|
| 253 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); |
---|
| 254 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); |
---|
| 255 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); |
---|
| 256 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); |
---|
| 257 | } else { |
---|
| 258 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i][j-1][EAST]); |
---|
| 259 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i][j-1][EAST]); |
---|
| 260 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i][j-1][EAST]); |
---|
| 261 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i][j-1][EAST]); |
---|
| 262 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i][j-1][EAST]); |
---|
| 263 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i][j-1][EAST]); |
---|
| 264 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i][j-1][EAST]); |
---|
| 265 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i][j-1][EAST]); |
---|
| 266 | } |
---|
| 267 | } else { |
---|
| 268 | routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); |
---|
| 269 | routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); |
---|
| 270 | routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); |
---|
| 271 | routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); |
---|
| 272 | routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); |
---|
| 273 | routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); |
---|
| 274 | routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); |
---|
| 275 | routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); |
---|
| 276 | } |
---|
[97] | 277 | } |
---|
| 278 | } |
---|
| 279 | } |
---|
| 280 | } |
---|
| 281 | |
---|
| 282 | //////////////////////////////////////////////////////// |
---|
| 283 | |
---|
| 284 | |
---|
| 285 | |
---|
| 286 | //////////////////////////////////////////////// |
---|
| 287 | // Simulation Loop // |
---|
| 288 | //////////////////////////////////////////////// |
---|
| 289 | int ncycles; |
---|
| 290 | |
---|
| 291 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 292 | signal_resetn = false; |
---|
| 293 | |
---|
| 294 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 295 | signal_resetn = true; |
---|
| 296 | |
---|
[105] | 297 | while(1) { |
---|
[97] | 298 | sc_start(sc_core::sc_time(100000, SC_NS)); |
---|
| 299 | } |
---|
| 300 | |
---|
| 301 | return EXIT_SUCCESS; |
---|
| 302 | } |
---|
| 303 | |
---|
| 304 | int sc_main (int argc, char *argv[]) |
---|
| 305 | { |
---|
| 306 | try { |
---|
| 307 | return _main(argc, argv); |
---|
| 308 | } catch (std::exception &e) { |
---|
| 309 | std::cout << e.what() << std::endl; |
---|
| 310 | } catch (...) { |
---|
| 311 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 312 | throw; |
---|
| 313 | } |
---|
| 314 | return 1; |
---|
| 315 | } |
---|