source: trunk/platforms/caba-vgmn-vcache2_memcache-mipsel/top.cpp@ 95

Last change on this file since 95 was 3, checked in by nipo, 17 years ago

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1
2#include <systemc>
3#include <sys/time.h>
4#include <iostream>
5#include <cstdlib>
6#include <cstdarg>
7
8#include "mapping_table.h"
9#include "mips32.h"
10#include "iss2_simhelper.h"
11#include "vci_simple_ram.h"
12#include "vci_multi_tty.h"
13#include "vci_vgmn.h"
14#include "vci_mem_cache.h"
15//#include "vci_cc_vcache_wrapper.h"
16#include "vci_cc_vcache_wrapper2.h"
17
18
19#ifdef USE_GDB_SERVER
20#include "iss/gdbserver.h"
21#endif
22
23#include "segmentation.h"
24
25int _main(int argc, char *argv[])
26{
27 using namespace sc_core;
28 // Avoid repeating these everywhere
29 using soclib::common::IntTab;
30 using soclib::common::Segment;
31
32 // Define VCI parameters
33 typedef soclib::caba::VciParams<4,8,32,1,1,1,14,4,4,1> vci_param;
34 typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
35 // Mapping table
36
37 soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
38
39 maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2), true));
40 maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2), true));
41 maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(2), true));
42 maptabp.add(Segment("tty" , TTY_BASE , TTY_SIZE , IntTab(1), false));
43 maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0)));
44 maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
45 //maptabp.add(Segment("ptba" , PTD_ADDR , TAB_SIZE , IntTab(0), false));
46 maptabp.add(Segment("ptba" , PTD_ADDR , TAB_SIZE , IntTab(2), true));
47
48 std::cout << maptabp << std::endl;
49
50 soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
51 maptabc.add(Segment("proc0" , PROC0_BASE , PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
52 maptabc.add(Segment("proc1" , PROC1_BASE , PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
53 std::cout << maptabc << std::endl;
54
55 soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
56 maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), true));
57 maptabx.add(Segment("ptba" , PTD_ADDR , TAB_SIZE , IntTab(0), true));
58 maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
59 maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
60 maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));
61
62 std::cout << maptabx << std::endl;
63
64 // Signals
65 sc_clock signal_clk("clk");
66 sc_signal<bool> signal_resetn("resetn");
67
68 sc_signal<bool> signal_proc0_it0("proc0_it0");
69 sc_signal<bool> signal_proc0_it1("proc0_it1");
70 sc_signal<bool> signal_proc0_it2("proc0_it2");
71 sc_signal<bool> signal_proc0_it3("proc0_it3");
72 sc_signal<bool> signal_proc0_it4("proc0_it4");
73 sc_signal<bool> signal_proc0_it5("proc0_it5");
74
75 sc_signal<bool> signal_proc1_it0("proc1_it0");
76 sc_signal<bool> signal_proc1_it1("proc1_it1");
77 sc_signal<bool> signal_proc1_it2("proc1_it2");
78 sc_signal<bool> signal_proc1_it3("proc1_it3");
79 sc_signal<bool> signal_proc1_it4("proc1_it4");
80 sc_signal<bool> signal_proc1_it5("proc1_it5");
81
82 soclib::caba::VciSignals<vci_param> signal_vci_ini_proc0("vci_ini_proc0");
83 soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
84
85 soclib::caba::VciSignals<vci_param> signal_vci_ini_proc1("vci_ini_proc1");
86 soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
87
88 soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
89
90 soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
91
92 soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
93
94 soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
95 soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
96 soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
97
98 sc_signal<bool> signal_tty_irq0("signal_tty_irq0");
99 sc_signal<bool> signal_tty_irq1("signal_tty_irq1");
100
101 // Components
102 // VCI ports indexation : 3 intiateurs et 5 cibles
103
104 // INIT0 : proc_ini
105 // INIT1 : memc_ini
106 // INIT2 : memc_ixr
107
108 // TGT 0 : rom_tgt
109 // TGT 1 : tty_tgt
110 // TGT 2 : xram_tgt
111 // TGT 3 : memc_tgt
112 // TGT 4 : proc_tgt
113
114 soclib::common::Loader loader("soft/bin.soft");
115/*
116 soclib::caba::VciCcVCacheWrapper<vci_param, proc_iss >
117 proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),4,16,4,16,4,64,16,4,64,16,16);
118
119 soclib::caba::VciCcVCacheWrapper<vci_param, proc_iss >
120 proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),4,16,4,16,4,64,16,4,64,16,16);
121*/
122 soclib::caba::VciCcVCacheWrapper2<vci_param, proc_iss >
123 proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),4,16,4,16,4,64,16,4,64,16,16);
124
125 soclib::caba::VciCcVCacheWrapper2<vci_param, proc_iss >
126 proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),4,16,4,16,4,64,16,4,64,16,16);
127
128 soclib::caba::VciSimpleRam<vci_param>
129 rom("rom", IntTab(0), maptabp, loader);
130
131 soclib::caba::VciSimpleRam<vci_param>
132 xram("xram", IntTab(0), maptabx, loader);
133
134 soclib::caba::VciMemCache<vci_param>
135 memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(0),IntTab(2),16,256,16);
136
137 soclib::caba::VciMultiTty<vci_param>
138 tty("tty",IntTab(1),maptabp,"tty0","tty1",NULL);
139
140 soclib::caba::VciVgmn<vci_param>
141 vgmnp("vgmnp",maptabp, 2, 3, 1, 8);
142
143 soclib::caba::VciVgmn<vci_param>
144 vgmnc("vgmnc",maptabc, 1, 2, 1, 8);
145
146 soclib::caba::VciVgmn<vci_param>
147 vgmnx("vgmnx",maptabx, 1, 1, 1, 8);
148
149 // Net-List
150
151 proc0.p_clk(signal_clk);
152 proc0.p_resetn(signal_resetn);
153 proc0.p_irq[0](signal_proc0_it0);
154 proc0.p_irq[1](signal_proc0_it1);
155 proc0.p_irq[2](signal_proc0_it2);
156 proc0.p_irq[3](signal_proc0_it3);
157 proc0.p_irq[4](signal_proc0_it4);
158 proc0.p_irq[5](signal_proc0_it5);
159 proc0.p_vci_ini(signal_vci_ini_proc0);
160 proc0.p_vci_tgt(signal_vci_tgt_proc0);
161
162 proc1.p_clk(signal_clk);
163 proc1.p_resetn(signal_resetn);
164 proc1.p_irq[0](signal_proc1_it0);
165 proc1.p_irq[1](signal_proc1_it1);
166 proc1.p_irq[2](signal_proc1_it2);
167 proc1.p_irq[3](signal_proc1_it3);
168 proc1.p_irq[4](signal_proc1_it4);
169 proc1.p_irq[5](signal_proc1_it5);
170 proc1.p_vci_ini(signal_vci_ini_proc1);
171 proc1.p_vci_tgt(signal_vci_tgt_proc1);
172
173 rom.p_clk(signal_clk);
174 rom.p_resetn(signal_resetn);
175 rom.p_vci(signal_vci_tgt_rom);
176
177 tty.p_clk(signal_clk);
178 tty.p_resetn(signal_resetn);
179 tty.p_vci(signal_vci_tgt_tty);
180 tty.p_irq[0](signal_tty_irq0);
181 tty.p_irq[1](signal_tty_irq1);
182
183 memc.p_clk(signal_clk);
184 memc.p_resetn(signal_resetn);
185 memc.p_vci_tgt(signal_vci_tgt_memc);
186 memc.p_vci_ini(signal_vci_ini_memc);
187 memc.p_vci_ixr(signal_vci_ixr_memc);
188
189 xram.p_clk(signal_clk);
190 xram.p_resetn(signal_resetn);
191 xram.p_vci(signal_vci_tgt_xram);
192
193 vgmnp.p_clk(signal_clk);
194 vgmnp.p_resetn(signal_resetn);
195
196 vgmnc.p_clk(signal_clk);
197 vgmnc.p_resetn(signal_resetn);
198
199 vgmnx.p_clk(signal_clk);
200 vgmnx.p_resetn(signal_resetn);
201
202 vgmnp.p_to_initiator[0](signal_vci_ini_proc0);
203 vgmnp.p_to_initiator[1](signal_vci_ini_proc1);
204 vgmnc.p_to_initiator[0](signal_vci_ini_memc);
205 vgmnx.p_to_initiator[0](signal_vci_ixr_memc);
206
207 vgmnp.p_to_target[0](signal_vci_tgt_rom);
208 vgmnp.p_to_target[1](signal_vci_tgt_tty);
209 vgmnp.p_to_target[2](signal_vci_tgt_memc);
210
211 vgmnc.p_to_target[0](signal_vci_tgt_proc0);
212 vgmnc.p_to_target[1](signal_vci_tgt_proc1);
213 vgmnx.p_to_target[0](signal_vci_tgt_xram);
214
215 int ncycles;
216
217#ifndef SOCVIEW
218 if (argc == 2) {
219 ncycles = std::atoi(argv[1]);
220 } else {
221 std::cerr
222 << std::endl
223 << "The number of simulation cycles must "
224 "be defined in the command line"
225 << std::endl;
226 exit(1);
227 }
228
229 sc_start(sc_core::sc_time(0, SC_NS));
230 signal_resetn = false;
231
232 sc_start(sc_core::sc_time(1, SC_NS));
233 signal_resetn = true;
234
235 for (int i = 0; i < ncycles ; i+=1000) {
236 sc_start(sc_core::sc_time(1000, SC_NS));
237 //proc.print_stats();
238 //memc.print_stats();
239 }
240 return EXIT_SUCCESS;
241#else
242 ncycles = 1;
243 sc_start(sc_core::sc_time(0, SC_NS));
244 signal_resetn = false;
245 sc_start(sc_core::sc_time(1, SC_NS));
246 signal_resetn = true;
247
248 debug();
249 return EXIT_SUCCESS;
250#endif
251}
252
253int sc_main (int argc, char *argv[])
254{
255 try {
256 return _main(argc, argv);
257 } catch (std::exception &e) {
258 std::cout << e.what() << std::endl;
259 } catch (...) {
260 std::cout << "Unknown exception occured" << std::endl;
261 throw;
262 }
263 return 1;
264}
265
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