| 1 | |
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| 2 | __doc__ = ''' |
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| 3 | This file is a Cluster library. It contains classes implementing the |
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| 4 | netlist of a cluster, for different tsar versions. |
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| 5 | ''' |
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| 6 | |
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| 7 | class Cluster: |
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| 8 | ''' |
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| 9 | A generic netlist of a cluster, which must be subclassed to |
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| 10 | implement caches&dma instanciation |
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| 11 | ''' |
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| 12 | |
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| 13 | def __init__(self, pf, ringp, mtp, proc_count, cluster_no, cluster_base): |
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| 14 | self.pf = pf |
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| 15 | self.ringp = ringp |
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| 16 | self.mtp = mtp |
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| 17 | self.cluster_no = cluster_no |
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| 18 | |
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| 19 | self.generate(proc_count, cluster_base) |
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| 20 | |
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| 21 | def generate(self, proc_count, cluster_base): |
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| 22 | ''' |
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| 23 | The core netlist, where caches and components are created |
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| 24 | ''' |
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| 25 | self.cpu = [] |
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| 26 | for i in range(proc_count): |
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| 27 | c = self.create_cpu(i, |
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| 28 | cluster_base |
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| 29 | + 0x10200000 |
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| 30 | + 0x01000000 * (i+1) |
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| 31 | ) |
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| 32 | self.cpu.append(c) |
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| 33 | |
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| 34 | xram = self.create_ram( segments = [(cluster_base, 0x02000000)] ) |
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| 35 | rom = self.create_rom( segments = [(0xbfc00000, 0x00400000)] ) |
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| 36 | tty = self.create_tty( addr = 0xd0200000 ) |
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| 37 | dma = self.create_dma( addr = 0xd1200000 ) |
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| 38 | xicu = self.create_xicu( addr = 0xd2200000, hwi_count = 3, cpu_count = proc_count ) |
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| 39 | |
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| 40 | xicu.hwi[0] // tty.irq[0] |
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| 41 | xicu.hwi[1] // dma.irq |
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| 42 | |
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| 43 | for p, cpu in enumerate(self.cpu): |
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| 44 | for i in range(6): |
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| 45 | xicu.irq[i+p*6] // cpu.irq[i] |
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| 46 | |
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| 47 | def create_rom(self, segments): |
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| 48 | name = 'rom%d'%self.cluster_no |
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| 49 | rom = self.pf.create('caba:vci_simple_ram', name, latency = 1) |
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| 50 | self.ringp.to_target.new() // rom.vci |
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| 51 | for addr, size in segments: |
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| 52 | rom.addSegment(name, address = addr, size = size, cacheable = True) |
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| 53 | return rom |
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| 54 | |
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| 55 | def create_ram(self, segments): |
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| 56 | name = 'ram%d'%self.cluster_no |
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| 57 | ram = self.pf.create('caba:vci_simple_ram', name, latency = 1) |
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| 58 | self.ringp.to_target.new() // ram.vci |
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| 59 | for addr, size in segments: |
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| 60 | ram.addSegment(name, address = addr, size = size, cacheable = True) |
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| 61 | return ram |
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| 62 | |
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| 63 | def create_tty(self, addr): |
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| 64 | name = 'tty%d'%self.cluster_no |
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| 65 | tty = self.pf.create('caba:vci_multi_tty', name, names = ['tty0']) |
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| 66 | self.ringp.to_target.new() // tty.vci |
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| 67 | tty.addSegment(name, address = addr, size = 0x10, cacheable = False) |
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| 68 | return tty |
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| 69 | |
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| 70 | def create_xicu(self, addr, hwi_count, cpu_count): |
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| 71 | name = 'xicu%d'%self.cluster_no |
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| 72 | xicu = self.pf.create('caba:vci_xicu', name, |
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| 73 | pti_count = cpu_count, |
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| 74 | hwi_count = hwi_count, |
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| 75 | wti_count = cpu_count, |
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| 76 | irq_count = 6*cpu_count, |
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| 77 | ) |
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| 78 | self.ringp.to_target.new() // xicu.vci |
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| 79 | xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False) |
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| 80 | return xicu |
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| 81 | |
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| 82 | def create_cpu(self, cpuid, addr): |
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| 83 | c = self.pf.create( |
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| 84 | 'caba:vci_vcache_wrapper2', |
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| 85 | 'proc_%d_%d' % (self.cluster_no, cpuid), |
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| 86 | iss_t = "common:mips32el", |
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| 87 | proc_id = cpuid, |
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| 88 | icache_ways = 4, |
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| 89 | icache_sets = 64, |
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| 90 | icache_words = 16, |
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| 91 | itlb_ways = 4, |
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| 92 | itlb_sets = 16, |
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| 93 | dcache_ways = 4, |
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| 94 | dcache_sets = 64, |
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| 95 | dcache_words = 16, |
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| 96 | dtlb_ways = 4, |
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| 97 | dtlb_sets = 16, |
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| 98 | write_buf_size = 16, |
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| 99 | ) |
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| 100 | self.ringp.to_initiator.new() // c.vci |
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| 101 | return c |
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| 102 | |
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| 103 | def create_dma(self, addr): |
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| 104 | name = 'dma%d'%self.cluster_no |
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| 105 | dma = self.pf.create('caba:vci_dma', name, burst_size = 64) |
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| 106 | self.ringp.to_target.new() // dma.vci_target |
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| 107 | self.ringp.to_initiator.new() // dma.vci_initiator |
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| 108 | dma.addSegment(name, address = addr, size = 0x14, cacheable = False) |
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| 109 | return dma |
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