[93] | 1 | ; Copyright 1991-2009 Mentor Graphics Corporation |
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| 2 | ; |
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| 3 | ; All Rights Reserved. |
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| 4 | ; |
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| 5 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF |
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| 6 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
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| 7 | ; |
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| 8 | |
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| 9 | [Library] |
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| 10 | others = $MODEL_TECH/../modelsim.ini |
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| 11 | ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release |
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| 12 | ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release |
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| 13 | ;mvc_lib = $MODEL_TECH/../mvc_lib |
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| 14 | |
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| 15 | work = work |
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| 16 | [vcom] |
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| 17 | ; VHDL93 variable selects language version as the default. |
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| 18 | ; Default is VHDL-2002. |
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| 19 | ; Value of 0 or 1987 for VHDL-1987. |
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| 20 | ; Value of 1 or 1993 for VHDL-1993. |
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| 21 | ; Default or value of 2 or 2002 for VHDL-2002. |
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| 22 | ; Value of 3 or 2008 for VHDL-2008 |
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| 23 | VHDL93 = 2002 |
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| 24 | |
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| 25 | ; Show source line containing error. Default is off. |
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| 26 | ; Show_source = 1 |
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| 27 | |
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| 28 | ; Turn off unbound-component warnings. Default is on. |
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| 29 | ; Show_Warning1 = 0 |
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| 30 | |
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| 31 | ; Turn off process-without-a-wait-statement warnings. Default is on. |
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| 32 | ; Show_Warning2 = 0 |
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| 33 | |
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| 34 | ; Turn off null-range warnings. Default is on. |
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| 35 | ; Show_Warning3 = 0 |
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| 36 | |
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| 37 | ; Turn off no-space-in-time-literal warnings. Default is on. |
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| 38 | ; Show_Warning4 = 0 |
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| 39 | |
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| 40 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. |
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| 41 | ; Show_Warning5 = 0 |
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| 42 | |
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| 43 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. |
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| 44 | ; Optimize_1164 = 0 |
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| 45 | |
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| 46 | ; Turn on resolving of ambiguous function overloading in favor of the |
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| 47 | ; "explicit" function declaration (not the one automatically created by |
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| 48 | ; the compiler for each type declaration). Default is off. |
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| 49 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned |
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| 50 | ; will match the behavior of synthesis tools. |
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| 51 | Explicit = 1 |
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| 52 | |
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| 53 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. |
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| 54 | ; NoVital = 1 |
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| 55 | |
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| 56 | ; Turn off VITAL compliance checking. Default is checking on. |
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| 57 | ; NoVitalCheck = 1 |
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| 58 | |
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| 59 | ; Ignore VITAL compliance checking errors. Default is to not ignore. |
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| 60 | ; IgnoreVitalErrors = 1 |
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| 61 | |
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| 62 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. |
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| 63 | ; Show_VitalChecksWarnings = 0 |
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| 64 | |
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| 65 | ; Turn off PSL assertion warning messages. Default is to show warnings. |
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| 66 | ; Show_PslChecksWarnings = 0 |
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| 67 | |
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| 68 | ; Enable parsing of embedded PSL assertions. Default is enabled. |
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| 69 | ; EmbeddedPsl = 0 |
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| 70 | |
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| 71 | ; Keep silent about case statement static warnings. |
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| 72 | ; Default is to give a warning. |
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| 73 | ; NoCaseStaticError = 1 |
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| 74 | |
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| 75 | ; Keep silent about warnings caused by aggregates that are not locally static. |
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| 76 | ; Default is to give a warning. |
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| 77 | ; NoOthersStaticError = 1 |
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| 78 | |
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| 79 | ; Treat as errors: |
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| 80 | ; case statement static warnings |
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| 81 | ; warnings caused by aggregates that are not locally static |
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| 82 | ; Overrides NoCaseStaticError, NoOthersStaticError settings. |
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| 83 | ; PedanticErrors = 1 |
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| 84 | |
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| 85 | ; Turn off inclusion of debugging info within design units. |
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| 86 | ; Default is to include debugging info. |
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| 87 | ; NoDebug = 1 |
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| 88 | |
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| 89 | ; Turn off "Loading..." messages. Default is messages on. |
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| 90 | ; Quiet = 1 |
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| 91 | |
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| 92 | ; Turn on some limited synthesis rule compliance checking. Checks only: |
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| 93 | ; -- signals used (read) by a process must be in the sensitivity list |
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| 94 | ; CheckSynthesis = 1 |
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| 95 | |
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| 96 | ; Activate optimizations on expressions that do not involve signals, |
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| 97 | ; waits, or function/procedure/task invocations. Default is off. |
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| 98 | ; ScalarOpts = 1 |
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| 99 | |
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| 100 | ; Turns on lint-style checking. |
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| 101 | ; Show_Lint = 1 |
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| 102 | |
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| 103 | ; Require the user to specify a configuration for all bindings, |
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| 104 | ; and do not generate a compile time default binding for the |
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| 105 | ; component. This will result in an elaboration error of |
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| 106 | ; 'component not bound' if the user fails to do so. Avoids the rare |
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| 107 | ; issue of a false dependency upon the unused default binding. |
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| 108 | ; RequireConfigForAllDefaultBinding = 1 |
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| 109 | |
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| 110 | ; Perform default binding at compile time. |
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| 111 | ; Default is to do default binding at load time. |
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| 112 | ; BindAtCompile = 1; |
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| 113 | |
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| 114 | ; Inhibit range checking on subscripts of arrays. Range checking on |
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| 115 | ; scalars defined with subtypes is inhibited by default. |
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| 116 | ; NoIndexCheck = 1 |
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| 117 | |
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| 118 | ; Inhibit range checks on all (implicit and explicit) assignments to |
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| 119 | ; scalar objects defined with subtypes. |
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| 120 | ; NoRangeCheck = 1 |
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| 121 | |
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| 122 | ; Run the 0-in compiler on the VHDL source files |
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| 123 | ; Default is off. |
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| 124 | ; ZeroIn = 1 |
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| 125 | |
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| 126 | ; Set the options to be passed to the 0-in compiler. |
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| 127 | ; Default is "". |
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| 128 | ; ZeroInOptions = "" |
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| 129 | |
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| 130 | ; Turn on code coverage in VHDL design units. Default is off. |
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| 131 | ; Coverage = sbceft |
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| 132 | |
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| 133 | ; Turn off code coverage in VHDL subprograms. Default is on. |
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| 134 | ; CoverageSub = 0 |
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| 135 | |
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| 136 | ; Automatically exclude VHDL case statement default branches. |
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| 137 | ; Default is to not exclude. |
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| 138 | ; CoverExcludeDefault = 1 |
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| 139 | |
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| 140 | ; Control compiler and VOPT optimizations that are allowed when |
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| 141 | ; code coverage is on. Refer to the comment for this in the [vlog] area. |
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| 142 | ; CoverOpt = 3 |
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| 143 | |
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| 144 | ; Inform code coverage optimizations to respect VHDL 'H' and 'L' |
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| 145 | ; values on signals in conditions and expressions, and to not automatically |
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| 146 | ; convert them to '1' and '0'. Default is to not convert. |
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| 147 | ; CoverRespectHandL = 0 |
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| 148 | |
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| 149 | ; Increase or decrease the maximum number of rows allowed in a UDP table |
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| 150 | ; implementing a VHDL condition coverage or expression coverage expression. |
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| 151 | ; More rows leads to a longer compile time, but more expressions covered. |
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| 152 | ; CoverMaxUDPRows = 192 |
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| 153 | |
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| 154 | ; Increase or decrease the maximum number of input patterns that are present |
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| 155 | ; in FEC table. This leads to a longer compile time with more expressions |
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| 156 | ; covered with FEC metric. |
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| 157 | ; CoverMaxFECRows = 192 |
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| 158 | |
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| 159 | ; Enable or disable Focused Expression Coverage analysis for conditions and |
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| 160 | ; expressions. Focused Expression Coverage data is provided by default when |
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| 161 | ; expression and/or condition coverage is active. |
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| 162 | ; CoverFEC = 0 |
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| 163 | |
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| 164 | ; Enable or disable short circuit evaluation of conditions and expressions when |
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| 165 | ; condition or expression coverage is active. Short circuit evaluation is enabled |
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| 166 | ; by default. |
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| 167 | ; CoverShortCircuit = 0 |
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| 168 | |
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| 169 | ; Use this directory for compiler temporary files instead of "work/_temp" |
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| 170 | ; CompilerTempDir = /tmp |
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| 171 | |
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| 172 | ; Set this to cause the compilers to force data to be committed to disk |
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| 173 | ; when the files are closed. |
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| 174 | ; SyncCompilerFiles = 1 |
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| 175 | |
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| 176 | ; Add VHDL-AMS declarations to package STANDARD |
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| 177 | ; Default is not to add |
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| 178 | ; AmsStandard = 1 |
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| 179 | |
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| 180 | ; Range and length checking will be performed on array indices and discrete |
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| 181 | ; ranges, and when violations are found within subprograms, errors will be |
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| 182 | ; reported. Default is to issue warnings for violations, because subprograms |
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| 183 | ; may not be invoked. |
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| 184 | ; NoDeferSubpgmCheck = 0 |
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| 185 | |
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| 186 | ; Turn off detection of FSMs having single bit current state variable. |
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| 187 | ; FsmSingle = 0 |
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| 188 | |
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| 189 | ; Turn off reset state transitions in FSM. |
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| 190 | ; FsmResetTrans = 0 |
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| 191 | |
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| 192 | ; Do not show immediate assertions with constant expressions in |
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| 193 | ; GUI/report/UCDB etc. By default immediate assertions with constant |
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| 194 | ; expressions are shown in GUI/report/UCDB etc. This does not affect ; |
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| 195 | ; evaluation of immediate assertions. |
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| 196 | ; ShowConstantImmediateAsserts = 0 |
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| 197 | |
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| 198 | [vlog] |
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| 199 | ; Turn off inclusion of debugging info within design units. |
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| 200 | ; Default is to include debugging info. |
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| 201 | ; NoDebug = 1 |
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| 202 | |
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| 203 | ; Turn on `protect compiler directive processing. |
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| 204 | ; Default is to ignore `protect directives. |
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| 205 | ; Protect = 1 |
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| 206 | |
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| 207 | ; Turn off "Loading..." messages. Default is messages on. |
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| 208 | ; Quiet = 1 |
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| 209 | |
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| 210 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). |
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| 211 | ; Default is off. |
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| 212 | ; Hazard = 1 |
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| 213 | |
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| 214 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case |
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| 215 | ; insensitivity for module names. Default is no conversion. |
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| 216 | ; UpCase = 1 |
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| 217 | |
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| 218 | ; Activate optimizations on expressions that do not involve signals, |
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| 219 | ; waits, or function/procedure/task invocations. Default is off. |
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| 220 | ; ScalarOpts = 1 |
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| 221 | |
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| 222 | ; Turns on lint-style checking. |
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| 223 | ; Show_Lint = 1 |
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| 224 | |
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| 225 | ; Show source line containing error. Default is off. |
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| 226 | ; Show_source = 1 |
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| 227 | |
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| 228 | ; Turn on bad option warning. Default is off. |
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| 229 | ; Show_BadOptionWarning = 1 |
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| 230 | |
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| 231 | ; Revert back to IEEE 1364-1995 syntax, default is 0 (off). |
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| 232 | ; vlog95compat = 1 |
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| 233 | |
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| 234 | ; Turn off PSL warning messages. Default is to show warnings. |
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| 235 | ; Show_PslChecksWarnings = 0 |
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| 236 | |
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| 237 | ; Enable parsing of embedded PSL assertions. Default is enabled. |
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| 238 | ; EmbeddedPsl = 0 |
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| 239 | |
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| 240 | ; Set the threshold for automatically identifying sparse Verilog memories. |
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| 241 | ; A memory with depth equal to or more than the sparse memory threshold gets |
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| 242 | ; marked as sparse automatically, unless specified otherwise in source code |
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| 243 | ; or by +nosparse commandline option of vlog or vopt. |
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| 244 | ; The default is 1M. (i.e. memories with depth equal |
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| 245 | ; to or greater than 1M are marked as sparse) |
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| 246 | ; SparseMemThreshold = 1048576 |
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| 247 | |
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| 248 | ; Run the 0-in compiler on the Verilog source files |
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| 249 | ; Default is off. |
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| 250 | ; ZeroIn = 1 |
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| 251 | |
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| 252 | ; Set the options to be passed to the 0-in compiler. |
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| 253 | ; Default is "". |
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| 254 | ; ZeroInOptions = "" |
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| 255 | |
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| 256 | ; Set the option to treat all files specified in a vlog invocation as a |
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| 257 | ; single compilation unit. The default value is set to 0 which will treat |
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| 258 | ; each file as a separate compilation unit as specified in the P1800 draft standard. |
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| 259 | ; MultiFileCompilationUnit = 1 |
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| 260 | |
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| 261 | ; Turn on code coverage in Verilog design units. Default is off. |
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| 262 | ; Coverage = sbceft |
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| 263 | |
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| 264 | ; Automatically exclude Verilog case statement default branches. |
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| 265 | ; Default is to not automatically exclude defaults. |
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| 266 | ; CoverExcludeDefault = 1 |
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| 267 | |
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| 268 | ; Increase or decrease the maximum number of rows allowed in a UDP table |
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| 269 | ; implementing a Verilog condition coverage or expression coverage expression. |
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| 270 | ; More rows leads to a longer compile time, but more expressions covered. |
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| 271 | ; CoverMaxUDPRows = 192 |
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| 272 | |
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| 273 | ; Increase or decrease the maximum number of input patterns that are present |
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| 274 | ; in FEC table. This leads to a longer compile time with more expressions |
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| 275 | ; covered with FEC metric. |
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| 276 | ; CoverMaxFECRows = 192 |
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| 277 | |
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| 278 | ; Enable or disable Focused Expression Coverage analysis for conditions and |
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| 279 | ; expressions. Focused Expression Coverage data is provided by default when |
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| 280 | ; expression and/or condition coverage is active. |
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| 281 | ; CoverFEC = 0 |
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| 282 | |
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| 283 | ; Enable or disable short circuit evaluation of conditions and expressions when |
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| 284 | ; condition or expression coverage is active. Short circuit evaluation is enabled |
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| 285 | ; by default. |
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| 286 | ; CoverShortCircuit = 0 |
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| 287 | |
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| 288 | |
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| 289 | ; Turn on code coverage in VLOG `celldefine modules and modules included |
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| 290 | ; using vlog -v and -y. Default is off. |
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| 291 | ; CoverCells = 1 |
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| 292 | |
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| 293 | ; Control compiler and VOPT optimizations that are allowed when |
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| 294 | ; code coverage is on. This is a number from 1 to 4, with the following |
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| 295 | ; meanings (the default is 3): |
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| 296 | ; 1 -- Turn off all optimizations that affect coverage reports. |
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| 297 | ; 2 -- Allow optimizations that allow large performance improvements |
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| 298 | ; by invoking sequential processes only when the data changes. |
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| 299 | ; This may make major reductions in coverage counts. |
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| 300 | ; 3 -- In addition, allow optimizations that may change expressions or |
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| 301 | ; remove some statements. Allow constant propagation. Allow VHDL |
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| 302 | ; subprogram inlining and VHDL FF recognition. |
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| 303 | ; 4 -- In addition, allow optimizations that may remove major regions of |
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| 304 | ; code by changing assignments to built-ins or removing unused |
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| 305 | ; signals. Change Verilog gates to continuous assignments. |
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| 306 | ; CoverOpt = 3 |
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| 307 | |
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| 308 | ; Specify the override for the default value of "cross_num_print_missing" |
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| 309 | ; option for the Cross in Covergroups. If not specified then LRM default |
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| 310 | ; value of 0 (zero) is used. This is a compile time option. |
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| 311 | ; SVCrossNumPrintMissingDefault = 0 |
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| 312 | |
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| 313 | ; Setting following to 1 would cause creation of variables which |
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| 314 | ; would represent the value of Coverpoint expressions. This is used |
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| 315 | ; in conjunction with "SVCoverpointExprVariablePrefix" option |
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| 316 | ; in the modelsim.ini |
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| 317 | ; EnableSVCoverpointExprVariable = 0 |
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| 318 | |
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| 319 | ; Specify the override for the prefix used in forming the variable names |
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| 320 | ; which represent the Coverpoint expressions. This is used in conjunction with |
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| 321 | ; "EnableSVCoverpointExprVariable" option of the modelsim.ini |
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| 322 | ; The default prefix is "expr". |
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| 323 | ; The variable name is |
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| 324 | ; variable name => <prefix>_<coverpoint name> |
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| 325 | ; SVCoverpointExprVariablePrefix = expr |
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| 326 | |
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| 327 | ; Override for the default value of the SystemVerilog covergroup, |
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| 328 | ; coverpoint, and cross option.goal (defined to be 100 in the LRM). |
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| 329 | ; NOTE: It does not override specific assignments in SystemVerilog |
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| 330 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" |
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| 331 | ; in the [vsim] section can override this value. |
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| 332 | ; SVCovergroupGoalDefault = 100 |
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| 333 | |
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| 334 | ; Override for the default value of the SystemVerilog covergroup, |
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| 335 | ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) |
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| 336 | ; NOTE: It does not override specific assignments in SystemVerilog |
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| 337 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" |
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| 338 | ; in the [vsim] section can override this value. |
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| 339 | ; SVCovergroupTypeGoalDefault = 100 |
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| 340 | |
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| 341 | ; Specify the override for the default value of "strobe" option for the |
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| 342 | ; Covergroup Type. This is a compile time option which forces "strobe" to |
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| 343 | ; a user specified default value and supersedes SystemVerilog specified |
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| 344 | ; default value of '0'(zero). NOTE: This can be overriden by a runtime |
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| 345 | ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. |
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| 346 | ; SVCovergroupStrobeDefault = 0 |
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| 347 | |
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| 348 | ; Specify the override for the default value of "merge_instances" option for |
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| 349 | ; the Covergroup Type. This is a compile time option which forces |
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| 350 | ; "merge_instances" to a user specified default value and supersedes |
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| 351 | ; SystemVerilog specified default value of '0'(zero). |
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| 352 | ; SVCovergroupMergeInstancesDefault = 0 |
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| 353 | |
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| 354 | ; Specify the override for the default value of "per_instance" option for the |
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| 355 | ; Covergroup variables. This is a compile time option which forces "per_instance" |
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| 356 | ; to a user specified default value and supersedes SystemVerilog specified |
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| 357 | ; default value of '0'(zero). |
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| 358 | ; SVCovergroupPerInstanceDefault = 0 |
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| 359 | |
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| 360 | ; Specify the override for the default value of "get_inst_coverage" option for the |
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| 361 | ; Covergroup variables. This is a compile time option which forces |
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| 362 | ; "get_inst_coverage" to a user specified default value and supersedes |
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| 363 | ; SystemVerilog specified default value of '0'(zero). |
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| 364 | ; SVCovergroupGetInstCoverageDefault = 0 |
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| 365 | |
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| 366 | ; |
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| 367 | ; A space separated list of resource libraries that contain precompiled |
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| 368 | ; packages. The behavior is identical to using the "-L" switch. |
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| 369 | ; |
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| 370 | ; LibrarySearchPath = <path/lib> [<path/lib> ...] |
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| 371 | LibrarySearchPath = mtiAvm mtiOvm mtiUPF |
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| 372 | |
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| 373 | ; The behavior is identical to the "-mixedansiports" switch. Default is off. |
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| 374 | ; MixedAnsiPorts = 1 |
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| 375 | |
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| 376 | ; Enable SystemVerilog 3.1a $typeof() function. Default is off. |
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| 377 | ; EnableTypeOf = 1 |
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| 378 | |
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| 379 | ; Only allow lower case pragmas. Default is disabled. |
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| 380 | ; AcceptLowerCasePragmaOnly = 1 |
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| 381 | |
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| 382 | ; Set the maximum depth permitted for a recursive include file nesting. |
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| 383 | ; IncludeRecursionDepthMax = 5 |
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| 384 | |
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| 385 | ; Turn off detection of FSMs having single bit current state variable. |
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| 386 | ; FsmSingle = 0 |
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| 387 | |
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| 388 | ; Turn off reset state transitions in FSM. |
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| 389 | ; FsmResetTrans = 0 |
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| 390 | |
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| 391 | ; Turn off detections of FSMs having x-assignment. |
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| 392 | ; FsmXAssign = 0 |
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| 393 | |
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| 394 | ; List of file suffixes which will be read as SystemVerilog. White space |
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| 395 | ; in extensions can be specified with a back-slash: "\ ". Back-slashes |
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| 396 | ; can be specified with two consecutive back-slashes: "\\"; |
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| 397 | ; SVFileExtensions = sv svp svh |
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| 398 | |
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| 399 | ; This setting is the same as the vlog -sv command line switch. |
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| 400 | ; Enables SystemVerilog features and keywords when true (1). |
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| 401 | ; When false (0), the rules of IEEE Std 1364-2001 are followed and |
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| 402 | ; SystemVerilog keywords are ignored. |
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| 403 | ; Svlog = 0 |
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| 404 | |
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| 405 | ; Prints attribute placed upon SV packages during package import |
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| 406 | ; when true (1). The attribute will be ignored when this |
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| 407 | ; entry is false (0). The attribute name is "package_load_message". |
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| 408 | ; The value of this attribute is a string literal. |
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| 409 | ; Default is true (1). |
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| 410 | ; PrintSVPackageLoadingAttribute = 1 |
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| 411 | |
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| 412 | ; Do not show immediate assertions with constant expressions in |
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| 413 | ; GUI/reports/UCDB etc. By default immediate assertions with constant |
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| 414 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect |
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| 415 | ; evaluation of immediate assertions. |
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| 416 | ; ShowConstantImmediateAsserts = 0 |
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| 417 | |
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| 418 | [sccom] |
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| 419 | ; Enable use of SCV include files and library. Default is off. |
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| 420 | ; UseScv = 1 |
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| 421 | |
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| 422 | ; Add C++ compiler options to the sccom command line by using this variable. |
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| 423 | ; CppOptions = -g |
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| 424 | |
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| 425 | ; Use custom C++ compiler located at this path rather than the default path. |
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| 426 | ; The path should point directly at a compiler executable. |
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| 427 | ; CppPath = /usr/bin/g++ |
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| 428 | |
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| 429 | ; Enable verbose messages from sccom. Default is off. |
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| 430 | ; SccomVerbose = 1 |
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| 431 | |
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| 432 | ; sccom logfile. Default is no logfile. |
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| 433 | ; SccomLogfile = sccom.log |
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| 434 | |
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| 435 | ; Enable use of SC_MS include files and library. Default is off. |
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| 436 | ; UseScMs = 1 |
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| 437 | |
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| 438 | [vopt] |
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| 439 | ; Turn on code coverage in vopt. Default is off. |
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| 440 | ; Coverage = sbceft |
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| 441 | |
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| 442 | ; Control compiler optimizations that are allowed when |
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| 443 | ; code coverage is on. Refer to the comment for this in the [vlog] area. |
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| 444 | ; CoverOpt = 3 |
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| 445 | |
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| 446 | ; Increase or decrease the maximum number of rows allowed in a UDP table |
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| 447 | ; implementing a vopt condition coverage or expression coverage expression. |
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| 448 | ; More rows leads to a longer compile time, but more expressions covered. |
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| 449 | ; CoverMaxUDPRows = 192 |
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| 450 | |
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| 451 | ; Increase or decrease the maximum number of input patterns that are present |
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| 452 | ; in FEC table. This leads to a longer compile time with more expressions |
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| 453 | ; covered with FEC metric. |
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| 454 | ; CoverMaxFECRows = 192 |
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| 455 | |
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| 456 | ; Do not show immediate assertions with constant expressions in |
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| 457 | ; GUI/reports/UCDB etc. By default immediate assertions with constant |
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| 458 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect |
---|
| 459 | ; evaluation of immediate assertions. |
---|
| 460 | ; ShowConstantImmediateAsserts = 0 |
---|
| 461 | |
---|
| 462 | ; Set the maximum number of iterations permitted for a generate loop. |
---|
| 463 | ; Restricting this permits the implementation to recognize infinite |
---|
| 464 | ; generate loops. |
---|
| 465 | ; GenerateLoopIterationMax = 100000 |
---|
| 466 | |
---|
| 467 | ; Set the maximum depth permitted for a recursive generate instantiation. |
---|
| 468 | ; Restricting this permits the implementation to recognize infinite |
---|
| 469 | ; recursions. |
---|
| 470 | ; GenerateRecursionDepthMax = 200 |
---|
| 471 | |
---|
| 472 | |
---|
| 473 | [vsim] |
---|
| 474 | ; vopt flow |
---|
| 475 | ; Set to turn on automatic optimization of a design. |
---|
| 476 | ; Default is on |
---|
| 477 | VoptFlow = 1 |
---|
| 478 | |
---|
| 479 | ; vopt automatic SDF |
---|
| 480 | ; If automatic design optimization is on, enables automatic compilation |
---|
| 481 | ; of SDF files. |
---|
| 482 | ; Default is on, uncomment to turn off. |
---|
| 483 | ; VoptAutoSDFCompile = 0 |
---|
| 484 | |
---|
| 485 | ; Automatic SDF compilation |
---|
| 486 | ; Disables automatic compilation of SDF files in flows that support it. |
---|
| 487 | ; Default is on, uncomment to turn off. |
---|
| 488 | ; NoAutoSDFCompile = 1 |
---|
| 489 | |
---|
| 490 | ; Simulator resolution |
---|
| 491 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. |
---|
| 492 | Resolution = ns |
---|
| 493 | |
---|
| 494 | ; Disable certain code coverage exclusions automatically. |
---|
| 495 | ; Assertions and FSM are exluded from the code coverage by default |
---|
| 496 | ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm |
---|
| 497 | ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions |
---|
| 498 | ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions |
---|
| 499 | ; Or specify comma or space separated list |
---|
| 500 | ;AutoExclusionsDisable = fsm,assertions |
---|
| 501 | |
---|
| 502 | ; User time unit for run commands |
---|
| 503 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the |
---|
| 504 | ; unit specified for Resolution. For example, if Resolution is 100ps, |
---|
| 505 | ; then UserTimeUnit defaults to ps. |
---|
| 506 | ; Should generally be set to default. |
---|
| 507 | UserTimeUnit = default |
---|
| 508 | |
---|
| 509 | ; Default run length |
---|
| 510 | RunLength = 100 |
---|
| 511 | |
---|
| 512 | ; Maximum iterations that can be run without advancing simulation time |
---|
| 513 | IterationLimit = 5000 |
---|
| 514 | |
---|
| 515 | ; Control PSL and Verilog Assume directives during simulation |
---|
| 516 | ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts |
---|
| 517 | ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts |
---|
| 518 | ; SimulateAssumeDirectives = 1 |
---|
| 519 | |
---|
| 520 | ; Control the simulation of PSL and SVA |
---|
| 521 | ; These switches can be overridden by the vsim command line switches: |
---|
| 522 | ; -psl, -nopsl, -sva, -nosva. |
---|
| 523 | ; Set SimulatePSL = 0 to disable PSL simulation |
---|
| 524 | ; Set SimulatePSL = 1 to enable PSL simulation (default) |
---|
| 525 | ; SimulatePSL = 1 |
---|
| 526 | ; Set SimulateSVA = 0 to disable SVA simulation |
---|
| 527 | ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) |
---|
| 528 | ; SimulateSVA = 1 |
---|
| 529 | |
---|
| 530 | ; Directives to license manager can be set either as single value or as |
---|
| 531 | ; space separated multi-values: |
---|
| 532 | ; vhdl Immediately reserve a VHDL license |
---|
| 533 | ; vlog Immediately reserve a Verilog license |
---|
| 534 | ; plus Immediately reserve a VHDL and Verilog license |
---|
| 535 | ; nomgc Do not look for Mentor Graphics Licenses |
---|
| 536 | ; nomti Do not look for Model Technology Licenses |
---|
| 537 | ; noqueue Do not wait in the license queue when a license is not available |
---|
| 538 | ; viewsim Try for viewer license but accept simulator license(s) instead |
---|
| 539 | ; of queuing for viewer license (PE ONLY) |
---|
| 540 | ; noviewer Disable checkout of msimviewer and vsim-viewer license |
---|
| 541 | ; features (PE ONLY) |
---|
| 542 | ; noslvhdl Disable checkout of qhsimvh and vsim license features |
---|
| 543 | ; noslvlog Disable checkout of qhsimvl and vsimvlog license features |
---|
| 544 | ; nomix Disable checkout of msimhdlmix and hdlmix license features |
---|
| 545 | ; nolnl Disable checkout of msimhdlsim and hdlsim license features |
---|
| 546 | ; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license |
---|
| 547 | ; features |
---|
| 548 | ; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, |
---|
| 549 | ; hdlmix license features |
---|
| 550 | ; Single value: |
---|
| 551 | ; License = plus |
---|
| 552 | ; Multi-value: |
---|
| 553 | ; License = noqueue plus |
---|
| 554 | |
---|
| 555 | ; Stop the simulator after a VHDL/Verilog immediate assertion message |
---|
| 556 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal |
---|
| 557 | BreakOnAssertion = 3 |
---|
| 558 | |
---|
| 559 | ; VHDL assertion Message Format |
---|
| 560 | ; %S - Severity Level |
---|
| 561 | ; %R - Report Message |
---|
| 562 | ; %T - Time of assertion |
---|
| 563 | ; %D - Delta |
---|
| 564 | ; %I - Instance or Region pathname (if available) |
---|
| 565 | ; %i - Instance pathname with process |
---|
| 566 | ; %O - Process name |
---|
| 567 | ; %K - Kind of object path is to return: Instance, Signal, Process or Unknown |
---|
| 568 | ; %P - Instance or Region path without leaf process |
---|
| 569 | ; %F - File |
---|
| 570 | ; %L - Line number of assertion or, if assertion is in a subprogram, line |
---|
| 571 | ; from which the call is made |
---|
| 572 | ; %% - Print '%' character |
---|
| 573 | ; If specific format for assertion level is defined, use its format. |
---|
| 574 | ; If specific format is not defined for assertion level: |
---|
| 575 | ; - and if failure occurs during elaboration, use MessageFormatBreakLine; |
---|
| 576 | ; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion |
---|
| 577 | ; level), use MessageFormatBreak; |
---|
| 578 | ; - otherwise, use MessageFormat. |
---|
| 579 | ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" |
---|
| 580 | ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" |
---|
| 581 | ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" |
---|
| 582 | ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" |
---|
| 583 | ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" |
---|
| 584 | ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" |
---|
| 585 | ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" |
---|
| 586 | ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" |
---|
| 587 | |
---|
| 588 | ; Error File - alternate file for storing error messages |
---|
| 589 | ; ErrorFile = error.log |
---|
| 590 | |
---|
| 591 | |
---|
| 592 | ; Simulation Breakpoint messages |
---|
| 593 | ; This flag controls the display of function names when reporting the location |
---|
| 594 | ; where the simulator stops do to a breakpoint or fatal error. |
---|
| 595 | ; Example w/function name: # Break in Process ctr at counter.vhd line 44 |
---|
| 596 | ; Example wo/function name: # Break at counter.vhd line 44 |
---|
| 597 | ShowFunctions = 1 |
---|
| 598 | |
---|
| 599 | ; Default radix for all windows and commands. |
---|
| 600 | ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned |
---|
| 601 | DefaultRadix = symbolic |
---|
| 602 | |
---|
| 603 | ; VSIM Startup command |
---|
| 604 | ; Startup = do startup.do |
---|
| 605 | |
---|
| 606 | ; VSIM Shutdown file |
---|
| 607 | ; Filename to save u/i formats and configurations. |
---|
| 608 | ; ShutdownFile = restart.do |
---|
| 609 | ; To explicitly disable auto save: |
---|
| 610 | ; ShutdownFile = --disable-auto-save |
---|
| 611 | |
---|
| 612 | ; File for saving command transcript |
---|
| 613 | TranscriptFile = transcript |
---|
| 614 | |
---|
| 615 | ; File for saving command history |
---|
| 616 | ; CommandHistory = cmdhist.log |
---|
| 617 | |
---|
| 618 | ; Specify whether paths in simulator commands should be described |
---|
| 619 | ; in VHDL or Verilog format. |
---|
| 620 | ; For VHDL, PathSeparator = / |
---|
| 621 | ; For Verilog, PathSeparator = . |
---|
| 622 | ; Must not be the same character as DatasetSeparator. |
---|
| 623 | PathSeparator = / |
---|
| 624 | |
---|
| 625 | ; Specify the dataset separator for fully rooted contexts. |
---|
| 626 | ; The default is ':'. For example: sim:/top |
---|
| 627 | ; Must not be the same character as PathSeparator. |
---|
| 628 | DatasetSeparator = : |
---|
| 629 | |
---|
| 630 | ; Specify a unique path separator for the Signal Spy set of functions. |
---|
| 631 | ; The default will be to use the PathSeparator variable. |
---|
| 632 | ; Must not be the same character as DatasetSeparator. |
---|
| 633 | ; SignalSpyPathSeparator = / |
---|
| 634 | |
---|
| 635 | ; Used to control parsing of HDL identifiers input to the tool. |
---|
| 636 | ; This includes CLI commands, vsim/vopt/vlog/vcom options, |
---|
| 637 | ; string arguments to FLI/VPI/DPI calls, etc. |
---|
| 638 | ; If set to 1, accept either Verilog escaped Id syntax or |
---|
| 639 | ; VHDL extended id syntax, regardless of source language. |
---|
| 640 | ; If set to 0, the syntax of the source language must be used. |
---|
| 641 | ; Each identifier in a hierarchical name may need different syntax, |
---|
| 642 | ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or |
---|
| 643 | ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" |
---|
| 644 | ; GenerousIdentifierParsing = 1 |
---|
| 645 | |
---|
| 646 | ; Disable VHDL assertion messages |
---|
| 647 | ; IgnoreNote = 1 |
---|
| 648 | ; IgnoreWarning = 1 |
---|
| 649 | ; IgnoreError = 1 |
---|
| 650 | ; IgnoreFailure = 1 |
---|
| 651 | |
---|
| 652 | ; Disable System Verilog assertion messages |
---|
| 653 | ; IgnoreSVAInfo = 1 |
---|
| 654 | ; IgnoreSVAWarning = 1 |
---|
| 655 | ; IgnoreSVAError = 1 |
---|
| 656 | ; IgnoreSVAFatal = 1 |
---|
| 657 | |
---|
| 658 | ; Do not print any additional information from Severity System tasks. |
---|
| 659 | ; Only the message provided by the user is printed along with severity |
---|
| 660 | ; information. |
---|
| 661 | ; SVAPrintOnlyUserMessage = 1; |
---|
| 662 | |
---|
| 663 | ; Default force kind. May be freeze, drive, deposit, or default |
---|
| 664 | ; or in other terms, fixed, wired, or charged. |
---|
| 665 | ; A value of "default" will use the signal kind to determine the |
---|
| 666 | ; force kind, drive for resolved signals, freeze for unresolved signals |
---|
| 667 | ; DefaultForceKind = freeze |
---|
| 668 | |
---|
| 669 | ; If zero, open files when elaborated; otherwise, open files on |
---|
| 670 | ; first read or write. Default is 0. |
---|
| 671 | ; DelayFileOpen = 1 |
---|
| 672 | |
---|
| 673 | ; Control VHDL files opened for write. |
---|
| 674 | ; 0 = Buffered, 1 = Unbuffered |
---|
| 675 | UnbufferedOutput = 0 |
---|
| 676 | |
---|
| 677 | ; Control the number of VHDL files open concurrently. |
---|
| 678 | ; This number should always be less than the current ulimit |
---|
| 679 | ; setting for max file descriptors. |
---|
| 680 | ; 0 = unlimited |
---|
| 681 | ConcurrentFileLimit = 40 |
---|
| 682 | |
---|
| 683 | ; Control the number of hierarchical regions displayed as |
---|
| 684 | ; part of a signal name shown in the Wave window. |
---|
| 685 | ; A value of zero tells VSIM to display the full name. |
---|
| 686 | ; The default is 0. |
---|
| 687 | ; WaveSignalNameWidth = 0 |
---|
| 688 | |
---|
| 689 | ; Turn off warnings when changing VHDL constants and generics |
---|
| 690 | ; Default is 1 to generate warning messages |
---|
| 691 | ; WarnConstantChange = 0 |
---|
| 692 | |
---|
| 693 | ; Turn off warnings from the std_logic_arith, std_logic_unsigned |
---|
| 694 | ; and std_logic_signed packages. |
---|
| 695 | ; StdArithNoWarnings = 1 |
---|
| 696 | |
---|
| 697 | ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. |
---|
| 698 | ; NumericStdNoWarnings = 1 |
---|
| 699 | |
---|
| 700 | ; Control the format of the (VHDL) FOR generate statement label |
---|
| 701 | ; for each iteration. Do not quote it. |
---|
| 702 | ; The format string here must contain the conversion codes %s and %d, |
---|
| 703 | ; in that order, and no other conversion codes. The %s represents |
---|
| 704 | ; the generate_label; the %d represents the generate parameter value |
---|
| 705 | ; at a particular generate iteration (this is the position number if |
---|
| 706 | ; the generate parameter is of an enumeration type). Embedded whitespace |
---|
| 707 | ; is allowed (but discouraged); leading and trailing whitespace is ignored. |
---|
| 708 | ; Application of the format must result in a unique scope name over all |
---|
| 709 | ; such names in the design so that name lookup can function properly. |
---|
| 710 | ; GenerateFormat = %s__%d |
---|
| 711 | |
---|
| 712 | ; Specify whether checkpoint files should be compressed. |
---|
| 713 | ; The default is 1 (compressed). |
---|
| 714 | ; CheckpointCompressMode = 0 |
---|
| 715 | |
---|
| 716 | ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. |
---|
| 717 | ; The term "out-of-the-blue" refers to SystemVerilog export function calls |
---|
| 718 | ; made from C functions that don't have the proper context setup |
---|
| 719 | ; (as is the case when running under "DPI-C" import functions). |
---|
| 720 | ; When this is enabled, one can call a DPI export function |
---|
| 721 | ; (but not task) from any C code. |
---|
| 722 | ; the setting of this variable can be one of the following values: |
---|
| 723 | ; 0 : dpioutoftheblue call is disabled (default) |
---|
| 724 | ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. |
---|
| 725 | ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. |
---|
| 726 | ; DpiOutOfTheBlue = 1 |
---|
| 727 | |
---|
| 728 | ; Specify whether continuous assignments are run before other normal priority |
---|
| 729 | ; processes scheduled in the same iteration. This event ordering minimizes race |
---|
| 730 | ; differences between optimized and non-optimized designs, and is the default |
---|
| 731 | ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set |
---|
| 732 | ; ImmediateContinuousAssign to 0. |
---|
| 733 | ; The default is 1 (enabled). |
---|
| 734 | ; ImmediateContinuousAssign = 0 |
---|
| 735 | |
---|
| 736 | ; List of dynamically loaded objects for Verilog PLI applications |
---|
| 737 | ; Veriuser = veriuser.sl |
---|
| 738 | |
---|
| 739 | ; Which default VPI object model should the tool conform to? |
---|
| 740 | ; The 1364 modes are Verilog-only, for backwards compatibility with older |
---|
| 741 | ; libraries, and SystemVerilog objects are not available in these modes. |
---|
| 742 | ; |
---|
| 743 | ; In the absence of a user-specified default, the tool default is the |
---|
| 744 | ; latest available LRM behavior. |
---|
| 745 | ; Options for PliCompatDefault are: |
---|
| 746 | ; VPI_COMPATIBILITY_VERSION_1364v1995 |
---|
| 747 | ; VPI_COMPATIBILITY_VERSION_1364v2001 |
---|
| 748 | ; VPI_COMPATIBILITY_VERSION_1364v2005 |
---|
| 749 | ; VPI_COMPATIBILITY_VERSION_1800v2005 |
---|
| 750 | ; VPI_COMPATIBILITY_VERSION_1800v2008 |
---|
| 751 | ; |
---|
| 752 | ; Synonyms for each string are also recognized: |
---|
| 753 | ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) |
---|
| 754 | ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) |
---|
| 755 | ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) |
---|
| 756 | ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) |
---|
| 757 | ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) |
---|
| 758 | |
---|
| 759 | |
---|
| 760 | ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 |
---|
| 761 | |
---|
| 762 | ; Specify default options for the restart command. Options can be one |
---|
| 763 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions |
---|
| 764 | ; DefaultRestartOptions = -force |
---|
| 765 | |
---|
| 766 | ; Turn on (1) or off (0) WLF file compression. |
---|
| 767 | ; The default is 1 (compress WLF file). |
---|
| 768 | ; WLFCompress = 0 |
---|
| 769 | |
---|
| 770 | ; Specify whether to save all design hierarchy (1) in the WLF file |
---|
| 771 | ; or only regions containing logged signals (0). |
---|
| 772 | ; The default is 0 (save only regions with logged signals). |
---|
| 773 | ; WLFSaveAllRegions = 1 |
---|
| 774 | |
---|
| 775 | ; WLF file time limit. Limit WLF file by time, as closely as possible, |
---|
| 776 | ; to the specified amount of simulation time. When the limit is exceeded |
---|
| 777 | ; the earliest times get truncated from the file. |
---|
| 778 | ; If both time and size limits are specified the most restrictive is used. |
---|
| 779 | ; UserTimeUnits are used if time units are not specified. |
---|
| 780 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} |
---|
| 781 | ; WLFTimeLimit = 0 |
---|
| 782 | |
---|
| 783 | ; WLF file size limit. Limit WLF file size, as closely as possible, |
---|
| 784 | ; to the specified number of megabytes. If both time and size limits |
---|
| 785 | ; are specified then the most restrictive is used. |
---|
| 786 | ; The default is 0 (no limit). |
---|
| 787 | ; WLFSizeLimit = 1000 |
---|
| 788 | |
---|
| 789 | ; Specify whether or not a WLF file should be deleted when the |
---|
| 790 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. |
---|
| 791 | ; The default is 0 (do not delete WLF file when simulation ends). |
---|
| 792 | ; WLFDeleteOnQuit = 1 |
---|
| 793 | |
---|
| 794 | ; Specify whether or not a WLF file should be indexed during |
---|
| 795 | ; simulation. If set to 0, the WLF file will not be indexed. |
---|
| 796 | ; The default is 1, indexed the WLF file. |
---|
| 797 | ; WLFIndex = 0 |
---|
| 798 | |
---|
| 799 | ; Specify whether or not a WLF file should be optimized during |
---|
| 800 | ; simulation. If set to 0, the WLF file will not be optimized. |
---|
| 801 | ; The default is 1, optimize the WLF file. |
---|
| 802 | ; WLFOptimize = 0 |
---|
| 803 | |
---|
| 804 | ; Specify the name of the WLF file. |
---|
| 805 | ; The default is vsim.wlf |
---|
| 806 | ; WLFFilename = vsim.wlf |
---|
| 807 | |
---|
| 808 | ; Specify the WLF reader cache size limit for each open WLF file. |
---|
| 809 | ; The size is giving in megabytes. A value of 0 turns off the |
---|
| 810 | ; WLF cache. |
---|
| 811 | ; WLFSimCacheSize allows a different cache size to be set for |
---|
| 812 | ; simulation WLF file independent of post-simulation WLF file |
---|
| 813 | ; viewing. If WLFSimCacheSize is not set it defaults to the |
---|
| 814 | ; WLFCacheSize setting. |
---|
| 815 | ; The default WLFCacheSize setting is enabled to 256M per open WLF file. |
---|
| 816 | ; WLFCacheSize = 2000 |
---|
| 817 | ; WLFSimCacheSize = 500 |
---|
| 818 | |
---|
| 819 | ; Specify the WLF file event collapse mode. |
---|
| 820 | ; 0 = Preserve all events and event order. (same as -wlfnocollapse) |
---|
| 821 | ; 1 = Only record values of logged objects at the end of a simulator iteration. |
---|
| 822 | ; (same as -wlfcollapsedelta) |
---|
| 823 | ; 2 = Only record values of logged objects at the end of a simulator time step. |
---|
| 824 | ; (same as -wlfcollapsetime) |
---|
| 825 | ; The default is 1. |
---|
| 826 | ; WLFCollapseMode = 0 |
---|
| 827 | |
---|
| 828 | ; Specify whether WLF file logging can use threads on multi-processor machines |
---|
| 829 | ; if 0, no threads will be used, if 1, threads will be used if the system has |
---|
| 830 | ; more than one processor |
---|
| 831 | ; WLFUseThreads = 1 |
---|
| 832 | |
---|
| 833 | ; Turn on/off undebuggable SystemC type warnings. Default is on. |
---|
| 834 | ; ShowUndebuggableScTypeWarning = 0 |
---|
| 835 | |
---|
| 836 | ; Turn on/off unassociated SystemC name warnings. Default is off. |
---|
| 837 | ; ShowUnassociatedScNameWarning = 1 |
---|
| 838 | |
---|
| 839 | ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. |
---|
| 840 | ; ScShowIeeeDeprecationWarnings = 1 |
---|
| 841 | |
---|
| 842 | ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. |
---|
| 843 | ; ScEnableScSignalWriteCheck = 1 |
---|
| 844 | |
---|
| 845 | ; Set SystemC default time unit. |
---|
| 846 | ; Set to fs, ps, ns, us, ms, or sec with optional |
---|
| 847 | ; prefix of 1, 10, or 100. The default is 1 ns. |
---|
| 848 | ; The ScTimeUnit value is honored if it is coarser than Resolution. |
---|
| 849 | ; If ScTimeUnit is finer than Resolution, it is set to the value |
---|
| 850 | ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, |
---|
| 851 | ; then the default time unit will be 1 ns. However if Resolution |
---|
| 852 | ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. |
---|
| 853 | ScTimeUnit = ns |
---|
| 854 | |
---|
| 855 | ; Set SystemC sc_main stack size. The stack size is set as an integer |
---|
| 856 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or |
---|
| 857 | ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends |
---|
| 858 | ; on the amount of data on the sc_main() stack and the memory required |
---|
| 859 | ; to succesfully execute the longest function call chain of sc_main(). |
---|
| 860 | ScMainStackSize = 10 Mb |
---|
| 861 | |
---|
| 862 | ; Turn on/off execution of remainder of sc_main upon quitting the current |
---|
| 863 | ; simulation session. If the cumulative length of sc_main() in terms of |
---|
| 864 | ; simulation time units is less than the length of the current simulation |
---|
| 865 | ; run upon quit or restart, sc_main() will be in the middle of execution. |
---|
| 866 | ; This switch gives the option to execute the remainder of sc_main upon |
---|
| 867 | ; quitting simulation. The drawback of not running sc_main till the end |
---|
| 868 | ; is memory leaks for objects created by sc_main. If on, the remainder of |
---|
| 869 | ; sc_main will be executed ignoring all delays. This may cause the simulator |
---|
| 870 | ; to crash if the code in sc_main is dependent on some simulation state. |
---|
| 871 | ; Default is on. |
---|
| 872 | ScMainFinishOnQuit = 1 |
---|
| 873 | |
---|
| 874 | ; Set the SCV relationship name that will be used to identify phase |
---|
| 875 | ; relations. If the name given to a transactor relation matches this |
---|
| 876 | ; name, the transactions involved will be treated as phase transactions |
---|
| 877 | ScvPhaseRelationName = mti_phase |
---|
| 878 | |
---|
| 879 | ; Customize the vsim kernel shutdown behavior at the end of the simulation. |
---|
| 880 | ; Some common causes of the end of simulation are $finish (implicit or explicit), |
---|
| 881 | ; sc_stop(), tf_dofinish(), and assertion failures. |
---|
| 882 | ; This should be set to "ask", "exit", or "stop". The default is "ask". |
---|
| 883 | ; "ask" -- In batch mode, the vsim kernel will abruptly exit. |
---|
| 884 | ; In GUI mode, a dialog box will pop up and ask for user confirmation |
---|
| 885 | ; whether or not to quit the simulation. |
---|
| 886 | ; "stop" -- Cause the simulation to stay loaded in memory. This can make some |
---|
| 887 | ; post-simulation tasks easier. |
---|
| 888 | ; "exit" -- The simulation will abruptly exit without asking for any confirmation. |
---|
| 889 | ; "final" -- Run SystemVerilog final blocks then behave as "stop". |
---|
| 890 | ; Note: these ini variables can be overriden by the vsim command |
---|
| 891 | ; line switch "-onfinish <ask|stop|exit>". |
---|
| 892 | OnFinish = ask |
---|
| 893 | |
---|
| 894 | ; Print pending deferred assertion messages. |
---|
| 895 | ; Deferred assertion messages may be scheduled after the $finish in the same |
---|
| 896 | ; time step. Deferred assertions scheduled to print after the $finish are |
---|
| 897 | ; printed before exiting with severity level NOTE since it's not known whether |
---|
| 898 | ; the assertion is still valid due to being printed in the active region |
---|
| 899 | ; instead of the reactive region where they are normally printed. |
---|
| 900 | ; OnFinishPendingAssert = 1; |
---|
| 901 | |
---|
| 902 | ; Print "simstats" result at the end of simulation before shutdown. |
---|
| 903 | ; If this is enabled, the simstats result will be printed out before shutdown. |
---|
| 904 | ; The default is off. |
---|
| 905 | ; PrintSimStats = 1 |
---|
| 906 | |
---|
| 907 | ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages |
---|
| 908 | ; AssertFile = assert.log |
---|
| 909 | |
---|
| 910 | ; Run simulator in assertion debug mode. Default is off. |
---|
| 911 | ; AssertionDebug = 1 |
---|
| 912 | |
---|
| 913 | ; Turn on/off PSL/SVA concurrent assertion pass enable. |
---|
| 914 | ; For SVA, Default is on when the assertion has a pass action block, or |
---|
| 915 | ; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active. |
---|
| 916 | ; For PSL, Default is on only when vsim switch "-assertdebug" is used |
---|
| 917 | ; and the vopt "+acc=a" flag is active. |
---|
| 918 | ; AssertionPassEnable = 0 |
---|
| 919 | |
---|
| 920 | ; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. |
---|
| 921 | ; AssertionFailEnable = 0 |
---|
| 922 | |
---|
| 923 | ; Set PSL/SVA concurrent assertion pass limit. Default is -1. |
---|
| 924 | ; Any positive integer, -1 for infinity. |
---|
| 925 | ; AssertionPassLimit = 1 |
---|
| 926 | |
---|
| 927 | ; Set PSL/SVA concurrent assertion fail limit. Default is -1. |
---|
| 928 | ; Any positive integer, -1 for infinity. |
---|
| 929 | ; AssertionFailLimit = 1 |
---|
| 930 | |
---|
| 931 | ; Turn on/off PSL concurrent assertion pass log. Default is off. |
---|
| 932 | ; The flag does not affect SVA |
---|
| 933 | ; AssertionPassLog = 1 |
---|
| 934 | |
---|
| 935 | ; Turn on/off PSL concurrent assertion fail log. Default is on. |
---|
| 936 | ; The flag does not affect SVA |
---|
| 937 | ; AssertionFailLog = 0 |
---|
| 938 | |
---|
| 939 | ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. |
---|
| 940 | ; AssertionFailLocalVarLog = 0 |
---|
| 941 | |
---|
| 942 | ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. |
---|
| 943 | ; 0 = Continue 1 = Break 2 = Exit |
---|
| 944 | ; AssertionFailAction = 1 |
---|
| 945 | |
---|
| 946 | ; Enable the active thread monitor in the waveform display when assertion debug is enabled. |
---|
| 947 | ; AssertionActiveThreadMonitor = 1 |
---|
| 948 | |
---|
| 949 | ; Control how many waveform rows will be used for displaying the active threads. Default is 5. |
---|
| 950 | ; AssertionActiveThreadMonitorLimit = 5 |
---|
| 951 | |
---|
| 952 | |
---|
| 953 | ; As per strict 1850-2005 PSL LRM, an always property can either pass |
---|
| 954 | ; or fail. However, by default, Questa reports multiple passes and |
---|
| 955 | ; multiple fails on top always/never property (always/never operator |
---|
| 956 | ; is the top operator under Verification Directive). The reason |
---|
| 957 | ; being that Questa reports passes and fails on per attempt of the |
---|
| 958 | ; top always/never property. Use the following flag to instruct |
---|
| 959 | ; Questa to strictly follow LRM. With this flag, all assert/never |
---|
| 960 | ; directives will start an attempt once at start of simulation. |
---|
| 961 | ; The attempt can either fail, match or match vacuously. |
---|
| 962 | ; For e.g. if always is the top operator under assert, the always will |
---|
| 963 | ; keep on checking the property at every clock. If the property under |
---|
| 964 | ; always fails, the directive will be considered failed and no more |
---|
| 965 | ; checking will be done for that directive. A top always property, |
---|
| 966 | ; if it does not fail, will show a pass at end of simulation. |
---|
| 967 | ; The default value is '0' (i.e. zero is off). For example: |
---|
| 968 | ; PslOneAttempt = 1 |
---|
| 969 | |
---|
| 970 | ; Specify the number of clock ticks to represent infinite clock ticks. |
---|
| 971 | ; This affects eventually!, until! and until_!. If at End of Simulation |
---|
| 972 | ; (EOS) an active strong-property has not clocked this number of |
---|
| 973 | ; clock ticks then neither pass or fail (vacuous match) is returned |
---|
| 974 | ; else respective fail/pass is returned. The default value is '0' (zero) |
---|
| 975 | ; which effectively does not check for clock tick condition. For example: |
---|
| 976 | ; PslInfinityThreshold = 5000 |
---|
| 977 | |
---|
| 978 | ; Control how many thread start times will be preserved for ATV viewing for a given assertion |
---|
| 979 | ; instance. Default is -1 (ALL). |
---|
| 980 | ; ATVStartTimeKeepCount = -1 |
---|
| 981 | |
---|
| 982 | ; Turn on/off code coverage |
---|
| 983 | ; CodeCoverage = 0 |
---|
| 984 | |
---|
| 985 | ; Count all code coverage condition and expression truth table rows that match. |
---|
| 986 | ; CoverCountAll = 1 |
---|
| 987 | |
---|
| 988 | ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default |
---|
| 989 | ; is to include them. |
---|
| 990 | ; ToggleNoIntegers = 1 |
---|
| 991 | |
---|
| 992 | ; Set the maximum number of values that are collected for toggle coverage of |
---|
| 993 | ; VHDL integers. Default is 100; |
---|
| 994 | ; ToggleMaxIntValues = 100 |
---|
| 995 | |
---|
| 996 | ; Set the maximum number of values that are collected for toggle coverage of |
---|
| 997 | ; Verilog real. Default is 100; |
---|
| 998 | ; ToggleMaxRealValues = 100 |
---|
| 999 | |
---|
| 1000 | ; Turn on automatic inclusion of Verilog integers in toggle coverage, except |
---|
| 1001 | ; for enumeration types. Default is to include them. |
---|
| 1002 | ; ToggleVlogIntegers = 0 |
---|
| 1003 | |
---|
| 1004 | ; Turn on automatic inclusion of Verilog real type in toggle coverage, except |
---|
| 1005 | ; for shortreal types. Default is to not include them. |
---|
| 1006 | ; ToggleVlogReal = 1 |
---|
| 1007 | |
---|
| 1008 | ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage. |
---|
| 1009 | ; Default is to not include them. |
---|
| 1010 | ; ToggleFixedSizeArray = 1 |
---|
| 1011 | |
---|
| 1012 | ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that |
---|
| 1013 | ; are included for toggle coverage. This leads to a longer simulation time with bigger |
---|
| 1014 | ; arrays covered with toggle coverage. Default is 1024. |
---|
| 1015 | ; ToggleMaxFixedSizeArray = 1024 |
---|
| 1016 | |
---|
| 1017 | ; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0. |
---|
| 1018 | ; TogglePackedAsVec = 0 |
---|
| 1019 | |
---|
| 1020 | ; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0. |
---|
| 1021 | ; ToggleVlogEnumBits = 0 |
---|
| 1022 | |
---|
| 1023 | ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. |
---|
| 1024 | ; For unlimited width, set to 0. |
---|
| 1025 | ; ToggleWidthLimit = 128 |
---|
| 1026 | |
---|
| 1027 | ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have |
---|
| 1028 | ; reached this count, further activity on the bit is ignored. Default is 1. |
---|
| 1029 | ; For unlimited counts, set to 0. |
---|
| 1030 | ; ToggleCountLimit = 1 |
---|
| 1031 | |
---|
| 1032 | ; Turn on/off all PSL/SVA cover directive enables. Default is on. |
---|
| 1033 | ; CoverEnable = 0 |
---|
| 1034 | |
---|
| 1035 | ; Turn on/off PSL/SVA cover log. Default is off "0". |
---|
| 1036 | ; CoverLog = 1 |
---|
| 1037 | |
---|
| 1038 | ; Set "at_least" value for all PSL/SVA cover directives. Default is 1. |
---|
| 1039 | ; CoverAtLeast = 2 |
---|
| 1040 | |
---|
| 1041 | ; Set "limit" value for all PSL/SVA cover directives. Default is -1. |
---|
| 1042 | ; Any positive integer, -1 for infinity. |
---|
| 1043 | ; CoverLimit = 1 |
---|
| 1044 | |
---|
| 1045 | ; Specify the coverage database filename. |
---|
| 1046 | ; Default is "" (i.e. database is NOT automatically saved on close). |
---|
| 1047 | ; UCDBFilename = vsim.ucdb |
---|
| 1048 | |
---|
| 1049 | ; Specify the maximum limit for the number of Cross (bin) products reported |
---|
| 1050 | ; in XML and UCDB report against a Cross. A warning is issued if the limit |
---|
| 1051 | ; is crossed. |
---|
| 1052 | ; MaxReportRhsSVCrossProducts = 1000 |
---|
| 1053 | |
---|
| 1054 | ; Specify the override for the "auto_bin_max" option for the Covergroups. |
---|
| 1055 | ; If not specified then value from Covergroup "option" is used. |
---|
| 1056 | ; SVCoverpointAutoBinMax = 64 |
---|
| 1057 | |
---|
| 1058 | ; Specify the override for the value of "cross_num_print_missing" |
---|
| 1059 | ; option for the Cross in Covergroups. If not specified then value |
---|
| 1060 | ; specified in the "option.cross_num_print_missing" is used. This |
---|
| 1061 | ; is a runtime option. NOTE: This overrides any "cross_num_print_missing" |
---|
| 1062 | ; value specified by user in source file and any SVCrossNumPrintMissingDefault |
---|
| 1063 | ; specified in modelsim.ini. |
---|
| 1064 | ; SVCrossNumPrintMissing = 0 |
---|
| 1065 | |
---|
| 1066 | ; Specify whether to use the value of "cross_num_print_missing" |
---|
| 1067 | ; option in report and GUI for the Cross in Covergroups. If not specified then |
---|
| 1068 | ; cross_num_print_missing is ignored for creating reports and displaying |
---|
| 1069 | ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". |
---|
| 1070 | ; UseSVCrossNumPrintMissing = 0 |
---|
| 1071 | |
---|
| 1072 | ; Specify the override for the value of "strobe" option for the |
---|
| 1073 | ; Covergroup Type. If not specified then value in "type_option.strobe" |
---|
| 1074 | ; will be used. This is runtime option which forces "strobe" to |
---|
| 1075 | ; user specified value and supersedes user specified values in the |
---|
| 1076 | ; SystemVerilog Code. NOTE: This also overrides the compile time |
---|
| 1077 | ; default value override specified using "SVCovergroupStrobeDefault" |
---|
| 1078 | ; SVCovergroupStrobe = 0 |
---|
| 1079 | |
---|
| 1080 | ; Override for explicit assignments in source code to "option.goal" of |
---|
| 1081 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the |
---|
| 1082 | ; default value of "option.goal" (defined to be 100 in the SystemVerilog |
---|
| 1083 | ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". |
---|
| 1084 | ; SVCovergroupGoal = 100 |
---|
| 1085 | |
---|
| 1086 | ; Override for explicit assignments in source code to "type_option.goal" of |
---|
| 1087 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the |
---|
| 1088 | ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog |
---|
| 1089 | ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". |
---|
| 1090 | ; SVCovergroupTypeGoal = 100 |
---|
| 1091 | |
---|
| 1092 | ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() |
---|
| 1093 | ; builtin functions, and report. This setting changes the default values of |
---|
| 1094 | ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 |
---|
| 1095 | ; behavior if explicit assignments are not made on option.get_inst_coverage and |
---|
| 1096 | ; type_option.merge_instances by the user. There are two vsim command line |
---|
| 1097 | ; options, -cvg63 and -nocvg63 to override this setting from vsim command line. |
---|
| 1098 | ; The default value of this variable is 1 |
---|
| 1099 | ; SVCovergroup63Compatibility = 1 |
---|
| 1100 | |
---|
| 1101 | ; Enable or disable generation of more detailed information about the sampling |
---|
| 1102 | ; of covergroup, cross, and coverpoints. It provides the details of the number |
---|
| 1103 | ; of times the covergroup instance and type were sampled, as well as details |
---|
| 1104 | ; about why covergroup, cross and coverpoint were not covered. A non-zero value |
---|
| 1105 | ; is to enable this feature. 0 is to disable this feature. Default is 0 |
---|
| 1106 | ; SVCovergroupSampleInfo = 0 |
---|
| 1107 | |
---|
| 1108 | ; Specify the maximum number of Coverpoint bins in whole design for |
---|
| 1109 | ; all Covergroups. |
---|
| 1110 | ; MaxSVCoverpointBinsDesign = 2147483648 |
---|
| 1111 | |
---|
| 1112 | ; Specify maximum number of Coverpoint bins in any instance of a Covergroup |
---|
| 1113 | ; MaxSVCoverpointBinsInst = 2147483648 |
---|
| 1114 | |
---|
| 1115 | ; Specify the maximum number of Cross bins in whole design for |
---|
| 1116 | ; all Covergroups. |
---|
| 1117 | ; MaxSVCrossBinsDesign = 2147483648 |
---|
| 1118 | |
---|
| 1119 | ; Specify maximum number of Cross bins in any instance of a Covergroup |
---|
| 1120 | ; MaxSVCrossBinsInst = 2147483648 |
---|
| 1121 | |
---|
| 1122 | ; Set weight for all PSL/SVA cover directives. Default is 1. |
---|
| 1123 | ; CoverWeight = 2 |
---|
| 1124 | |
---|
| 1125 | ; Check vsim plusargs. Default is 0 (off). |
---|
| 1126 | ; 0 = Don't check plusargs |
---|
| 1127 | ; 1 = Warning on unrecognized plusarg |
---|
| 1128 | ; 2 = Error and exit on unrecognized plusarg |
---|
| 1129 | ; CheckPlusargs = 1 |
---|
| 1130 | |
---|
| 1131 | ; Load the specified shared objects with the RTLD_GLOBAL flag. |
---|
| 1132 | ; This gives global visibility to all symbols in the shared objects, |
---|
| 1133 | ; meaning that subsequently loaded shared objects can bind to symbols |
---|
| 1134 | ; in the global shared objects. The list of shared objects should |
---|
| 1135 | ; be whitespace delimited. This option is not supported on the |
---|
| 1136 | ; Windows or AIX platforms. |
---|
| 1137 | ; GlobalSharedObjectList = example1.so example2.so example3.so |
---|
| 1138 | |
---|
| 1139 | ; Run the 0in tools from within the simulator. |
---|
| 1140 | ; Default is off. |
---|
| 1141 | ; ZeroIn = 1 |
---|
| 1142 | |
---|
| 1143 | ; Set the options to be passed to the 0in runtime tool. |
---|
| 1144 | ; Default value set to "". |
---|
| 1145 | ; ZeroInOptions = "" |
---|
| 1146 | |
---|
| 1147 | ; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). |
---|
| 1148 | ; Sv_Seed = 0 |
---|
| 1149 | |
---|
| 1150 | ; Maximum size of dynamic arrays that are resized during randomize(). |
---|
| 1151 | ; The default is 1000. A value of 0 indicates no limit. |
---|
| 1152 | ; SolveArrayResizeMax = 1000 |
---|
| 1153 | |
---|
| 1154 | ; Error message severity when randomize() failure is detected (SystemVerilog). |
---|
| 1155 | ; The default is 0 (no error). |
---|
| 1156 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal |
---|
| 1157 | ; SolveFailSeverity = 0 |
---|
| 1158 | |
---|
| 1159 | ; Enable/disable debug information for randomize() failures (SystemVerilog). |
---|
| 1160 | ; The default is 0 (disabled). Set to 1 to enable. |
---|
| 1161 | ; SolveFailDebug = 0 |
---|
| 1162 | |
---|
| 1163 | ; When SolveFailDebug is enabled, this value specifies the algorithm used to |
---|
| 1164 | ; discover conflicts between constraints for randomize() failures. |
---|
| 1165 | ; The default is "many". |
---|
| 1166 | ; |
---|
| 1167 | ; Valid schemes are: |
---|
| 1168 | ; "many" = best for determining conflicts due to many related constraints |
---|
| 1169 | ; "few" = best for determining conflicts due to few related constraints |
---|
| 1170 | ; |
---|
| 1171 | ; SolveFailDebugScheme = many |
---|
| 1172 | |
---|
| 1173 | ; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value |
---|
| 1174 | ; specifies the maximum number of constraint subsets that will be tested for |
---|
| 1175 | ; conflicts. |
---|
| 1176 | ; The default is 0 (no limit). |
---|
| 1177 | ; SolveFailDebugLimit = 0 |
---|
| 1178 | |
---|
| 1179 | ; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value |
---|
| 1180 | ; specifies the maximum size of constraint subsets that will be tested for |
---|
| 1181 | ; conflicts. |
---|
| 1182 | ; The default value is 0 (no limit). |
---|
| 1183 | ; SolveFailDebugMaxSet = 0 |
---|
| 1184 | |
---|
| 1185 | ; Maximum size of the solution graph that may be generated during randomize(). |
---|
| 1186 | ; This value can be used to force randomize() to abort if the memory |
---|
| 1187 | ; requirements of the constraint scenario exceeds the specified limit. This |
---|
| 1188 | ; value is specified in 1000s of nodes. |
---|
| 1189 | ; The default is 10000. A value of 0 indicates no limit. |
---|
| 1190 | ; SolveGraphMaxSize = 10000 |
---|
| 1191 | |
---|
| 1192 | ; Maximum number of evaluations that may be performed on the solution graph |
---|
| 1193 | ; generated during randomize(). This value can be used to force randomize() to |
---|
| 1194 | ; abort if the complexity of the constraint scenario (in time) exceeds the |
---|
| 1195 | ; specified limit. This value is specified in 10000s of evaluations. |
---|
| 1196 | ; The default is 10000. A value of 0 indicates no limit. |
---|
| 1197 | ; SolveGraphMaxEval = 10000 |
---|
| 1198 | |
---|
| 1199 | ; Use SolveFlags to specify options that will guide the behavior of the |
---|
| 1200 | ; constraint solver. These options may improve the performance of the |
---|
| 1201 | ; constraint solver for some testcases, and decrease the performance of |
---|
| 1202 | ; the constraint solver for others. |
---|
| 1203 | ; The default value is "" (no options). |
---|
| 1204 | ; |
---|
| 1205 | ; Valid flags are: |
---|
| 1206 | ; i = disable bit interleaving for >, >=, <, <= constraints |
---|
| 1207 | ; n = disable bit interleaving for all constraints |
---|
| 1208 | ; r = reverse bit interleaving |
---|
| 1209 | ; |
---|
| 1210 | ; SolveFlags = |
---|
| 1211 | |
---|
| 1212 | ; Specify random sequence compatiblity with a prior letter release. This |
---|
| 1213 | ; option is used to get the same random sequences during simulation as |
---|
| 1214 | ; as a prior letter release. Only prior letter releases (of the current |
---|
| 1215 | ; number release) are allowed. |
---|
| 1216 | ; Note: To achieve the same random sequences, solver optimizations and/or |
---|
| 1217 | ; bug fixes introduced since the specified release may be disabled - |
---|
| 1218 | ; yielding the performance / behavior of the prior release. |
---|
| 1219 | ; Default value set to "" (random compatibility not required). |
---|
| 1220 | ; SolveRev = |
---|
| 1221 | |
---|
| 1222 | ; Environment variable expansion of command line arguments has been depricated |
---|
| 1223 | ; in favor shell level expansion. Universal environment variable expansion |
---|
| 1224 | ; inside -f files is support and continued support for MGC Location Maps provide |
---|
| 1225 | ; alternative methods for handling flexible pathnames. |
---|
| 1226 | ; The following line may be uncommented and the value set to 1 to re-enable this |
---|
| 1227 | ; deprecated behavior. The default value is 0. |
---|
| 1228 | ; DeprecatedEnvironmentVariableExpansion = 0 |
---|
| 1229 | |
---|
| 1230 | ; Turn on/off collapsing of bus ports in VCD dumpports output |
---|
| 1231 | DumpportsCollapse = 1 |
---|
| 1232 | |
---|
| 1233 | ; Location of Multi-Level Verification Component (MVC) installation. |
---|
| 1234 | ; The default location is the product installation directory. |
---|
| 1235 | ; MvcHome = $MODEL_TECH/... |
---|
| 1236 | |
---|
| 1237 | [lmc] |
---|
| 1238 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software |
---|
| 1239 | libsm = $MODEL_TECH/libsm.sl |
---|
| 1240 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) |
---|
| 1241 | ; libsm = $MODEL_TECH/libsm.dll |
---|
| 1242 | ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) |
---|
| 1243 | ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl |
---|
| 1244 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) |
---|
| 1245 | ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o |
---|
| 1246 | ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) |
---|
| 1247 | ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so |
---|
| 1248 | ; Logic Modeling's SmartModel SWIFT software (Windows NT) |
---|
| 1249 | ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll |
---|
| 1250 | ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) |
---|
| 1251 | ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so |
---|
| 1252 | ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) |
---|
| 1253 | ; libswift = $LMC_HOME/lib/linux.lib/libswift.so |
---|
| 1254 | |
---|
| 1255 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software |
---|
| 1256 | libhm = $MODEL_TECH/libhm.sl |
---|
| 1257 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) |
---|
| 1258 | ; libhm = $MODEL_TECH/libhm.dll |
---|
| 1259 | ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) |
---|
| 1260 | ; libsfi = <sfi_dir>/lib/hp700/libsfi.sl |
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| 1261 | ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) |
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| 1262 | ; libsfi = <sfi_dir>/lib/rs6000/libsfi.a |
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| 1263 | ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) |
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| 1264 | ; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so |
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| 1265 | ; Logic Modeling's hardware modeler SFI software (Windows NT) |
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| 1266 | ; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll |
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| 1267 | ; Logic Modeling's hardware modeler SFI software (Linux) |
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| 1268 | ; libsfi = <sfi_dir>/lib/linux/libsfi.so |
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| 1269 | |
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| 1270 | [msg_system] |
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| 1271 | ; Change a message severity or suppress a message. |
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| 1272 | ; The format is: <msg directive> = <msg number>[,<msg number>...] |
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| 1273 | ; suppress can be used to achieve +nowarn<CODE> functionality |
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| 1274 | ; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...] |
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| 1275 | ; Examples: |
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| 1276 | ; note = 3009 |
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| 1277 | ; warning = 3033 |
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| 1278 | ; error = 3010,3016 |
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| 1279 | ; fatal = 3016,3033 |
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| 1280 | ; suppress = 3009,3016,3043 |
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| 1281 | ; suppress = 3009,CNNODP,3043,TFMPC |
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| 1282 | ; The command verror <msg number> can be used to get the complete |
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| 1283 | ; description of a message. |
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| 1284 | |
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| 1285 | ; Control transcripting of Verilog display system task messages and |
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| 1286 | ; PLI/FLI print function call messages. The system tasks include |
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| 1287 | ; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They |
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| 1288 | ; also include the analogous file I/O tasks that write to STDOUT |
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| 1289 | ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, |
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| 1290 | ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default |
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| 1291 | ; is to have messages appear only in the transcript. The other |
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| 1292 | ; settings are to send messages to the wlf file only (messages that |
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| 1293 | ; are recorded in the wlf file can be viewed in the MsgViewer) or |
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| 1294 | ; to both the transcript and the wlf file. The valid values are |
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| 1295 | ; tran {transcript only (default)} |
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| 1296 | ; wlf {wlf file only} |
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| 1297 | ; both {transcript and wlf file} |
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| 1298 | ; displaymsgmode = tran |
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| 1299 | |
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| 1300 | ; Control transcripting of elaboration/runtime messages not |
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| 1301 | ; addressed by the displaymsgmode setting. The default is to |
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| 1302 | ; have messages appear in the transcript and recorded in the wlf |
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| 1303 | ; file (messages that are recorded in the wlf file can be viewed |
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| 1304 | ; in the MsgViewer). The other settings are to send messages |
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| 1305 | ; only to the transcript or only to the wlf file. The valid |
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| 1306 | ; values are |
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| 1307 | ; both {default} |
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| 1308 | ; tran {transcript only} |
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| 1309 | ; wlf {wlf file only} |
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| 1310 | ; msgmode = both |
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