source: trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/_topcell_.vhd @ 93

library verilog;
use verilog.vl_types.all;
entity topcell_ is
    port(
        p_clock : in  vl_logic;
        p_resetn : in  vl_logic
    );
end topcell_;