Last change
on this file since 317 was
275,
checked in by bouyer, 12 years ago
|
This VHDL implementation uses rings, use rings here too.
|
File size:
715 bytes
|
Rev | Line | |
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[274] | 1 | |
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| 2 | # -*- python -*- |
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| 3 | |
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| 4 | |
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| 5 | todo = Platform('caba', 'top.cpp', |
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| 6 | uses = [ |
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| 7 | Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:mips32el'), |
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| 8 | Uses('caba:vci_simple_ram'), |
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| 9 | Uses('caba:vci_multi_tty'), |
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| 10 | Uses('caba:vci_xicu'), |
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| 11 | Uses('caba:vci_block_device_tsar_v4'), |
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| 12 | Uses('caba:vci_simhelper'), |
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| 13 | Uses('caba:vci_framebuffer'), |
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[275] | 14 | Uses('caba:vci_simple_ring_fast', |
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| 15 | ring_cmd_data_size=40, |
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| 16 | ring_rsp_data_size=33 |
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| 17 | ), |
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[274] | 18 | Uses('caba:vci_logger'), |
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| 19 | Uses('caba:vci_mem_cache_v4'), |
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| 20 | Uses('common:elf_file_loader'), |
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| 21 | ], |
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| 22 | cell_size = 4, |
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| 23 | plen_size = 8, |
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| 24 | addr_size = 32, |
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| 25 | rerror_size = 2, |
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| 26 | clen_size = 1, |
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| 27 | rflag_size = 1, |
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| 28 | srcid_size = 5, |
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| 29 | pktid_size = 4, |
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| 30 | trdid_size = 4, |
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| 31 | wrplen_size = 1 |
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| 32 | ) |
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| 33 | |
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