Context Navigation

source: trunk/platforms/tsar_generic_iob/arch.py @ 1003

Last change on this file since 1003 was 1002, checked in by alain, 9 years ago
Introducing the BDV / SDC / HBA switch in the tsar_generic_iob plat-form
Property svn:executable set to ``*
File size: 20.3 KB

Line
1	#!/usr/bin/env python
2
3	from math import log, ceil
4	from mapping import *
5
6	##################################################################################
7	# file : arch.py (for the tsar_generic_iob architecture)
8	# date : may 2014
9	# author : Alain Greiner
10	##################################################################################
11	# This file contains a mapping generator for the "tsar_generic_iob" platform.
12	# This includes both the hardware architecture (clusters, processors, peripherals,
13	# physical space segmentation) and the mapping of all boot and kernel objects
14	# (global vsegs).
15	#
16	# This platform includes 7 external peripherals, accessible through an IOB
17	# components located in cluster [0,0] or in cluster [x_size-1, y_size-1].
18	# Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC.
19	#
20	# All clusters contain (nb_procs) processors, one L2 cache, one XCU, and
21	# one optional hardware coprocessor connected to a MWMR_DMA controller.
22	#
23	# The "constructor" parameters (defined in Makefile) are:
24	# - x_size : number of clusters in a row
25	# - y_size : number of clusters in a column
26	# - nb_procs : number of processors per cluster
27	# - nb_ttys : number of TTY channels
28	# - fbf_width : frame_buffer width = frame_buffer heigth
29	# - ioc_type : can be 'BDV','HBA','SDC', 'SPI' but not 'RDK'
30	#
31	#
32	# The other hardware parameters (defined in this script) are:
33	# - nb_nics : number of NIC channels
34	# - nb_cmas : number of CMA channels
35	# - x_io : cluster_io x coordinate
36	# - y_io : cluster_io y coordinate
37	# - x_width : number of bits for x coordinate
38	# - y_width : number of bits for y coordinate
39	# - paddr_width : number of bits for physical address
40	# - irq_per_proc : number of input IRQs per processor
41	# - use_ramdisk : use a ramdisk when True
42	# - vseg_increment : address increment for replicated vsegs
43	# - mwr_type : coprocessor type / can be 'GCD','DCT','NOPE'
44	# - use_dma : one single channel DMA per cluster if non zero
45	#
46	# Regarding the boot and kernel vsegs mapping :
47	# - We use one big physical page (2 Mbytes) for the preloader and the four
48	# boot vsegs, all allocated in cluster[0,0].
49	# - We use one big page per cluster for the replicated kernel code vsegs.
50	# - We use one big page in cluster[0][0] for the kernel data vseg.
51	# - We use one big page per cluster for the distributed kernel heap vsegs.
52	# - We use one big page per cluster for the distributed ptab vsegs.
53	# - We use small physical pages (4 Kbytes) per cluster for the schedulers.
54	# - We use one big page for each external peripheral in IO cluster,
55	# - We use one small page per cluster for each internal peripheral.
56	##################################################################################
57
58	########################
59	def arch( x_size = 2,
60	y_size = 2,
61	nb_procs = 2,
62	nb_ttys = 1,
63	fbf_width = 128,
64	ioc_type = 'HBA' ):
65
66	### define architecture constants
67
68	nb_nics = 1
69	nb_cmas = 2
70	x_io = 0
71	y_io = 0
72	x_width = 4
73	y_width = 4
74	p_width = 4
75	paddr_width = 40
76	irq_per_proc = 4
77	peri_increment = 0x10000
78	mwr_type = 'CPY'
79
80	### constructor parameters checking
81
82	assert( nb_procs <= (1 << p_width) )
83
84	assert( (x_size == 1) or (x_size == 2) or (x_size == 4)
85	or (x_size == 8) or (x_size == 16) )
86
87	assert( (y_size == 1) or (y_size == 2) or (y_size == 4)
88	or (y_size == 8) or (y_size == 16) )
89
90	assert( (nb_ttys >= 1) and (nb_ttys <= 8) )
91
92	assert( ((x_io == 0) and (y_io == 0)) or
93	((x_io == x_size-1) and (y_io == y_size-1)) )
94
95	assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' , 'SPI' ] )
96
97	assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' , 'NONE' ] )
98
99	### define platform name
100
101	platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_procs )
102	platform_name += '_%d_%d_%s' % ( fbf_width , nb_ttys , ioc_type )
103
104	### define physical segments replicated in all clusters
105
106	ram_base = 0x0000000000
107	ram_size = 0x1000000 # 16 Mbytes
108
109	xcu_base = 0x00B0000000
110	xcu_size = 0x1000 # 4 Kbytes
111
112	mwr_base = 0x00B1000000
113	mwr_size = 0x1000 # 4 Kbytes
114
115	mmc_base = 0x00B2000000
116	mmc_size = 0x1000 # 4 Kbytes
117
118	### define physical segments for external peripherals
119	## These segments are only defined in cluster_io
120
121	ioc_base = 0x00B3000000
122	ioc_size = 0x1000 # 4 Kbytes
123
124	tty_base = 0x00B4000000
125	tty_size = 0x4000 # 16 Kbytes
126
127	nic_base = 0x00B5000000
128	nic_size = 0x80000 # 512 kbytes
129
130	cma_base = 0x00B6000000
131	cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics
132
133	fbf_base = 0x00B7000000
134	fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes
135
136	pic_base = 0x00B8000000
137	pic_size = 0x1000 # 4 Kbytes
138
139	iob_base = 0x00BE000000
140	iob_size = 0x1000 # 4 bytes
141
142	rom_base = 0x00BFC00000
143	rom_size = 0x4000 # 16 Kbytes
144
145	### define bootloader vsegs base addresses and sizes
146	### We want to pack these 4 vsegs in the same big page
147	### => boot cost is one BIG page in cluster[0][0]
148
149	boot_mapping_vbase = 0x00000000 # ident
150	boot_mapping_size = 0x00080000 # 512 Kbytes
151
152	boot_code_vbase = 0x00080000 # ident
153	boot_code_size = 0x00040000 # 256 Kbytes
154
155	boot_data_vbase = 0x000C0000 # ident
156	boot_data_size = 0x000C0000 # 768 Kbytes
157
158	boot_stack_vbase = 0x00180000 # ident
159	boot_stack_size = 0x00080000 # 512 Kbytes
160
161	### define kernel vsegs base addresses and sizes
162	### code, init, ptab, heap & sched vsegs are replicated in all clusters.
163	### data & uncdata vsegs are only mapped in cluster[0][0].
164
165	kernel_code_vbase = 0x80000000
166	kernel_code_size = 0x00100000 # 1 Mbytes per cluster
167
168	kernel_init_vbase = 0x80100000
169	kernel_init_size = 0x00100000 # 1 Mbytes per cluster
170
171	kernel_data_vbase = 0x90000000
172	kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0]
173
174	kernel_ptab_vbase = 0xE0000000
175	kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster
176
177	kernel_heap_vbase = 0xD0000000
178	kernel_heap_size = 0x00200000 # 2 Mbytes per cluster
179
180	kernel_sched_vbase = 0xA0000000
181	kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster
182
183	#########################
184	### create mapping
185	#########################
186
187	mapping = Mapping( name = platform_name,
188	x_size = x_size,
189	y_size = y_size,
190	nprocs = nb_procs,
191	x_width = x_width,
192	y_width = y_width,
193	p_width = p_width,
194	paddr_width = paddr_width,
195	coherence = True,
196	irq_per_proc = irq_per_proc,
197	use_ramdisk = (ioc_type == 'RDK'),
198	x_io = x_io,
199	y_io = y_io,
200	peri_increment = peri_increment,
201	ram_base = ram_base,
202	ram_size = ram_size )
203
204
205	#############################
206	### Hardware Components
207	#############################
208
209	for x in xrange( x_size ):
210	for y in xrange( y_size ):
211	cluster_xy = (x << y_width) + y;
212	offset = cluster_xy << (paddr_width - x_width - y_width)
213
214	### components replicated in all clusters
215	mapping.addRam( 'RAM', base = ram_base + offset,
216	size = ram_size )
217
218	xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset,
219	size = xcu_size, ptype = 'XCU',
220	channels = nb_procs * irq_per_proc,
221	arg0 = 32, arg1 = 32, arg2 = 32 )
222
223	mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset,
224	size = mmc_size, ptype = 'MMC' )
225
226	if ( mwr_type == 'GCD' ):
227	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
228	size = mwr_size, ptype = 'MWR', subtype = 'GCD',
229	arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 )
230
231	if ( mwr_type == 'DCT' ):
232	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
233	size = mwr_size, ptype = 'MWR', subtype = 'DCT',
234	arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )
235
236	if ( mwr_type == 'CPY' ):
237	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
238	size = mwr_size, ptype = 'MWR', subtype = 'CPY',
239	arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )
240
241	mapping.addIrq( xcu, index = 0, src = mmc, isrtype = 'ISR_MMC' )
242	mapping.addIrq( xcu, index = 1, src = mwr, isrtype = 'ISR_MWR' )
243
244	for p in xrange ( nb_procs ):
245	mapping.addProc( x , y , p )
246
247	### external peripherals in cluster_io
248	if ( (x==x_io) and (y==y_io) ):
249
250	iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size,
251	ptype = 'IOB' )
252
253	ioc = mapping.addPeriph( 'IOC', base = ioc_base + offset, size = ioc_size,
254	ptype = 'IOC', subtype = ioc_type )
255
256	tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size,
257	ptype = 'TTY', channels = nb_ttys )
258
259	nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size,
260	ptype = 'NIC', channels = nb_nics )
261
262	cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size,
263	ptype = 'CMA', channels = nb_cmas )
264
265	fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size,
266	ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width )
267
268	rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size,
269	ptype = 'ROM' )
270
271	pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size,
272	ptype = 'PIC', channels = 32 )
273
274	mapping.addIrq( pic, index = 0, src = nic,
275	isrtype = 'ISR_NIC_RX', channel = 0 )
276	mapping.addIrq( pic, index = 1, src = nic,
277	isrtype = 'ISR_NIC_RX', channel = 1 )
278
279	mapping.addIrq( pic, index = 2, src = nic,
280	isrtype = 'ISR_NIC_TX', channel = 0 )
281	mapping.addIrq( pic, index = 3, src = nic,
282	isrtype = 'ISR_NIC_TX', channel = 1 )
283
284	mapping.addIrq( pic, index = 4, src = cma,
285	isrtype = 'ISR_CMA', channel = 0 )
286	mapping.addIrq( pic, index = 5, src = cma,
287	isrtype = 'ISR_CMA', channel = 1 )
288	mapping.addIrq( pic, index = 6, src = cma,
289	isrtype = 'ISR_CMA', channel = 2 )
290	mapping.addIrq( pic, index = 7, src = cma,
291	isrtype = 'ISR_CMA', channel = 3 )
292
293	if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV'
294	if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA'
295	if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC'
296	if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI'
297
298	mapping.addIrq( pic, index = 8, src = ioc,
299	isrtype = isr_ioc, channel = 0 )
300	mapping.addIrq( pic, index = 16, src = tty,
301	isrtype = 'ISR_TTY_RX', channel = 0 )
302	mapping.addIrq( pic, index = 17, src = tty,
303	isrtype = 'ISR_TTY_RX', channel = 1 )
304	mapping.addIrq( pic, index = 18, src = tty,
305	isrtype = 'ISR_TTY_RX', channel = 2 )
306	mapping.addIrq( pic, index = 19, src = tty,
307	isrtype = 'ISR_TTY_RX', channel = 3 )
308	mapping.addIrq( pic, index = 20, src = tty,
309	isrtype = 'ISR_TTY_RX', channel = 4 )
310	mapping.addIrq( pic, index = 21, src = tty,
311	isrtype = 'ISR_TTY_RX', channel = 5 )
312	mapping.addIrq( pic, index = 22, src = tty,
313	isrtype = 'ISR_TTY_RX', channel = 6 )
314	mapping.addIrq( pic, index = 23, src = tty,
315	isrtype = 'ISR_TTY_RX', channel = 7 )
316
317
318	####################################
319	### Boot & Kernel vsegs mapping
320	####################################
321
322	### global vsegs for boot_loader
323	### we want to pack those 4 vsegs in the same big page
324	### => same flags CXW_ / identity mapping / non local / big page
325
326	mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
327	'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM',
328	identity = True , local = False, big = True )
329
330	mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
331	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
332	identity = True , local = False, big = True )
333
334	mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
335	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
336	identity = True , local = False, big = True )
337
338	mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
339	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
340	identity = True , local = False, big = True )
341
342	### global vseg kernel_data : big / non local
343	### Only mapped in cluster[0][0]
344	mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size,
345	'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM',
346	binpath = 'build/kernel/kernel.elf',
347	local = False, big = True )
348
349	### global vsegs kernel_code, kernel_init : big / local
350	### replicated in all clusters with indexed name & same vbase
351	for x in xrange( x_size ):
352	for y in xrange( y_size ):
353	mapping.addGlobal( 'seg_kernel_code_%d_%d' %(x,y),
354	kernel_code_vbase, kernel_code_size,
355	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
356	binpath = 'build/kernel/kernel.elf',
357	local = True, big = True )
358
359	mapping.addGlobal( 'seg_kernel_init_%d_%d' %(x,y),
360	kernel_init_vbase, kernel_init_size,
361	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
362	binpath = 'build/kernel/kernel.elf',
363	local = True, big = True )
364
365	### Global vsegs kernel_ptab_x_y : big / non local
366	### one vseg per cluster: name indexed by (x,y)
367	for x in xrange( x_size ):
368	for y in xrange( y_size ):
369	offset = ((x << y_width) + y) * kernel_ptab_size
370	base = kernel_ptab_vbase + offset
371	mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size,
372	'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM',
373	local = False , big = True )
374
375	### global vsegs kernel_sched_x_y : small / non local
376	### one vseg per cluster with name indexed by (x,y)
377	for x in xrange( x_size ):
378	for y in xrange( y_size ):
379	offset = ((x << y_width) + y) * kernel_sched_size
380	mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y),
381	kernel_sched_vbase + offset , kernel_sched_size,
382	'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM',
383	local = False, big = False )
384
385	### global vsegs kernel_heap_x_y : big / non local
386	### one vseg per cluster with name indexed by (x,y)
387	for x in xrange( x_size ):
388	for y in xrange( y_size ):
389	offset = ((x << y_width) + y) * kernel_heap_size
390	mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y),
391	kernel_heap_vbase + offset , kernel_heap_size,
392	'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM',
393	local = False, big = True )
394
395	### global vsegs for external peripherals : non local / big page
396	mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_',
397	vtype = 'PERI', x = 0, y = 0, pseg = 'IOB',
398	local = False, big = True )
399
400	mapping.addGlobal( 'seg_ioc', ioc_base, ioc_size, '__W_',
401	vtype = 'PERI', x = 0, y = 0, pseg = 'IOC',
402	local = False, big = True )
403
404	mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_',
405	vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
406	local = False, big = True )
407
408	mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_',
409	vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
410	local = False, big = True )
411
412	mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_',
413	vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
414	local = False, big = True )
415
416	mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_',
417	vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
418	local = False, big = True )
419
420	mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_',
421	vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
422	local = False, big = True )
423
424	mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_',
425	vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
426	local = False, big = True )
427
428	### global vsegs for internal peripherals : non local / small pages
429	### allocated in all clusters with name indexed by (x,y)
430	### as vbase address is incremented by (cluster_xy * vseg_increment)
431	for x in xrange( x_size ):
432	for y in xrange( y_size ):
433	offset = ((x << y_width) + y) * peri_increment
434
435	mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size,
436	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU',
437	local = False, big = False )
438
439	mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size,
440	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
441	local = False, big = False )
442
443	if ( mwr_type != 'NONE' ):
444	mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size,
445	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR',
446	local = False, big = False )
447
448	return mapping
449
450	################################# platform test ####################################
451
452	if __name__ == '__main__':
453
454	mapping = arch( x_size = 2,
455	y_size = 2,
456	nb_procs = 2 )
457
458	# print mapping.netbsd_dts()
459
460	print mapping.xml()
461
462	# print mapping.giet_vsegs()
463
464
465	# Local Variables:
466	# tab-width: 4;
467	# c-basic-offset: 4;
468	# c-file-offsets:((innamespace . 0)(inline-open . 0));
469	# indent-tabs-mode: nil;
470	# End:
471	#
472	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
473

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0