1 | #!/usr/bin/env python |
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2 | |
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3 | from math import log, ceil |
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4 | from mapping import * |
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5 | |
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6 | ################################################################################## |
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7 | # file : arch.py (for the tsar_generic_iob architecture) |
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8 | # date : may 2014 |
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9 | # author : Alain Greiner |
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10 | ################################################################################## |
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11 | # This file contains a mapping generator for the "tsar_generic_iob" platform. |
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12 | # This includes both the hardware architecture (clusters, processors, peripherals, |
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13 | # physical space segmentation) and the mapping of all boot and kernel objects |
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14 | # (global vsegs). |
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15 | # |
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16 | # This platform includes 7 external peripherals, accessible through an IOB |
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17 | # components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. |
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18 | # Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC. |
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19 | # |
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20 | # All clusters contain (nb_procs) processors, one L2 cache, one XCU, and |
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21 | # one optional hardware coprocessor connected to a MWMR_DMA controller. |
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22 | # |
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23 | # The "constructor" parameters (defined in Makefile) are: |
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24 | # - x_size : number of clusters in a row |
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25 | # - y_size : number of clusters in a column |
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26 | # - nb_procs : number of processors per cluster |
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27 | # - nb_ttys : number of TTY channels |
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28 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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29 | # - ioc_type : can be 'BDV','HBA','SDC', 'SPI' but not 'RDK' |
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30 | # - mwr_type : coprocessor type / can be 'GCD','DCT','CPY','NONE' |
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31 | # |
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32 | # The other hardware parameters (defined in this script) are: |
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33 | # - nb_nics : number of NIC channels |
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34 | # - nb_cmas : number of CMA channels |
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35 | # - x_io : cluster_io x coordinate |
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36 | # - y_io : cluster_io y coordinate |
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37 | # - x_width : number of bits for x coordinate |
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38 | # - y_width : number of bits for y coordinate |
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39 | # - p_width : number of bits for processor local index |
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40 | # - paddr_width : number of bits for physical address |
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41 | # - irq_per_proc : number of input IRQs per processor |
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42 | # - peri_increment : address increment for replicated peripherals |
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43 | # |
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44 | # Regarding the boot and kernel vsegs mapping : |
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45 | # - We use one big physical page (2 Mbytes) for the preloader, |
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46 | # the 4 boot vsegs are packed in one BPP allocated in cluster[0,0]. |
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47 | # - We use one BPP per cluster for the replicated kernel code vsegs. |
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48 | # - We use one BPP in cluster[0][0] for the kernel data vseg. |
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49 | # - We use two BPP per cluster for the distributed kernel heap vsegs. |
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50 | # - We use one BPP per cluster for the distributed ptab vsegs. |
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51 | # - We use two SPP per cluster for each schedulers. |
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52 | # - We use one PBB for each external peripheral in IO cluster, |
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53 | # - We use one SPP per cluster for each internal peripheral. |
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54 | ################################################################################## |
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55 | |
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56 | ######################## |
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57 | def arch( x_size = 2, |
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58 | y_size = 2, |
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59 | nb_procs = 2, |
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60 | nb_ttys = 1, |
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61 | fbf_width = 128, |
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62 | ioc_type = 'BDV', |
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63 | mwr_type = 'CPY' ): |
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64 | |
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65 | ### define architecture constants |
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66 | |
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67 | if ( x_size * y_size >= 4 ) : nb_nics = 4 |
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68 | elif ( x_size * y_size == 2 ) : nb_nics = 2 |
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69 | else : nb_nics = 1 |
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70 | |
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71 | nb_cmas = 1 |
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72 | x_io = 0 |
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73 | y_io = 0 |
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74 | x_width = 4 |
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75 | y_width = 4 |
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76 | p_width = 4 |
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77 | paddr_width = 40 |
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78 | irq_per_proc = 4 |
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79 | peri_increment = 0x10000 |
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80 | |
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81 | ### constructor parameters checking |
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82 | |
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83 | assert( nb_procs <= (1 << p_width) ) |
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84 | |
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85 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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86 | or (x_size == 8) or (x_size == 16) ) |
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87 | |
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88 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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89 | or (y_size == 8) or (y_size == 16) ) |
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90 | |
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91 | assert( (nb_ttys >= 1) and (nb_ttys <= 16) ) |
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92 | |
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93 | assert( ((x_io == 0) and (y_io == 0)) or |
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94 | ((x_io == x_size-1) and (y_io == y_size-1)) ) |
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95 | |
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96 | assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' , 'SPI' ] ) |
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97 | |
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98 | assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' ] ) |
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99 | |
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100 | ### define platform name |
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101 | |
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102 | platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_procs ) |
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103 | platform_name += '_%d_%d_%s_%s' % ( fbf_width , nb_ttys , ioc_type , mwr_type ) |
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104 | |
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105 | ### define physical segments replicated in all clusters |
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106 | |
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107 | ram_base = 0x0000000000 |
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108 | ram_size = 0x4000000 # 64 Mbytes |
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109 | |
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110 | xcu_base = 0x00B0000000 |
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111 | xcu_size = 0x1000 # 4 Kbytes |
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112 | |
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113 | mwr_base = 0x00B1000000 |
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114 | mwr_size = 0x1000 # 4 Kbytes |
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115 | |
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116 | mmc_base = 0x00B2000000 |
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117 | mmc_size = 0x1000 # 4 Kbytes |
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118 | |
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119 | ### define physical segments for external peripherals |
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120 | ## These segments are only defined in cluster_io |
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121 | |
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122 | ioc_base = 0x00B3000000 |
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123 | ioc_size = 0x1000 # 4 Kbytes |
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124 | |
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125 | tty_base = 0x00B4000000 |
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126 | tty_size = 0x4000 # 16 Kbytes |
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127 | |
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128 | nic_base = 0x00B5000000 |
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129 | nic_size = 0x1000 # 4 Kkbytes |
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130 | |
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131 | cma_base = 0x00B6000000 |
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132 | cma_size = 0x1000 * nb_cmas # 4 kbytes * nb_cmas |
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133 | |
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134 | fbf_base = 0x00B7000000 |
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135 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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136 | |
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137 | pic_base = 0x00B8000000 |
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138 | pic_size = 0x1000 # 4 Kbytes |
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139 | |
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140 | iob_base = 0x00BE000000 |
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141 | iob_size = 0x1000 # 4 bytes |
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142 | |
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143 | rom_base = 0x00BFC00000 |
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144 | rom_size = 0x4000 # 16 Kbytes |
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145 | |
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146 | ### define bootloader vsegs base addresses and sizes |
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147 | ### We want to pack these 4 vsegs in 2 big pages |
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148 | ### => boot cost two BIG pages in cluster[0][0] |
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149 | |
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150 | boot_mapping_vbase = 0x00000000 # ident |
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151 | boot_mapping_size = 0x00100000 # 1 Mbytes |
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152 | |
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153 | boot_code_vbase = 0x00100000 # ident |
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154 | boot_code_size = 0x00080000 # 512 Kbytes |
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155 | |
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156 | boot_stack_vbase = 0x00180000 # ident |
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157 | boot_stack_size = 0x00080000 # 512 Kbytes |
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158 | |
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159 | boot_data_vbase = 0x00200000 # ident |
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160 | boot_data_size = 0x00200000 # 2 Mbytes |
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161 | |
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162 | ### define kernel vsegs base addresses and sizes |
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163 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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164 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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165 | |
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166 | kernel_code_vbase = 0x80000000 |
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167 | kernel_code_size = 0x00200000 # 2 Mbytes per cluster |
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168 | |
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169 | kernel_data_vbase = 0x90000000 |
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170 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] |
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171 | |
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172 | kernel_ptab_vbase = 0xE0000000 |
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173 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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174 | |
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175 | kernel_heap_vbase = 0xD0000000 |
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176 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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177 | |
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178 | kernel_sched_vbase = 0xA0000000 |
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179 | kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster |
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180 | |
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181 | ######################### |
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182 | ### create mapping |
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183 | ######################### |
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184 | |
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185 | mapping = Mapping( name = platform_name, |
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186 | x_size = x_size, |
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187 | y_size = y_size, |
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188 | nprocs = nb_procs, |
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189 | x_width = x_width, |
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190 | y_width = y_width, |
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191 | p_width = p_width, |
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192 | paddr_width = paddr_width, |
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193 | coherence = True, |
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194 | irq_per_proc = irq_per_proc, |
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195 | use_ramdisk = (ioc_type == 'RDK'), |
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196 | x_io = x_io, |
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197 | y_io = y_io, |
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198 | peri_increment = peri_increment, |
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199 | ram_base = ram_base, |
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200 | ram_size = ram_size ) |
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201 | |
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202 | |
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203 | ############################# |
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204 | ### Hardware Components |
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205 | ############################# |
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206 | |
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207 | for x in xrange( x_size ): |
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208 | for y in xrange( y_size ): |
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209 | cluster_xy = (x << y_width) + y; |
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210 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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211 | |
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212 | ### components replicated in all clusters |
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213 | mapping.addRam( 'RAM', base = ram_base + offset, |
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214 | size = ram_size ) |
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215 | |
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216 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, |
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217 | size = xcu_size, ptype = 'XCU', |
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218 | channels = nb_procs * irq_per_proc, |
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219 | arg0 = 32, arg1 = 32, arg2 = 32 ) |
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220 | |
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221 | mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, |
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222 | size = mmc_size, ptype = 'MMC' ) |
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223 | |
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224 | if ( mwr_type == 'GCD' ): |
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225 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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226 | size = mwr_size, ptype = 'MWR', subtype = 'GCD', |
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227 | arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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228 | |
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229 | if ( mwr_type == 'DCT' ): |
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230 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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231 | size = mwr_size, ptype = 'MWR', subtype = 'DCT', |
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232 | arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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233 | |
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234 | if ( mwr_type == 'CPY' ): |
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235 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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236 | size = mwr_size, ptype = 'MWR', subtype = 'CPY', |
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237 | arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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238 | |
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239 | mapping.addIrq( xcu, index = 0, src = mmc, isrtype = 'ISR_MMC' ) |
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240 | mapping.addIrq( xcu, index = 1, src = mwr, isrtype = 'ISR_MWR' ) |
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241 | |
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242 | for p in xrange ( nb_procs ): |
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243 | mapping.addProc( x , y , p ) |
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244 | |
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245 | ### external peripherals in cluster_io |
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246 | if ( (x==x_io) and (y==y_io) ): |
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247 | |
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248 | iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size, |
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249 | ptype = 'IOB' ) |
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250 | |
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251 | ioc = mapping.addPeriph( 'IOC', base = ioc_base + offset, size = ioc_size, |
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252 | ptype = 'IOC', subtype = ioc_type ) |
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253 | |
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254 | tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size, |
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255 | ptype = 'TTY', channels = nb_ttys ) |
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256 | |
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257 | nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size, |
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258 | ptype = 'NIC', channels = nb_nics ) |
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259 | |
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260 | cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size, |
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261 | ptype = 'CMA', channels = nb_cmas ) |
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262 | |
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263 | fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size, |
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264 | ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width ) |
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265 | |
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266 | rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, |
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267 | ptype = 'ROM' ) |
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268 | |
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269 | pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size, |
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270 | ptype = 'PIC', channels = 32 ) |
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271 | |
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272 | if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV' |
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273 | if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA' |
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274 | if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC' |
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275 | if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI' |
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276 | |
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277 | mapping.addIrq( pic, index = 0, src = nic, |
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278 | isrtype = 'ISR_NIC_RX', channel = 0 ) |
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279 | mapping.addIrq( pic, index = 1, src = nic, |
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280 | isrtype = 'ISR_NIC_RX', channel = 1 ) |
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281 | mapping.addIrq( pic, index = 2, src = nic, |
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282 | isrtype = 'ISR_NIC_RX', channel = 2 ) |
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283 | mapping.addIrq( pic, index = 3, src = nic, |
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284 | isrtype = 'ISR_NIC_RX', channel = 3 ) |
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285 | |
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286 | mapping.addIrq( pic, index = 4, src = nic, |
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287 | isrtype = 'ISR_NIC_TX', channel = 0 ) |
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288 | mapping.addIrq( pic, index = 5, src = nic, |
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289 | isrtype = 'ISR_NIC_TX', channel = 1 ) |
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290 | mapping.addIrq( pic, index = 6, src = nic, |
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291 | isrtype = 'ISR_NIC_TX', channel = 2 ) |
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292 | mapping.addIrq( pic, index = 7, src = nic, |
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293 | isrtype = 'ISR_NIC_TX', channel = 3 ) |
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294 | |
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295 | mapping.addIrq( pic, index = 8 , src = cma, |
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296 | isrtype = 'ISR_CMA', channel = 0 ) |
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297 | mapping.addIrq( pic, index = 9 , src = cma, |
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298 | isrtype = 'ISR_CMA', channel = 1 ) |
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299 | mapping.addIrq( pic, index = 10, src = cma, |
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300 | isrtype = 'ISR_CMA', channel = 2 ) |
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301 | mapping.addIrq( pic, index = 11, src = cma, |
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302 | isrtype = 'ISR_CMA', channel = 3 ) |
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303 | |
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304 | mapping.addIrq( pic, index = 12, src = ioc, |
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305 | isrtype = isr_ioc, channel = 0 ) |
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306 | |
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307 | mapping.addIrq( pic, index = 16, src = tty, |
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308 | isrtype = 'ISR_TTY_RX', channel = 0 ) |
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309 | mapping.addIrq( pic, index = 17, src = tty, |
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310 | isrtype = 'ISR_TTY_RX', channel = 1 ) |
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311 | mapping.addIrq( pic, index = 18, src = tty, |
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312 | isrtype = 'ISR_TTY_RX', channel = 2 ) |
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313 | mapping.addIrq( pic, index = 19, src = tty, |
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314 | isrtype = 'ISR_TTY_RX', channel = 3 ) |
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315 | mapping.addIrq( pic, index = 20, src = tty, |
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316 | isrtype = 'ISR_TTY_RX', channel = 4 ) |
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317 | mapping.addIrq( pic, index = 21, src = tty, |
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318 | isrtype = 'ISR_TTY_RX', channel = 5 ) |
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319 | mapping.addIrq( pic, index = 22, src = tty, |
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320 | isrtype = 'ISR_TTY_RX', channel = 6 ) |
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321 | mapping.addIrq( pic, index = 23, src = tty, |
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322 | isrtype = 'ISR_TTY_RX', channel = 7 ) |
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323 | |
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324 | |
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325 | #################################### |
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326 | ### Boot & Kernel vsegs mapping |
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327 | #################################### |
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328 | |
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329 | ### global vsegs for boot_loader |
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330 | ### we want to pack those 4 vsegs in the same big page |
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331 | ### => same flags CXW_ / identity mapping / non local / big page |
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332 | |
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333 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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334 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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335 | identity = True , local = False, big = True ) |
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336 | |
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337 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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338 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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339 | identity = True , local = False, big = True ) |
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340 | |
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341 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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342 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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343 | identity = True , local = False, big = True ) |
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344 | |
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345 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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346 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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347 | identity = True , local = False, big = True ) |
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348 | |
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349 | ### global vseg kernel_data : big / non local |
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350 | ### Only mapped in cluster[0][0] |
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351 | mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, |
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352 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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353 | binpath = 'bin/kernel/kernel.elf', |
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354 | local = False, big = True ) |
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355 | |
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356 | ### global vsegs kernel_code : big / local |
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357 | ### replicated in all clusters with indexed name & same vbase |
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358 | for x in xrange( x_size ): |
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359 | for y in xrange( y_size ): |
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360 | mapping.addGlobal( 'seg_kernel_code_%d_%d' %(x,y), |
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361 | kernel_code_vbase, kernel_code_size, |
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362 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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363 | binpath = 'bin/kernel/kernel.elf', |
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364 | local = True, big = True ) |
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365 | |
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366 | ### Global vsegs kernel_ptab_x_y : big / non local |
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367 | ### one vseg per cluster: name indexed by (x,y) |
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368 | for x in xrange( x_size ): |
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369 | for y in xrange( y_size ): |
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370 | offset = ((x << y_width) + y) * kernel_ptab_size |
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371 | base = kernel_ptab_vbase + offset |
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372 | mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size, |
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373 | 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', |
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374 | local = False , big = True ) |
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375 | |
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376 | ### global vsegs kernel_sched_x_y : small / non local |
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377 | ### one vseg per cluster with name indexed by (x,y) |
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378 | for x in xrange( x_size ): |
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379 | for y in xrange( y_size ): |
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380 | offset = ((x << y_width) + y) * kernel_sched_size |
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381 | mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), |
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382 | kernel_sched_vbase + offset , kernel_sched_size, |
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383 | 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM', |
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384 | local = False, big = False ) |
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385 | |
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386 | ### global vsegs kernel_heap_x_y : big / non local |
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387 | ### one vseg per cluster with name indexed by (x,y) |
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388 | for x in xrange( x_size ): |
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389 | for y in xrange( y_size ): |
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390 | offset = ((x << y_width) + y) * kernel_heap_size |
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391 | mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), |
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392 | kernel_heap_vbase + offset , kernel_heap_size, |
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393 | 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', |
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394 | local = False, big = True ) |
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395 | |
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396 | ### global vsegs for external peripherals : non local / big page |
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397 | mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', |
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398 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', |
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399 | local = False, big = True ) |
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400 | |
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401 | mapping.addGlobal( 'seg_ioc', ioc_base, ioc_size, '__W_', |
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402 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOC', |
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403 | local = False, big = True ) |
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404 | |
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405 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', |
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406 | vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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407 | local = False, big = True ) |
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408 | |
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409 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', |
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410 | vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', |
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411 | local = False, big = True ) |
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412 | |
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413 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', |
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414 | vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', |
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415 | local = False, big = True ) |
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416 | |
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417 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', |
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418 | vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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419 | local = False, big = True ) |
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420 | |
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421 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', |
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422 | vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', |
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423 | local = False, big = True ) |
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424 | |
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425 | mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', |
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426 | vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', |
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427 | local = False, big = True ) |
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428 | |
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429 | ### global vsegs for internal peripherals : non local / small pages |
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430 | ### allocated in all clusters with name indexed by (x,y) |
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431 | ### as vbase address is incremented by (cluster_xy * vseg_increment) |
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432 | for x in xrange( x_size ): |
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433 | for y in xrange( y_size ): |
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434 | offset = ((x << y_width) + y) * peri_increment |
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435 | |
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436 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, |
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437 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', |
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438 | local = False, big = False ) |
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439 | |
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440 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, |
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441 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', |
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442 | local = False, big = False ) |
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443 | |
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444 | if ( mwr_type != 'NONE' ): |
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445 | mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size, |
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446 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR', |
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447 | local = False, big = False ) |
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448 | |
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449 | return mapping |
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450 | |
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451 | ################################# platform test #################################### |
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452 | |
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453 | if __name__ == '__main__': |
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454 | |
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455 | mapping = arch( x_size = 2, |
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456 | y_size = 2, |
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457 | nb_procs = 2 ) |
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458 | |
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459 | # print mapping.netbsd_dts() |
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460 | |
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461 | print mapping.xml() |
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462 | |
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463 | # print mapping.giet_vsegs() |
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464 | |
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465 | |
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466 | # Local Variables: |
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467 | # tab-width: 4; |
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468 | # c-basic-offset: 4; |
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469 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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470 | # indent-tabs-mode: nil; |
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471 | # End: |
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472 | # |
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473 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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474 | |
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