| 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from mapping import * |
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| 4 | |
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| 5 | ####################################################################################### |
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| 6 | # file : arch.py (for the tsar_generic_iob architecture) |
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| 7 | # date : may 2014 |
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| 8 | # author : Alain Greiner |
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| 9 | ####################################################################################### |
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| 10 | # This file contains a mapping generator for the "tsar_generic_iob" platform. |
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| 11 | # This includes both the hardware architecture (clusters, processors, peripherals, |
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| 12 | # physical space segmentation) and the mapping of all kernel objects (global vsegs). |
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| 13 | # This platform includes 6 external peripherals, accessible through two IO_Bridge |
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| 14 | # components located in cluster [0,0] and cluster [x_size-1, y_size-1]. |
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| 15 | # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. |
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| 16 | # |
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| 17 | # The "constructor" parameters are: |
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| 18 | # - x_size : number of clusters in a row |
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| 19 | # - y_size : number of clusters in a column |
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| 20 | # - nb_procs : number of processors per cluster |
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| 21 | # |
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| 22 | # The "hidden" platform parameters are: |
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| 23 | # - nb_ttys : number of TTY channels |
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| 24 | # - nb_nics : number of NIC channels |
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| 25 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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| 26 | # - x_io : cluster_io x coordinate |
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| 27 | # - y_io : cluster_io y coordinate |
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| 28 | # - x_width : number of bits for x coordinate |
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| 29 | # - y_width : number of bits for y coordinate |
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| 30 | # - paddr_width : number of bits for physical address |
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| 31 | # - irq_per_proc : number of input IRQs per processor |
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| 32 | # - use_ramdisk : use a ramdisk when True |
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| 33 | # - peri_increment : address increment for replicated peripherals |
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| 34 | #################################################################################### |
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| 35 | |
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| 36 | ######################## |
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| 37 | def arch( x_size = 2, |
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| 38 | y_size = 2, |
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| 39 | nb_procs = 2 ): |
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| 40 | |
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| 41 | ### define architecture constants |
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| 42 | |
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| 43 | nb_ttys = 1 |
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| 44 | nb_nics = 2 |
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| 45 | fbf_width = 1024 |
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| 46 | x_io = 0 |
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| 47 | y_io = 0 |
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| 48 | x_width = 4 |
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| 49 | y_width = 4 |
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| 50 | paddr_width = 40 |
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| 51 | irq_per_proc = 4 |
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| 52 | use_ramdisk = False |
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| 53 | peri_increment = 0x10000 |
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| 54 | |
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| 55 | ### parameters checking |
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| 56 | |
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| 57 | assert( nb_procs <= 4 ) |
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| 58 | |
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| 59 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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| 60 | or (y_size == 8) or (x_size == 16) ) |
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| 61 | |
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| 62 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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| 63 | or (y_size == 8) or (y_size == 16) ) |
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| 64 | |
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| 65 | assert( nb_ttys == 1 ) |
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| 66 | |
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| 67 | assert( ((x_io == 0) and (y_io == 0)) or |
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| 68 | ((x_io == x_size-1) and (y_io == y_size-1)) ) |
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| 69 | |
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| 70 | platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) |
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| 71 | |
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| 72 | ### define physical segments |
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| 73 | |
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| 74 | ram_base = 0x0000000000 |
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| 75 | ram_size = 0x4000000 # 64 Mbytes |
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| 76 | |
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| 77 | xcu_base = 0x00B0000000 |
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| 78 | xcu_size = 0x1000 # 4 Kbytes |
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| 79 | |
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| 80 | dma_base = 0x00B1000000 |
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| 81 | dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs |
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| 82 | |
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| 83 | mmc_base = 0x00B2000000 |
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| 84 | mmc_size = 0x1000 # 4 Kbytes |
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| 85 | |
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| 86 | offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) |
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| 87 | |
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| 88 | bdv_base = 0x00B3000000 + offset_io |
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| 89 | bdv_size = 0x1000 # 4kbytes |
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| 90 | |
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| 91 | tty_base = 0x00B4000000 + offset_io |
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| 92 | tty_size = 0x4000 # 16 Kbytes |
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| 93 | |
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| 94 | nic_base = 0x00B5000000 + offset_io |
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| 95 | nic_size = 0x80000 # 512 kbytes |
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| 96 | |
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| 97 | cma_base = 0x00B6000000 + offset_io |
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| 98 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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| 99 | |
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| 100 | fbf_base = 0x00B7000000 + offset_io |
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| 101 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 102 | |
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| 103 | pic_base = 0x00B8000000 + offset_io |
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| 104 | pic_size = 0x1000 # 4 Kbytes |
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| 105 | |
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| 106 | iob_base = 0x00BE000000 + offset_io |
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| 107 | iob_size = 0x1000 # 4kbytes |
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| 108 | |
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| 109 | rom_base = 0x00BFC00000 + offset_io |
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| 110 | rom_size = 0x4000 # 16 Kbytes |
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| 111 | |
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| 112 | ### define bootloader vsegs base addresses |
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| 113 | |
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| 114 | boot_mapping_vbase = 0x00000000 # ident |
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| 115 | boot_mapping_size = 0x00040000 # 256 Kbytes |
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| 116 | |
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| 117 | boot_code_vbase = 0x00040000 # ident |
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| 118 | boot_code_size = 0x00020000 # 128 Kbytes |
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| 119 | |
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| 120 | boot_data_vbase = 0x00060000 # ident |
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| 121 | boot_data_size = 0x00010000 # 64 Kbytes |
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| 122 | |
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| 123 | boot_buffer_vbase = 0x00070000 # ident |
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| 124 | boot_buffer_size = 0x00060000 # 384 Kbytes |
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| 125 | |
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| 126 | boot_stack_vbase = 0x000D0000 # ident |
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| 127 | boot_stack_size = 0x00050000 # 320 Kbytes |
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| 128 | |
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| 129 | ### define kernel vsegs base addresses |
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| 130 | |
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| 131 | kernel_code_vbase = 0x80000000 |
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| 132 | kernel_code_size = 0x00020000 # 128 Kbytes |
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| 133 | |
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| 134 | kernel_data_vbase = 0x80020000 |
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| 135 | kernel_data_size = 0x00060000 # 384 Kbytes |
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| 136 | |
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| 137 | kernel_uncdata_vbase = 0x80080000 |
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| 138 | kernel_uncdata_size = 0x00040000 # 256 Kbytes |
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| 139 | |
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| 140 | kernel_init_vbase = 0x800C0000 |
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| 141 | kernel_init_size = 0x00010000 # 64 Kbytes |
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| 142 | |
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| 143 | kernel_sched_vbase = 0xF0000000 # distributed in all clusters |
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| 144 | kernel_sched_size = 0x1000 * nb_procs # 4 kbytes per processor |
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| 145 | |
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| 146 | ### create mapping |
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| 147 | |
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| 148 | mapping = Mapping( name = platform_name, |
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| 149 | x_size = x_size, |
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| 150 | y_size = y_size, |
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| 151 | procs_max = nb_procs, |
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| 152 | x_width = x_width, |
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| 153 | y_width = y_width, |
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| 154 | paddr_width = paddr_width, |
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| 155 | coherence = True, |
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| 156 | irq_per_proc = irq_per_proc, |
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| 157 | use_ramdisk = use_ramdisk, |
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| 158 | x_io = x_io, |
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| 159 | y_io = y_io, |
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| 160 | peri_increment = peri_increment ) |
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| 161 | |
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| 162 | ### external peripherals (accessible in cluster[0,0] only for this mapping) |
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| 163 | |
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| 164 | iob = mapping.addPeriph( 'IOB', base = iob_base, size = iob_size, ptype = 'IOB' ) |
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| 165 | |
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| 166 | bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) |
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| 167 | |
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| 168 | tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) |
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| 169 | |
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| 170 | nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) |
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| 171 | |
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| 172 | cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) |
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| 173 | |
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| 174 | fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) |
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| 175 | |
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| 176 | rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) |
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| 177 | |
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| 178 | pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) |
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| 179 | |
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| 180 | mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) |
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| 181 | mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) |
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| 182 | |
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| 183 | mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) |
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| 184 | mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) |
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| 185 | |
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| 186 | mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) |
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| 187 | mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) |
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| 188 | mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) |
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| 189 | mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) |
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| 190 | |
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| 191 | mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) |
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| 192 | |
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| 193 | mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) |
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| 194 | |
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| 195 | ### hardware components replicated in all clusters |
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| 196 | |
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| 197 | for x in xrange( x_size ): |
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| 198 | for y in xrange( y_size ): |
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| 199 | cluster_xy = (x << y_width) + y; |
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| 200 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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| 201 | |
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| 202 | ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) |
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| 203 | |
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| 204 | mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, |
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| 205 | ptype = 'MMC' ) |
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| 206 | |
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| 207 | dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, |
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| 208 | ptype = 'DMA', channels = nb_procs ) |
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| 209 | |
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| 210 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, |
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| 211 | ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) |
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| 212 | |
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| 213 | # MMC IRQ replicated in all clusters |
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| 214 | mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) |
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| 215 | |
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| 216 | # processors |
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| 217 | for p in xrange ( nb_procs ): |
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| 218 | mapping.addProc( x, y, p ) |
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| 219 | |
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| 220 | ### global vsegs for boot_loader / identity mapping |
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| 221 | |
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| 222 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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| 223 | 'C_W_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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| 224 | identity = True ) |
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| 225 | |
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| 226 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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| 227 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 228 | identity = True ) |
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| 229 | |
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| 230 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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| 231 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 232 | identity = True ) |
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| 233 | |
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| 234 | mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size, |
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| 235 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 236 | identity = True ) |
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| 237 | |
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| 238 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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| 239 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 240 | identity = True ) |
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| 241 | |
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| 242 | ### local global vsegs for kernel / same virtual address / different physical address |
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| 243 | |
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| 244 | for x in xrange( x_size ): |
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| 245 | for y in xrange( y_size ): |
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| 246 | cluster_xy = (x << y_width) + y; |
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| 247 | |
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| 248 | mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, |
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| 249 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 250 | binpath = 'build/kernel/kernel.elf', local = True ) |
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| 251 | |
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| 252 | mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, |
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| 253 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 254 | binpath = 'build/kernel/kernel.elf', local = True ) |
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| 255 | |
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| 256 | ### shared global vsegs for kernel |
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| 257 | |
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| 258 | mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, |
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| 259 | 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 260 | binpath = 'build/kernel/kernel.elf', local = False ) |
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| 261 | |
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| 262 | mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, |
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| 263 | '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 264 | binpath = 'build/kernel/kernel.elf', local = False ) |
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| 265 | |
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| 266 | ### global vsegs for external peripherals / identity mapping |
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| 267 | |
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| 268 | mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', |
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| 269 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', |
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| 270 | identity = True ) |
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| 271 | |
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| 272 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', |
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| 273 | vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', |
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| 274 | identity = True ) |
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| 275 | |
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| 276 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', |
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| 277 | vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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| 278 | identity = True ) |
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| 279 | |
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| 280 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', |
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| 281 | vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', |
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| 282 | identity = True ) |
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| 283 | |
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| 284 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', |
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| 285 | vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', |
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| 286 | identity = True ) |
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| 287 | |
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| 288 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', |
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| 289 | vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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| 290 | identity = True ) |
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| 291 | |
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| 292 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', |
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| 293 | vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', |
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| 294 | identity = True ) |
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| 295 | |
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| 296 | mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', |
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| 297 | vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', |
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| 298 | identity = True ) |
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| 299 | |
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| 300 | ### global vsegs for internal peripherals, and for schedulers |
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| 301 | ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) |
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| 302 | |
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| 303 | for x in xrange( x_size ): |
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| 304 | for y in xrange( y_size ): |
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| 305 | cluster_xy = (x << y_width) + y; |
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| 306 | offset = cluster_xy * peri_increment |
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| 307 | |
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| 308 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, |
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| 309 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) |
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| 310 | |
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| 311 | mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, |
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| 312 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA' ) |
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| 313 | |
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| 314 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, |
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| 315 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) |
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| 316 | |
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| 317 | mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, |
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| 318 | 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) |
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| 319 | |
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| 320 | ### return mapping ### |
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| 321 | |
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| 322 | return mapping |
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| 323 | |
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| 324 | ################################# platform test ####################################################### |
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| 325 | |
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| 326 | if __name__ == '__main__': |
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| 327 | |
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| 328 | mapping = arch( x_size = 2, |
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| 329 | y_size = 2, |
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| 330 | nb_procs = 2 ) |
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| 331 | |
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| 332 | # print mapping.netbsd_dts() |
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| 333 | |
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| 334 | print mapping.xml() |
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| 335 | |
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| 336 | # print mapping.giet_vsegs() |
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| 337 | |
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| 338 | |
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| 339 | # Local Variables: |
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| 340 | # tab-width: 4; |
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| 341 | # c-basic-offset: 4; |
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| 342 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 343 | # indent-tabs-mode: nil; |
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| 344 | # End: |
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| 345 | # |
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| 346 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 347 | |
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