1 | #!/usr/bin/env python |
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2 | |
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3 | from math import log, ceil |
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4 | from mapping import * |
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5 | |
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6 | ################################################################################## |
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7 | # file : arch.py (for the tsar_generic_iob architecture) |
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8 | # date : may 2014 |
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9 | # author : Alain Greiner |
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10 | ################################################################################## |
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11 | # This file contains a mapping generator for the "tsar_generic_iob" platform. |
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12 | # This includes both the hardware architecture (clusters, processors, peripherals, |
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13 | # physical space segmentation) and the mapping of all boot and kernel objects |
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14 | # (global vsegs). |
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15 | # |
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16 | # This platform includes 6 external peripherals, accessible through an IOB |
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17 | # components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. |
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18 | # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA, PIC. |
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19 | # |
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20 | # All clusters contain (nb_procs) processors, one L2 cache, one XCU, and |
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21 | # one DMA controller. |
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22 | # |
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23 | # The "constructor" parameters are: |
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24 | # - x_size : number of clusters in a row |
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25 | # - y_size : number of clusters in a column |
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26 | # - nb_procs : number of processors per cluster |
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27 | # - nb_ttys : number of TTY channels |
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28 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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29 | # |
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30 | # The other hardware parameters are: |
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31 | # - nb_nics : number of NIC channels |
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32 | # - nb_cmas : number of CMA channels |
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33 | # - x_io : cluster_io x coordinate |
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34 | # - y_io : cluster_io y coordinate |
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35 | # - x_width : number of bits for x coordinate |
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36 | # - y_width : number of bits for y coordinate |
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37 | # - paddr_width : number of bits for physical address |
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38 | # - irq_per_proc : number of input IRQs per processor |
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39 | # - use_ramdisk : use a ramdisk when True |
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40 | # - vseg_increment : address increment for replicated peripherals |
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41 | # |
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42 | # Regarding the boot and kernel vsegs mapping : |
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43 | # - We use one big physical page (2 Mbytes) for the preloader and the four |
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44 | # boot vsegs, all allocated in cluster[0,0]. |
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45 | # - We use one big page per cluster for the replicated kernel code vsegs. |
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46 | # - We use one big page in cluster[0][0] for the kernel data vseg. |
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47 | # - We use one big page per cluster for the distributed kernel heap vsegs. |
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48 | # - We use one big page per cluster for the distributed ptab vsegs. |
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49 | # - We use small physical pages (4 Kbytes) per cluster for the schedulers. |
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50 | # - We use one big page for each external peripheral in IO cluster, |
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51 | # - We use one small page per cluster for each internal peripheral. |
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52 | ################################################################################## |
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53 | |
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54 | ######################## |
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55 | def arch( x_size = 2, |
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56 | y_size = 2, |
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57 | nb_procs = 2, |
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58 | nb_ttys = 1, |
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59 | fbf_width = 128 ): |
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60 | |
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61 | ### define architecture constants |
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62 | |
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63 | nb_nics = 1 |
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64 | nb_cmas = 2 |
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65 | x_io = 0 |
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66 | y_io = 0 |
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67 | x_width = 4 |
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68 | y_width = 4 |
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69 | p_width = 4 |
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70 | paddr_width = 40 |
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71 | irq_per_proc = 4 |
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72 | use_ramdisk = False |
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73 | peri_increment = 0x10000 # distributed peripherals vbase address increment |
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74 | |
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75 | ### parameters checking |
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76 | |
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77 | assert( nb_procs <= (1 << p_width) ) |
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78 | |
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79 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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80 | or (x_size == 8) or (x_size == 16) ) |
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81 | |
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82 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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83 | or (y_size == 8) or (y_size == 16) ) |
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84 | |
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85 | assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) |
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86 | |
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87 | assert( ((x_io == 0) and (y_io == 0)) or |
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88 | ((x_io == x_size-1) and (y_io == y_size-1)) ) |
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89 | |
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90 | ### define type and name |
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91 | |
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92 | platform_type = 'tsar_iob' |
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93 | platform_name = '%s_%d_%d_%d' % ( platform_type, x_size, y_size , nb_procs ) |
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94 | |
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95 | ### define physical segments replicated in all clusters |
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96 | |
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97 | ram_base = 0x0000000000 |
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98 | ram_size = 0x1000000 # 16 Mbytes |
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99 | |
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100 | xcu_base = 0x00B0000000 |
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101 | xcu_size = 0x1000 # 4 Kbytes |
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102 | |
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103 | dma_base = 0x00B1000000 |
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104 | dma_size = 0x1000 # 4 Kbytes |
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105 | |
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106 | mmc_base = 0x00B2000000 |
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107 | mmc_size = 0x1000 # 4 Kbytes |
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108 | |
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109 | ### define physical segments for external peripherals |
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110 | ## These segments are only defined in cluster_io |
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111 | |
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112 | bdv_base = 0x00B3000000 |
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113 | bdv_size = 0x1000 # 4kbytes |
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114 | |
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115 | tty_base = 0x00B4000000 |
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116 | tty_size = 0x4000 # 16 Kbytes |
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117 | |
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118 | nic_base = 0x00B5000000 |
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119 | nic_size = 0x80000 # 512 kbytes |
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120 | |
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121 | cma_base = 0x00B6000000 |
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122 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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123 | |
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124 | fbf_base = 0x00B7000000 |
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125 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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126 | |
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127 | pic_base = 0x00B8000000 |
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128 | pic_size = 0x1000 # 4 Kbytes |
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129 | |
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130 | iob_base = 0x00BE000000 |
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131 | iob_size = 0x1000 # 4 bytes |
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132 | |
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133 | rom_base = 0x00BFC00000 |
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134 | rom_size = 0x4000 # 16 Kbytes |
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135 | |
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136 | ### define bootloader vsegs base addresses and sizes |
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137 | ### We want to pack these 4 vsegs in the same big page |
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138 | ### => boot cost is one BIG page in cluster[0][0] |
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139 | |
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140 | boot_mapping_vbase = 0x00000000 # ident |
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141 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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142 | |
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143 | boot_code_vbase = 0x00080000 # ident |
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144 | boot_code_size = 0x00040000 # 256 Kbytes |
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145 | |
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146 | boot_data_vbase = 0x000C0000 # ident |
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147 | boot_data_size = 0x000C0000 # 768 Kbytes |
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148 | |
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149 | boot_stack_vbase = 0x00180000 # ident |
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150 | boot_stack_size = 0x00080000 # 512 Kbytes |
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151 | |
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152 | ### define kernel vsegs base addresses and sizes |
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153 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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154 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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155 | |
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156 | kernel_code_vbase = 0x80000000 |
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157 | kernel_code_size = 0x00100000 # 1 Mbytes per cluster |
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158 | |
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159 | kernel_init_vbase = 0x80100000 |
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160 | kernel_init_size = 0x00100000 # 1 Mbytes per cluster |
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161 | |
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162 | kernel_data_vbase = 0x90000000 |
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163 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] |
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164 | |
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165 | kernel_ptab_vbase = 0xE0000000 |
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166 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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167 | |
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168 | kernel_heap_vbase = 0xD0000000 |
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169 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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170 | |
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171 | kernel_sched_vbase = 0xA0000000 |
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172 | kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster |
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173 | |
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174 | ######################### |
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175 | ### create mapping |
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176 | ######################### |
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177 | |
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178 | mapping = Mapping( name = platform_name, |
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179 | x_size = x_size, |
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180 | y_size = y_size, |
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181 | nprocs = nb_procs, |
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182 | x_width = x_width, |
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183 | y_width = y_width, |
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184 | p_width = p_width, |
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185 | paddr_width = paddr_width, |
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186 | coherence = True, |
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187 | irq_per_proc = irq_per_proc, |
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188 | use_ramdisk = use_ramdisk, |
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189 | x_io = x_io, |
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190 | y_io = y_io, |
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191 | peri_increment = peri_increment, |
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192 | ram_base = ram_base, |
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193 | ram_size = ram_size ) |
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194 | |
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195 | |
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196 | ############################# |
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197 | ### Hardware Components |
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198 | ############################# |
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199 | |
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200 | for x in xrange( x_size ): |
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201 | for y in xrange( y_size ): |
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202 | cluster_xy = (x << y_width) + y; |
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203 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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204 | |
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205 | ### components replicated in all clusters |
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206 | ram = mapping.addRam( 'RAM', base = ram_base + offset, |
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207 | size = ram_size ) |
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208 | |
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209 | mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, |
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210 | size = mmc_size, ptype = 'MMC' ) |
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211 | |
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212 | dma = mapping.addPeriph( 'DMA', base = dma_base + offset, |
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213 | size = dma_size, ptype = 'DMA', |
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214 | channels = nb_procs ) |
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215 | |
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216 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, |
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217 | size = xcu_size, ptype = 'XCU', |
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218 | channels = nb_procs * irq_per_proc, |
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219 | arg0 = 32, arg1 = 32, arg2 = 32 ) |
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220 | |
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221 | mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) |
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222 | |
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223 | for i in xrange ( dma.channels ): |
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224 | mapping.addIrq( xcu, index = 1+i, isrtype = 'ISR_DMA', |
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225 | channel = i ) |
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226 | |
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227 | for p in xrange ( nb_procs ): |
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228 | mapping.addProc( x, y, p ) |
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229 | |
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230 | ### external peripherals in cluster_io |
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231 | if ( (x==x_io) and (y==y_io) ): |
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232 | |
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233 | iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size, |
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234 | ptype = 'IOB' ) |
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235 | |
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236 | bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size, |
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237 | ptype = 'IOC', subtype = 'BDV' ) |
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238 | |
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239 | tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size, |
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240 | ptype = 'TTY', channels = nb_ttys ) |
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241 | |
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242 | nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size, |
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243 | ptype = 'NIC', channels = nb_nics ) |
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244 | |
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245 | cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size, |
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246 | ptype = 'CMA', channels = nb_cmas ) |
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247 | |
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248 | fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size, |
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249 | ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width ) |
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250 | |
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251 | rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, |
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252 | ptype = 'ROM' ) |
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253 | |
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254 | pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size, |
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255 | ptype = 'PIC', channels = 32 ) |
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256 | |
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257 | mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) |
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258 | mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) |
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259 | |
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260 | mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) |
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261 | mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) |
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262 | |
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263 | mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) |
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264 | mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) |
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265 | mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) |
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266 | mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) |
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267 | |
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268 | mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) |
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269 | |
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270 | mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) |
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271 | mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 ) |
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272 | mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 ) |
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273 | mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 ) |
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274 | mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 ) |
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275 | mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 ) |
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276 | mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 ) |
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277 | mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 ) |
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278 | |
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279 | |
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280 | #################################### |
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281 | ### Boot & Kernel vsegs mapping |
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282 | #################################### |
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283 | |
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284 | ### global vsegs for boot_loader |
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285 | ### we want to pack those 4 vsegs in the same big page |
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286 | ### => same flags CXW_ / identity mapping / non local / big page |
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287 | |
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288 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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289 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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290 | identity = True , local = False, big = True ) |
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291 | |
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292 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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293 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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294 | identity = True , local = False, big = True ) |
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295 | |
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296 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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297 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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298 | identity = True , local = False, big = True ) |
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299 | |
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300 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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301 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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302 | identity = True , local = False, big = True ) |
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303 | |
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304 | ### global vseg kernel_data : big / non local |
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305 | ### Only mapped in cluster[0][0] |
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306 | mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, |
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307 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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308 | binpath = 'build/kernel/kernel.elf', |
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309 | local = False, big = True ) |
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310 | |
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311 | ### global vsegs kernel_code, kernel_init : big / local |
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312 | ### replicated in all clusters with the same name & same vbase |
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313 | for x in xrange( x_size ): |
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314 | for y in xrange( y_size ): |
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315 | mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, |
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316 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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317 | binpath = 'build/kernel/kernel.elf', |
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318 | local = True, big = True ) |
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319 | |
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320 | mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, |
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321 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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322 | binpath = 'build/kernel/kernel.elf', |
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323 | local = True, big = True ) |
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324 | |
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325 | ### Global vsegs kernel_ptab_x_y : big / non local |
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326 | ### one vseg per cluster: name indexed by (x,y) |
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327 | for x in xrange( x_size ): |
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328 | for y in xrange( y_size ): |
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329 | offset = ((x << y_width) + y) * kernel_ptab_size |
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330 | base = kernel_ptab_vbase + offset |
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331 | mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size, |
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332 | 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', |
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333 | local = False , big = True ) |
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334 | |
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335 | ### global vsegs kernel_sched_x_y : small / non local |
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336 | ### one vseg per cluster with name indexed by (x,y) |
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337 | for x in xrange( x_size ): |
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338 | for y in xrange( y_size ): |
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339 | offset = ((x << y_width) + y) * kernel_sched_size |
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340 | mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), |
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341 | kernel_sched_vbase + offset , kernel_sched_size, |
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342 | 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM', |
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343 | local = False, big = False ) |
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344 | |
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345 | ### global vsegs kernel_heap_x_y : big / non local |
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346 | ### one vseg per cluster with name indexed by (x,y) |
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347 | for x in xrange( x_size ): |
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348 | for y in xrange( y_size ): |
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349 | offset = ((x << y_width) + y) * kernel_heap_size |
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350 | mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), |
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351 | kernel_heap_vbase + offset , kernel_heap_size, |
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352 | 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', |
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353 | local = False, big = True ) |
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354 | |
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355 | ### global vsegs for external peripherals : non local / big page |
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356 | mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', |
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357 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', |
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358 | local = False, big = True ) |
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359 | |
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360 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', |
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361 | vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', |
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362 | local = False, big = True ) |
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363 | |
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364 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', |
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365 | vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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366 | local = False, big = True ) |
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367 | |
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368 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', |
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369 | vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', |
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370 | local = False, big = True ) |
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371 | |
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372 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', |
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373 | vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', |
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374 | local = False, big = True ) |
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375 | |
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376 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', |
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377 | vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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378 | local = False, big = True ) |
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379 | |
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380 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', |
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381 | vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', |
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382 | local = False, big = True ) |
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383 | |
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384 | mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', |
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385 | vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', |
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386 | local = False, big = True ) |
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387 | |
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388 | ### global vsegs for internal peripherals : non local / small pages |
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389 | ### allocated in all clusters with name indexed by (x,y) |
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390 | ### as vbase address is incremented by (cluster_xy * vseg_increment) |
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391 | for x in xrange( x_size ): |
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392 | for y in xrange( y_size ): |
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393 | offset = ((x << y_width) + y) * peri_increment |
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394 | |
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395 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, |
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396 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', |
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397 | local = False, big = False ) |
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398 | |
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399 | mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, |
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400 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA', |
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401 | local = False, big = False ) |
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402 | |
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403 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, |
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404 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', |
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405 | local = False, big = False ) |
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406 | |
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407 | return mapping |
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408 | |
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409 | ################################# platform test #################################### |
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410 | |
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411 | if __name__ == '__main__': |
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412 | |
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413 | mapping = arch( x_size = 2, |
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414 | y_size = 2, |
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415 | nb_procs = 2 ) |
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416 | |
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417 | # print mapping.netbsd_dts() |
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418 | |
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419 | print mapping.xml() |
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420 | |
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421 | # print mapping.giet_vsegs() |
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422 | |
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423 | |
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424 | # Local Variables: |
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425 | # tab-width: 4; |
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426 | # c-basic-offset: 4; |
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427 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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428 | # indent-tabs-mode: nil; |
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429 | # End: |
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430 | # |
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431 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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432 | |
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