| 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from math import log, ceil |
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| 4 | from mapping import * |
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| 5 | |
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| 6 | ################################################################################## |
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| 7 | # file : arch.py (for the tsar_generic_iob architecture) |
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| 8 | # date : may 2014 |
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| 9 | # author : Alain Greiner |
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| 10 | ################################################################################## |
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| 11 | # This file contains a mapping generator for the "tsar_generic_iob" platform. |
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| 12 | # This includes both the hardware architecture (clusters, processors, peripherals, |
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| 13 | # physical space segmentation) and the mapping of all boot and kernel objects |
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| 14 | # (global vsegs). |
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| 15 | # |
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| 16 | # This platform includes 7 external peripherals, accessible through an IOB |
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| 17 | # components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. |
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| 18 | # Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC. |
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| 19 | # |
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| 20 | # All clusters contain (nb_procs) processors, one L2 cache, one XCU, and |
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| 21 | # one optional hardware coprocessor connected to a MWMR_DMA controller. |
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| 22 | # |
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| 23 | # The "constructor" parameters (defined in Makefile) are: |
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| 24 | # - x_size : number of clusters in a row |
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| 25 | # - y_size : number of clusters in a column |
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| 26 | # - nb_procs : number of processors per cluster |
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| 27 | # - nb_ttys : number of TTY channels |
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| 28 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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| 29 | # - ioc_type : can be 'BDV','HBA','SDC', but not 'RDK' |
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| 30 | # |
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| 31 | # |
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| 32 | # The other hardware parameters (defined in this script) are: |
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| 33 | # - nb_nics : number of NIC channels |
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| 34 | # - nb_cmas : number of CMA channels |
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| 35 | # - x_io : cluster_io x coordinate |
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| 36 | # - y_io : cluster_io y coordinate |
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| 37 | # - x_width : number of bits for x coordinate |
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| 38 | # - y_width : number of bits for y coordinate |
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| 39 | # - paddr_width : number of bits for physical address |
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| 40 | # - irq_per_proc : number of input IRQs per processor |
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| 41 | # - use_ramdisk : use a ramdisk when True |
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| 42 | # - vseg_increment : address increment for replicated vsegs |
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| 43 | # - mwr_type : coprocessor type / can be 'GCD','DCT','NOPE' |
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| 44 | # - use_dma : one single channel DMA per cluster if non zero |
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| 45 | # |
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| 46 | # Regarding the boot and kernel vsegs mapping : |
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| 47 | # - We use one big physical page (2 Mbytes) for the preloader and the four |
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| 48 | # boot vsegs, all allocated in cluster[0,0]. |
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| 49 | # - We use one big page per cluster for the replicated kernel code vsegs. |
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| 50 | # - We use one big page in cluster[0][0] for the kernel data vseg. |
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| 51 | # - We use one big page per cluster for the distributed kernel heap vsegs. |
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| 52 | # - We use one big page per cluster for the distributed ptab vsegs. |
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| 53 | # - We use small physical pages (4 Kbytes) per cluster for the schedulers. |
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| 54 | # - We use one big page for each external peripheral in IO cluster, |
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| 55 | # - We use one small page per cluster for each internal peripheral. |
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| 56 | ################################################################################## |
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| 57 | |
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| 58 | ######################## |
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| 59 | def arch( x_size = 2, |
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| 60 | y_size = 2, |
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| 61 | nb_procs = 2, |
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| 62 | nb_ttys = 1, |
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| 63 | fbf_width = 128, |
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| 64 | ioc_type = 'HBA' ): |
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| 65 | |
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| 66 | ### define architecture constants |
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| 67 | |
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| 68 | nb_nics = 1 |
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| 69 | nb_cmas = 2 |
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| 70 | x_io = 0 |
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| 71 | y_io = 0 |
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| 72 | x_width = 4 |
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| 73 | y_width = 4 |
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| 74 | p_width = 4 |
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| 75 | paddr_width = 40 |
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| 76 | irq_per_proc = 4 |
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| 77 | peri_increment = 0x10000 |
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| 78 | mwr_type = 'CPY' |
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| 79 | |
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| 80 | ### constructor parameters checking |
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| 81 | |
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| 82 | assert( nb_procs <= (1 << p_width) ) |
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| 83 | |
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| 84 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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| 85 | or (x_size == 8) or (x_size == 16) ) |
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| 86 | |
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| 87 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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| 88 | or (y_size == 8) or (y_size == 16) ) |
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| 89 | |
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| 90 | assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) |
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| 91 | |
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| 92 | assert( ((x_io == 0) and (y_io == 0)) or |
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| 93 | ((x_io == x_size-1) and (y_io == y_size-1)) ) |
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| 94 | |
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| 95 | assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' ] ) |
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| 96 | |
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| 97 | assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' , 'NONE' ] ) |
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| 98 | |
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| 99 | ### define platform name |
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| 100 | |
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| 101 | platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_procs ) |
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| 102 | platform_name += '_%d_%d_%s' % ( fbf_width , nb_ttys , ioc_type ) |
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| 103 | |
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| 104 | ### define physical segments replicated in all clusters |
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| 105 | |
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| 106 | ram_base = 0x0000000000 |
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| 107 | ram_size = 0x1000000 # 16 Mbytes |
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| 108 | |
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| 109 | xcu_base = 0x00B0000000 |
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| 110 | xcu_size = 0x1000 # 4 Kbytes |
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| 111 | |
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| 112 | mwr_base = 0x00B1000000 |
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| 113 | mwr_size = 0x1000 # 4 Kbytes |
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| 114 | |
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| 115 | mmc_base = 0x00B2000000 |
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| 116 | mmc_size = 0x1000 # 4 Kbytes |
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| 117 | |
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| 118 | ### define physical segments for external peripherals |
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| 119 | ## These segments are only defined in cluster_io |
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| 120 | |
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| 121 | ioc_base = 0x00B3000000 |
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| 122 | ioc_size = 0x1000 # 4 Kbytes |
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| 123 | |
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| 124 | tty_base = 0x00B4000000 |
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| 125 | tty_size = 0x4000 # 16 Kbytes |
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| 126 | |
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| 127 | nic_base = 0x00B5000000 |
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| 128 | nic_size = 0x80000 # 512 kbytes |
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| 129 | |
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| 130 | cma_base = 0x00B6000000 |
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| 131 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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| 132 | |
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| 133 | fbf_base = 0x00B7000000 |
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| 134 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 135 | |
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| 136 | pic_base = 0x00B8000000 |
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| 137 | pic_size = 0x1000 # 4 Kbytes |
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| 138 | |
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| 139 | iob_base = 0x00BE000000 |
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| 140 | iob_size = 0x1000 # 4 bytes |
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| 141 | |
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| 142 | rom_base = 0x00BFC00000 |
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| 143 | rom_size = 0x4000 # 16 Kbytes |
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| 144 | |
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| 145 | ### define bootloader vsegs base addresses and sizes |
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| 146 | ### We want to pack these 4 vsegs in the same big page |
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| 147 | ### => boot cost is one BIG page in cluster[0][0] |
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| 148 | |
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| 149 | boot_mapping_vbase = 0x00000000 # ident |
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| 150 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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| 151 | |
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| 152 | boot_code_vbase = 0x00080000 # ident |
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| 153 | boot_code_size = 0x00040000 # 256 Kbytes |
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| 154 | |
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| 155 | boot_data_vbase = 0x000C0000 # ident |
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| 156 | boot_data_size = 0x000C0000 # 768 Kbytes |
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| 157 | |
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| 158 | boot_stack_vbase = 0x00180000 # ident |
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| 159 | boot_stack_size = 0x00080000 # 512 Kbytes |
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| 160 | |
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| 161 | ### define kernel vsegs base addresses and sizes |
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| 162 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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| 163 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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| 164 | |
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| 165 | kernel_code_vbase = 0x80000000 |
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| 166 | kernel_code_size = 0x00100000 # 1 Mbytes per cluster |
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| 167 | |
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| 168 | kernel_init_vbase = 0x80100000 |
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| 169 | kernel_init_size = 0x00100000 # 1 Mbytes per cluster |
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| 170 | |
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| 171 | kernel_data_vbase = 0x90000000 |
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| 172 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] |
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| 173 | |
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| 174 | kernel_ptab_vbase = 0xE0000000 |
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| 175 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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| 176 | |
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| 177 | kernel_heap_vbase = 0xD0000000 |
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| 178 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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| 179 | |
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| 180 | kernel_sched_vbase = 0xA0000000 |
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| 181 | kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster |
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| 182 | |
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| 183 | ######################### |
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| 184 | ### create mapping |
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| 185 | ######################### |
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| 186 | |
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| 187 | mapping = Mapping( name = platform_name, |
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| 188 | x_size = x_size, |
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| 189 | y_size = y_size, |
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| 190 | nprocs = nb_procs, |
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| 191 | x_width = x_width, |
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| 192 | y_width = y_width, |
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| 193 | p_width = p_width, |
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| 194 | paddr_width = paddr_width, |
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| 195 | coherence = True, |
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| 196 | irq_per_proc = irq_per_proc, |
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| 197 | use_ramdisk = (ioc_type == 'RDK'), |
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| 198 | x_io = x_io, |
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| 199 | y_io = y_io, |
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| 200 | peri_increment = peri_increment, |
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| 201 | ram_base = ram_base, |
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| 202 | ram_size = ram_size ) |
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| 203 | |
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| 204 | |
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| 205 | ############################# |
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| 206 | ### Hardware Components |
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| 207 | ############################# |
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| 208 | |
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| 209 | for x in xrange( x_size ): |
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| 210 | for y in xrange( y_size ): |
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| 211 | cluster_xy = (x << y_width) + y; |
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| 212 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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| 213 | |
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| 214 | ### components replicated in all clusters |
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| 215 | mapping.addRam( 'RAM', base = ram_base + offset, |
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| 216 | size = ram_size ) |
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| 217 | |
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| 218 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, |
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| 219 | size = xcu_size, ptype = 'XCU', |
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| 220 | channels = nb_procs * irq_per_proc, |
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| 221 | arg0 = 32, arg1 = 32, arg2 = 32 ) |
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| 222 | |
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| 223 | mapping.addPeriph( 'MMC', base = mmc_base + offset, |
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| 224 | size = mmc_size, ptype = 'MMC' ) |
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| 225 | |
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| 226 | if ( mwr_type == 'GCD' ): |
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| 227 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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| 228 | size = mwr_size, ptype = 'MWR', subtype = 'GCD', |
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| 229 | arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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| 230 | |
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| 231 | if ( mwr_type == 'DCT' ): |
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| 232 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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| 233 | size = mwr_size, ptype = 'MWR', subtype = 'DCT', |
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| 234 | arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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| 235 | |
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| 236 | if ( mwr_type == 'CPY' ): |
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| 237 | mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, |
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| 238 | size = mwr_size, ptype = 'MWR', subtype = 'CPY', |
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| 239 | arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) |
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| 240 | |
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| 241 | mapping.addIrq( xcu, index = 0, src = mmc, isrtype = 'ISR_MMC' ) |
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| 242 | mapping.addIrq( xcu, index = 1, src = mwr, isrtype = 'ISR_MWR' ) |
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| 243 | |
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| 244 | for p in xrange ( nb_procs ): |
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| 245 | mapping.addProc( x , y , p ) |
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| 246 | |
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| 247 | ### external peripherals in cluster_io |
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| 248 | if ( (x==x_io) and (y==y_io) ): |
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| 249 | |
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| 250 | iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size, |
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| 251 | ptype = 'IOB' ) |
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| 252 | |
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| 253 | ioc = mapping.addPeriph( 'IOC', base = ioc_base + offset, size = ioc_size, |
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| 254 | ptype = 'IOC', subtype = ioc_type ) |
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| 255 | |
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| 256 | tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size, |
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| 257 | ptype = 'TTY', channels = nb_ttys ) |
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| 258 | |
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| 259 | nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size, |
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| 260 | ptype = 'NIC', channels = nb_nics ) |
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| 261 | |
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| 262 | cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size, |
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| 263 | ptype = 'CMA', channels = nb_cmas ) |
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| 264 | |
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| 265 | fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size, |
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| 266 | ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width ) |
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| 267 | |
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| 268 | rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, |
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| 269 | ptype = 'ROM' ) |
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| 270 | |
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| 271 | pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size, |
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| 272 | ptype = 'PIC', channels = 32 ) |
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| 273 | |
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| 274 | mapping.addIrq( pic, index = 0, src = nic, |
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| 275 | isrtype = 'ISR_NIC_RX', channel = 0 ) |
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| 276 | mapping.addIrq( pic, index = 1, src = nic, |
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| 277 | isrtype = 'ISR_NIC_RX', channel = 1 ) |
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| 278 | |
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| 279 | mapping.addIrq( pic, index = 2, src = nic, |
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| 280 | isrtype = 'ISR_NIC_TX', channel = 0 ) |
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| 281 | mapping.addIrq( pic, index = 3, src = nic, |
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| 282 | isrtype = 'ISR_NIC_TX', channel = 1 ) |
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| 283 | |
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| 284 | mapping.addIrq( pic, index = 4, src = cma, |
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| 285 | isrtype = 'ISR_CMA', channel = 0 ) |
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| 286 | mapping.addIrq( pic, index = 5, src = cma, |
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| 287 | isrtype = 'ISR_CMA', channel = 1 ) |
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| 288 | mapping.addIrq( pic, index = 6, src = cma, |
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| 289 | isrtype = 'ISR_CMA', channel = 2 ) |
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| 290 | mapping.addIrq( pic, index = 7, src = cma, |
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| 291 | isrtype = 'ISR_CMA', channel = 3 ) |
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| 292 | |
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| 293 | if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV' |
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| 294 | if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA' |
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| 295 | if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC' |
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| 296 | |
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| 297 | mapping.addIrq( pic, index = 8, src = ioc, |
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| 298 | isrtype = isr_ioc, channel = 0 ) |
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| 299 | mapping.addIrq( pic, index = 16, src = tty, |
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| 300 | isrtype = 'ISR_TTY_RX', channel = 0 ) |
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| 301 | mapping.addIrq( pic, index = 17, src = tty, |
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| 302 | isrtype = 'ISR_TTY_RX', channel = 1 ) |
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| 303 | mapping.addIrq( pic, index = 18, src = tty, |
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| 304 | isrtype = 'ISR_TTY_RX', channel = 2 ) |
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| 305 | mapping.addIrq( pic, index = 19, src = tty, |
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| 306 | isrtype = 'ISR_TTY_RX', channel = 3 ) |
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| 307 | mapping.addIrq( pic, index = 20, src = tty, |
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| 308 | isrtype = 'ISR_TTY_RX', channel = 4 ) |
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| 309 | mapping.addIrq( pic, index = 21, src = tty, |
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| 310 | isrtype = 'ISR_TTY_RX', channel = 5 ) |
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| 311 | mapping.addIrq( pic, index = 22, src = tty, |
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| 312 | isrtype = 'ISR_TTY_RX', channel = 6 ) |
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| 313 | mapping.addIrq( pic, index = 23, src = tty, |
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| 314 | isrtype = 'ISR_TTY_RX', channel = 7 ) |
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| 315 | |
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| 316 | |
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| 317 | #################################### |
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| 318 | ### Boot & Kernel vsegs mapping |
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| 319 | #################################### |
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| 320 | |
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| 321 | ### global vsegs for boot_loader |
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| 322 | ### we want to pack those 4 vsegs in the same big page |
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| 323 | ### => same flags CXW_ / identity mapping / non local / big page |
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| 324 | |
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| 325 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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| 326 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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| 327 | identity = True , local = False, big = True ) |
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| 328 | |
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| 329 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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| 330 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 331 | identity = True , local = False, big = True ) |
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| 332 | |
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| 333 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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| 334 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 335 | identity = True , local = False, big = True ) |
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| 336 | |
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| 337 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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| 338 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 339 | identity = True , local = False, big = True ) |
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| 340 | |
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| 341 | ### global vseg kernel_data : big / non local |
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| 342 | ### Only mapped in cluster[0][0] |
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| 343 | mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, |
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| 344 | 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 345 | binpath = 'build/kernel/kernel.elf', |
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| 346 | local = False, big = True ) |
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| 347 | |
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| 348 | ### global vsegs kernel_code, kernel_init : big / local |
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| 349 | ### replicated in all clusters with indexed name & same vbase |
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| 350 | for x in xrange( x_size ): |
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| 351 | for y in xrange( y_size ): |
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| 352 | mapping.addGlobal( 'seg_kernel_code_%d_%d' %(x,y), |
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| 353 | kernel_code_vbase, kernel_code_size, |
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| 354 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 355 | binpath = 'build/kernel/kernel.elf', |
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| 356 | local = True, big = True ) |
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| 357 | |
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| 358 | mapping.addGlobal( 'seg_kernel_init_%d_%d' %(x,y), |
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| 359 | kernel_init_vbase, kernel_init_size, |
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| 360 | 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', |
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| 361 | binpath = 'build/kernel/kernel.elf', |
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| 362 | local = True, big = True ) |
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| 363 | |
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| 364 | ### Global vsegs kernel_ptab_x_y : big / non local |
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| 365 | ### one vseg per cluster: name indexed by (x,y) |
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| 366 | for x in xrange( x_size ): |
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| 367 | for y in xrange( y_size ): |
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| 368 | offset = ((x << y_width) + y) * kernel_ptab_size |
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| 369 | base = kernel_ptab_vbase + offset |
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| 370 | mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size, |
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| 371 | 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', |
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| 372 | local = False , big = True ) |
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| 373 | |
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| 374 | ### global vsegs kernel_sched_x_y : small / non local |
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| 375 | ### one vseg per cluster with name indexed by (x,y) |
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| 376 | for x in xrange( x_size ): |
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| 377 | for y in xrange( y_size ): |
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| 378 | offset = ((x << y_width) + y) * kernel_sched_size |
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| 379 | mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), |
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| 380 | kernel_sched_vbase + offset , kernel_sched_size, |
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| 381 | 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM', |
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| 382 | local = False, big = False ) |
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| 383 | |
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| 384 | ### global vsegs kernel_heap_x_y : big / non local |
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| 385 | ### one vseg per cluster with name indexed by (x,y) |
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| 386 | for x in xrange( x_size ): |
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| 387 | for y in xrange( y_size ): |
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| 388 | offset = ((x << y_width) + y) * kernel_heap_size |
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| 389 | mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), |
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| 390 | kernel_heap_vbase + offset , kernel_heap_size, |
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| 391 | 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', |
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| 392 | local = False, big = True ) |
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| 393 | |
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| 394 | ### global vsegs for external peripherals : non local / big page |
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| 395 | mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', |
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| 396 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', |
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| 397 | local = False, big = True ) |
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| 398 | |
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| 399 | mapping.addGlobal( 'seg_ioc', ioc_base, ioc_size, '__W_', |
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| 400 | vtype = 'PERI', x = 0, y = 0, pseg = 'IOC', |
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| 401 | local = False, big = True ) |
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| 402 | |
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| 403 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', |
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| 404 | vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', |
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| 405 | local = False, big = True ) |
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| 406 | |
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| 407 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', |
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| 408 | vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', |
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| 409 | local = False, big = True ) |
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| 410 | |
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| 411 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', |
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| 412 | vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', |
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| 413 | local = False, big = True ) |
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| 414 | |
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| 415 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', |
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| 416 | vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', |
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| 417 | local = False, big = True ) |
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| 418 | |
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| 419 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', |
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| 420 | vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', |
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| 421 | local = False, big = True ) |
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| 422 | |
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| 423 | mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', |
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| 424 | vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', |
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| 425 | local = False, big = True ) |
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| 426 | |
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| 427 | ### global vsegs for internal peripherals : non local / small pages |
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| 428 | ### allocated in all clusters with name indexed by (x,y) |
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| 429 | ### as vbase address is incremented by (cluster_xy * vseg_increment) |
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| 430 | for x in xrange( x_size ): |
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| 431 | for y in xrange( y_size ): |
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| 432 | offset = ((x << y_width) + y) * peri_increment |
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| 433 | |
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| 434 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, |
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| 435 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', |
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| 436 | local = False, big = False ) |
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| 437 | |
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| 438 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, |
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| 439 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', |
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| 440 | local = False, big = False ) |
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| 441 | |
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| 442 | if ( mwr_type != 'NONE' ): |
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| 443 | mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size, |
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| 444 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR', |
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| 445 | local = False, big = False ) |
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| 446 | |
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| 447 | return mapping |
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| 448 | |
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| 449 | ################################# platform test #################################### |
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| 450 | |
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| 451 | if __name__ == '__main__': |
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| 452 | |
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| 453 | mapping = arch( x_size = 2, |
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| 454 | y_size = 2, |
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| 455 | nb_procs = 2 ) |
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| 456 | |
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| 457 | # print mapping.netbsd_dts() |
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| 458 | |
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| 459 | print mapping.xml() |
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| 460 | |
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| 461 | # print mapping.giet_vsegs() |
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| 462 | |
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| 463 | |
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| 464 | # Local Variables: |
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| 465 | # tab-width: 4; |
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| 466 | # c-basic-offset: 4; |
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| 467 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 468 | # indent-tabs-mode: nil; |
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| 469 | # End: |
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| 470 | # |
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| 471 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 472 | |
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