1 | #!/usr/bin/env python |
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2 | |
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3 | from arch_classes import * |
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4 | |
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5 | ######################################################################################### |
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6 | # file : arch_info.py for the tsar_generic_iob architecture) |
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7 | # date : august 2016 |
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8 | # author : Alain Greiner |
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9 | ######################################################################################### |
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10 | # This python script defines a specific instance of "tsar_generic_iob" architecture |
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11 | # for the ALMOS-MK operating system. It is used to generate the "hard_config.h" |
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12 | # and the "arch_info.bin files, used by bthe ALMOS-MK bootloader. |
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13 | # |
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14 | # The constructor prototype format is imposed by the genarch.py application, |
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15 | # and should not be modified. |
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16 | # |
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17 | # The "tsar_generic_iob" architecture includes 7 external peripherals, accessed |
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18 | # through an IOB components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. |
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19 | # Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC. |
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20 | # All clusters contain (nb_cores) processors, one L2 cache, one XCU, and |
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21 | # one optional hardware coprocessor connected to a MWMR controller. |
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22 | # |
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23 | # As the "tsar_generic_iob" architecture is generic, the following parameters |
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24 | # are defined as constructor arguments and can be redefined in the Makefile when |
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25 | # a new kernel image is generated : |
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26 | # - x_size : number of clusters in a row (from 1 to 16) |
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27 | # - y_size : number of clusters in a column (from & to 16) |
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28 | # - nb_cores : number of processors per cluster (from 1 to 4) |
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29 | # - nb_ttys : number of TTY channels (can be from 1 to 8) |
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30 | # - nb_nics : number of NIC channels (from 1 to 2) |
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31 | # - nb_cmas : number of CMA channels (from 1 to 4) |
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32 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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33 | # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' |
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34 | # - mwr_type : can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE' |
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35 | # - io_cxy : IO cluster identifier |
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36 | # - boot_cxy : boot cluster identifier |
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37 | # |
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38 | # The following parameters are imposed by the "tsar_generic_iob" architecture: |
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39 | # - devices_max : max number of devices per cluster |
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40 | # - x_width : number of bits for x coordinate |
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41 | # - y_width : number of bits for y coordinate |
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42 | # - paddr_width : number of bits for physical address |
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43 | # - p_width : number of bits for local processor index |
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44 | # - irqs_per_core : number of input IRQs per processor |
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45 | ######################################################################################## |
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46 | |
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47 | ############################ |
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48 | def arch( x_size = 2, |
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49 | y_size = 2, |
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50 | nb_cores = 2, |
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51 | nb_ttys = 1, |
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52 | nb_nics = 1, |
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53 | nb_cmas = 2, |
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54 | fbf_width = 128, |
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55 | ioc_type = 'IOC_BDV', |
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56 | mwr_type = 'MWR_CPY', |
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57 | io_cxy = 0, |
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58 | boot_cxy = 0 ): |
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59 | |
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60 | ### architecture constants |
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61 | |
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62 | p_width = 2 |
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63 | x_width = 4 |
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64 | y_width = 4 |
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65 | paddr_width = 40 |
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66 | irqs_per_core = 4 |
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67 | devices_max = 16 |
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68 | |
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69 | ### constructor parameters checking |
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70 | |
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71 | assert( (x_size == 1) or (x_size == 2) or (x_size == 4) |
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72 | or (x_size == 8) or (x_size == 16) ) |
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73 | |
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74 | assert( (y_size == 1) or (y_size == 2) or (y_size == 4) |
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75 | or (y_size == 8) or (y_size == 16) ) |
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76 | |
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77 | assert( nb_cores <= 4 ) |
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78 | |
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79 | assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) |
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80 | |
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81 | assert( (nb_nics >= 1) and (nb_nics <= 2) ) |
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82 | |
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83 | assert( (nb_cmas >= 1) and (nb_cmas <= 4) ) |
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84 | |
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85 | assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) |
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86 | |
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87 | assert( mwr_type in ['MWR_GCD','MWR_DCT','MWR_CPY'] ) |
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88 | |
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89 | assert( (io_cxy == 0) or (io_cxy == ((x_size-1)<<y_width) + (y_size-1)) ) |
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90 | |
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91 | assert( ((boot_cxy >> y_width) < x_size) and ((boot_cxy & ((1<<y_width)-1)) < y_size) ) |
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92 | |
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93 | ### define platform name |
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94 | |
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95 | platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_cores ) |
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96 | |
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97 | ### define physical segments replicated in all clusters |
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98 | |
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99 | ram_base = 0x0000000000 |
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100 | ram_size = 0x4000000 # 64 Mbytes |
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101 | |
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102 | xcu_base = 0x00B0000000 |
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103 | xcu_size = 0x1000 # 4 Kbytes |
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104 | |
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105 | mwr_base = 0x00B1000000 |
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106 | mwr_size = 0x1000 # 4 Kbytes |
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107 | |
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108 | mmc_base = 0x00B2000000 |
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109 | mmc_size = 0x1000 # 4 Kbytes |
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110 | |
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111 | ### define physical segments for external peripherals |
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112 | ## These segments are only defined in cluster_io |
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113 | |
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114 | ioc_base = 0x00B3000000 |
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115 | ioc_size = 0x1000 # 4 Kbytes |
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116 | |
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117 | tty_base = 0x00B4000000 |
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118 | tty_size = 0x4000 # 16 Kbytes |
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119 | |
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120 | nic_base = 0x00B5000000 |
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121 | nic_size = 0x80000 # 512 kbytes |
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122 | |
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123 | cma_base = 0x00B6000000 |
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124 | cma_size = 0x1000 * nb_cmas # 4 kbytes * nb_cmas |
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125 | |
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126 | fbf_base = 0x00B7000000 |
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127 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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128 | |
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129 | pic_base = 0x00B8000000 |
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130 | pic_size = 0x1000 # 4 Kbytes |
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131 | |
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132 | iob_base = 0x00BE000000 |
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133 | iob_size = 0x1000 # 4 bytes |
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134 | |
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135 | rom_base = 0x00BFC00000 |
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136 | rom_size = 0x4000 # 16 Kbytes |
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137 | |
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138 | ############################ |
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139 | ### call Header constructor |
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140 | ############################ |
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141 | |
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142 | archi = Archinfo( name = platform_name, |
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143 | x_size = x_size, |
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144 | y_size = y_size, |
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145 | cores_max = nb_cores, |
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146 | devices_max = devices_max, |
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147 | paddr_width = paddr_width, |
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148 | x_width = x_width, |
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149 | y_width = y_width, |
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150 | irqs_per_core = irqs_per_core, |
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151 | io_cxy = io_cxy, |
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152 | boot_cxy = boot_cxy, |
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153 | reset_address = rom_base, |
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154 | p_width = p_width ) |
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155 | |
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156 | #################################################### |
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157 | ### construct hardware components for each cluster |
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158 | #################################################### |
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159 | |
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160 | for x in xrange( x_size ): |
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161 | for y in xrange( y_size ): |
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162 | cxy = (x << y_width) + y; |
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163 | offset = cxy << (paddr_width - x_width - y_width) |
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164 | |
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165 | # build devices |
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166 | ram = archi.addDevice( ptype = 'RAM' , |
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167 | base = ram_base + offset, |
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168 | size = ram_size ) |
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169 | |
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170 | xcu = archi.addDevice( ptype = 'XCU', |
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171 | base = xcu_base + offset, |
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172 | size = xcu_size, |
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173 | channels = nb_cores * irqs_per_core, |
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174 | arg0 = 16, |
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175 | arg1 = 16, |
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176 | arg2 = 16 ) |
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177 | |
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178 | mmc = archi.addDevice( ptype = 'MMC', |
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179 | base = mmc_base + offset, |
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180 | size = mmc_size ) |
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181 | archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc, isrtype = 'ISR_MMC' ) |
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182 | |
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183 | if ( mwr_type == 'MWR_GCD' ): |
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184 | mwr = archi.addDevice( ptype = 'MWR_GCD', |
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185 | base = mwr_base + offset, |
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186 | size = mwr_size, |
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187 | arg0 = 2, |
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188 | arg1 = 1, |
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189 | arg2 = 1, |
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190 | arg3 = 0 ) |
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191 | archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) |
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192 | |
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193 | if ( mwr_type == 'MWR_DCT' ): |
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194 | mwr = archi.addDevice( ptype = 'MWR_DCT', |
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195 | base = mwr_base + offset, |
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196 | size = mwr_size, |
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197 | arg0 = 1, |
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198 | arg1 = 1, |
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199 | arg2 = 1, |
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200 | arg3 = 0 ) |
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201 | archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) |
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202 | |
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203 | if ( mwr_type == 'MWR_CPY' ): |
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204 | mwr = archi.addDevice( ptype = 'MWR_CPY', |
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205 | base = mwr_base + offset, |
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206 | size = mwr_size, |
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207 | arg0 = 1, |
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208 | arg1 = 1, |
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209 | arg2 = 1, |
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210 | arg3 = 0 ) |
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211 | archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) |
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212 | |
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213 | if( cxy == io_cxy ): |
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214 | |
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215 | iob = archi.addDevice( ptype = 'IOB', |
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216 | base = iob_base + offset, |
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217 | size = iob_size ) |
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218 | |
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219 | ioc = archi.addDevice( ptype = ioc_type, |
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220 | base = ioc_base + offset, |
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221 | size = ioc_size ) |
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222 | |
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223 | tty = archi.addDevice( ptype = 'TTY', |
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224 | base = tty_base + offset, |
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225 | size = tty_size, |
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226 | channels = nb_ttys ) |
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227 | |
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228 | nic = archi.addDevice( ptype = 'NIC', |
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229 | base = nic_base + offset, |
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230 | size = nic_size, |
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231 | channels = nb_nics ) |
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232 | |
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233 | cma = archi.addDevice( ptype = 'CMA', |
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234 | base = cma_base + offset, |
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235 | size = cma_size, |
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236 | channels = nb_cmas ) |
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237 | |
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238 | fbf = archi.addDevice( ptype = 'FBF', |
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239 | base = fbf_base + offset, |
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240 | size = fbf_size, |
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241 | arg0 = fbf_width, |
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242 | arg1 = fbf_width ) |
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243 | |
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244 | rom = archi.addDevice( ptype = 'ROM', |
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245 | base = rom_base + offset, |
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246 | size = rom_size ) |
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247 | |
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248 | pic = archi.addDevice( ptype ='PIC', |
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249 | base = pic_base + offset, |
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250 | size = pic_size, |
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251 | arg0 = 32 ) |
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252 | |
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253 | if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' |
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254 | elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' |
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255 | elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' |
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256 | elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' |
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257 | else : isr_ioc = 'ISR_DEFAULT' |
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258 | |
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259 | archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) |
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260 | archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) |
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261 | archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) |
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262 | archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) |
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263 | archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) |
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264 | archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) |
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265 | archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) |
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266 | archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) |
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267 | archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) |
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268 | archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) |
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269 | archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) |
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270 | archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) |
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271 | archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) |
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272 | archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) |
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273 | archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) |
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274 | archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) |
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275 | archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) |
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276 | |
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277 | # build cores |
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278 | for p in xrange ( nb_cores ): |
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279 | core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware identifier |
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280 | (x<<y_width) + y, # cluster identifier |
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281 | p ) # local index |
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282 | |
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283 | return archi |
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284 | |
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285 | ################################# platform test #################################### |
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286 | |
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287 | if __name__ == '__main__': |
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288 | |
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289 | archi = arch() |
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290 | |
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291 | print archi.xml() |
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292 | |
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293 | |
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294 | # Local Variables: |
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295 | # tab-width: 4; |
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296 | # c-basic-offset: 4; |
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297 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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298 | # indent-tabs-mode: nil; |
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299 | # End: |
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300 | # |
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301 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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302 | |
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