1 | /////////////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp (for tsar_generic_iob platform) |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : august 2013 / updated march 2015 |
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6 | // This program is released under the GNU public license |
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7 | /////////////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture with an external IO network |
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9 | // emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: |
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10 | // |
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11 | // - BROM : boot ROM |
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12 | // - FBUF : Frame Buffer |
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13 | // - MTTY : multi TTY (one channel) |
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14 | // - MNIC : Network controller (up to 2 channels) |
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15 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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16 | // - DISK : Block device controler (BDV / HBA / SDC) |
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17 | // - IOPI : HWI to SWI translator. |
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18 | // |
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19 | // This I/0 bus is connected to internal address space through two IOB bridges |
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20 | // located in cluster[0][0] and cluster[X_SIZE-1][Y_SIZE-1]. |
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21 | // |
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22 | // The internal physical address space is 40 bits, and the cluster index |
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23 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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24 | // Y is encoded on 4 bits, whatever the actual mesh size. |
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25 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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26 | // |
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27 | // It contains 3 networks: |
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28 | // |
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29 | // 1) the "INT" network supports Read/Write transactions |
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30 | // between processors and L2 caches or peripherals. |
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31 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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32 | // It supports also coherence transactions between L1 & L2 caches. |
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33 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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34 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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35 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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36 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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37 | // 4) the IOX network connects the two IO bridge components to the |
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38 | // 7 external peripheral controllers. |
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39 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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40 | // |
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41 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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42 | // external IOPIC component, that must be configured by the OS to route |
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43 | // these WTI IRQS to one or several internal XICU components. |
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44 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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45 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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46 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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47 | // - IOPIC HWI[8] connected to IRQ_DISK |
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48 | // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] |
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49 | // |
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50 | // Each cluster contains the following component: |
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51 | // - From 1 to 8 MIP32 processors |
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52 | // - One L2 cache controller |
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53 | // - One XICU component, |
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54 | // - One - optional - single channel DMA controler, |
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55 | // - One - optional - hardware coprocessor |
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56 | // The XICU component is mainly used to handle WTI IRQs, as at most |
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57 | // 2 HWI IRQs are connected to XICU in each cluster: |
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58 | // - IRQ_IN[0] : MMC |
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59 | // - IRQ_IN[1] : MWR |
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60 | // |
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61 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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62 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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63 | // connected to the three networks (INT, RAM, IOX). |
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64 | // |
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65 | // - It uses two dspin_local_crossbar per cluster to implement the |
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66 | // local interconnect correponding to the INT network. |
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67 | // - It uses three dspin_local_crossbar per cluster to implement the |
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68 | // local interconnect correponding to the coherence INT network. |
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69 | // - It uses two virtual_dspin_router per cluster to implement |
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70 | // the INT network (routing both the direct and coherence trafic). |
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71 | // - It uses two dspin_router per cluster to implement the RAM network. |
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72 | // - It uses the vci_cc_vcache_wrapper. |
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73 | // - It uses the vci_mem_cache. |
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74 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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75 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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76 | // |
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77 | // The TsarIobCluster component is defined in files |
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78 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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79 | // |
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80 | // The main hardware parameters must be defined in the hard_config.h file : |
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81 | // - X_WIDTH : number of bits for x cluster coordinate |
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82 | // - Y_WIDTH : number of bits for y cluster coordinate |
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83 | // - P_WIDTH : number of bits for local processor coordinate |
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84 | // - X_SIZE : number of clusters in a row |
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85 | // - Y_SIZE : number of clusters in a column |
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86 | // - NB_PROCS_MAX : number of processors per cluster (up to 8) |
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87 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) |
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88 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) |
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89 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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90 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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91 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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92 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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93 | // - XCU_NB_HWI : number of XCU HWIs (>= NB_PROCS_MAX + 1) |
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94 | // - XCU_NB_PTI : number of XCU PTIs (>= NB_PROCS_MAX) |
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95 | // - XCU_NB_WTI : number of XCU WTIs (>= 4*NB_PROCS_MAX) |
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96 | // - XCU_NB_OUT : number of XCU output IRQs (>= 4*NB_PROCS_MAX) |
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97 | // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) |
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98 | // |
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99 | // Some other hardware parameters must be defined in this top.cpp file: |
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100 | // - XRAM_LATENCY : external ram latency |
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101 | // - MEMC_WAYS : L2 cache number of ways |
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102 | // - MEMC_SETS : L2 cache number of sets |
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103 | // - L1_IWAYS |
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104 | // - L1_ISETS |
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105 | // - L1_DWAYS |
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106 | // - L1_DSETS |
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107 | // - DISK_IMAGE_NAME : file pathname for block device |
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108 | // |
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109 | // General policy for 40 bits physical address decoding: |
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110 | // All physical segments base addresses are multiple of 1 Mbytes |
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111 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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112 | // The (x_width + y_width) MSB bits (left aligned) define |
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113 | // the cluster index, and the LADR bits define the local index: |
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114 | // |X_ID|Y_ID| LADR | OFFSET | |
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115 | // | 4 | 4 | 8 | 24 | |
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116 | // |
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117 | // General policy for 14 bits SRCID decoding: |
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118 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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119 | // |X_ID|Y_ID| L_ID | |
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120 | // | 4 | 4 | 6 | |
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121 | ///////////////////////////////////////////////////////////////////////// |
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122 | |
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123 | #include <systemc> |
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124 | #include <sys/time.h> |
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125 | #include <iostream> |
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126 | #include <sstream> |
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127 | #include <cstdlib> |
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128 | #include <cstdarg> |
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129 | #include <stdint.h> |
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130 | |
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131 | #include "gdbserver.h" |
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132 | #include "mapping_table.h" |
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133 | |
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134 | |
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135 | |
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136 | #include "tsar_iob_cluster.h" |
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137 | #include "vci_chbuf_dma.h" |
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138 | #include "vci_multi_tty.h" |
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139 | #include "vci_multi_nic.h" |
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140 | #include "vci_simple_rom.h" |
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141 | #include "vci_multi_ahci.h" |
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142 | #include "vci_block_device_tsar.h" |
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143 | #include "vci_ahci_sdc.h" |
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144 | #include "sd_card.h" |
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145 | #include "vci_framebuffer.h" |
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146 | #include "vci_iox_network.h" |
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147 | #include "vci_iopic.h" |
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148 | |
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149 | #include "alloc_elems.h" |
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150 | |
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151 | |
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152 | ////////////////////////////////////////////////////////////////// |
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153 | // Coprocessor type (must be replicated in tsar_iob_cluster) |
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154 | ////////////////////////////////////////////////////////////////// |
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155 | |
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156 | #define MWR_COPROC_CPY 0 |
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157 | #define MWR_COPROC_DCT 1 |
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158 | #define MWR_COPROC_GCD 2 |
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159 | |
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160 | ////////////////////////////////////////////////////////////////// |
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161 | // For ALMOS |
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162 | ////////////////////////////////////////////////////////////////// |
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163 | |
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164 | #define USE_ALMOS 0 |
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165 | |
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166 | #define almos_bootloader_pathname "bootloader.bin" |
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167 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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168 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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169 | |
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170 | ////////////////////////////////////////////////////////////////// |
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171 | // Parallelisation |
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172 | ////////////////////////////////////////////////////////////////// |
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173 | |
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174 | #if USE_OPENMP |
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175 | #include <omp.h> |
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176 | #endif |
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177 | |
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178 | ////////////////////////////////////////////////////////////////// |
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179 | // DSPIN parameters |
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180 | ////////////////////////////////////////////////////////////////// |
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181 | |
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182 | #define dspin_int_cmd_width 39 |
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183 | #define dspin_int_rsp_width 32 |
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184 | |
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185 | #define dspin_ram_cmd_width 64 |
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186 | #define dspin_ram_rsp_width 64 |
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187 | |
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188 | ////////////////////////////////////////////////////////////////// |
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189 | // VCI fields width for the 3 VCI networks |
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190 | ////////////////////////////////////////////////////////////////// |
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191 | |
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192 | #define vci_cell_width_int 4 |
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193 | #define vci_cell_width_ext 8 |
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194 | |
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195 | #define vci_plen_width 8 |
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196 | #define vci_address_width 40 |
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197 | #define vci_rerror_width 1 |
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198 | #define vci_clen_width 1 |
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199 | #define vci_rflag_width 1 |
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200 | #define vci_srcid_width 14 |
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201 | #define vci_pktid_width 4 |
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202 | #define vci_trdid_width 4 |
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203 | #define vci_wrplen_width 1 |
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204 | |
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205 | //////////////////////////////////////////////////////////// |
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206 | // Main Hardware Parameters values |
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207 | //////////////////////i///////////////////////////////////// |
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208 | |
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209 | #include "hard_config.h" |
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210 | |
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211 | //////////////////////////////////////////////////////////// |
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212 | // Secondary Hardware Parameters values |
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213 | //////////////////////i///////////////////////////////////// |
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214 | |
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215 | #define XMAX X_SIZE |
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216 | #define YMAX Y_SIZE |
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217 | |
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218 | #define XRAM_LATENCY 0 |
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219 | |
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220 | #define MEMC_WAYS 16 |
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221 | #define MEMC_SETS 256 |
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222 | |
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223 | #define L1_IWAYS 4 |
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224 | #define L1_ISETS 64 |
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225 | |
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226 | #define L1_DWAYS 4 |
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227 | #define L1_DSETS 64 |
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228 | |
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229 | #define DISK_IMAGE_NAME "virt_hdd.dmg" |
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230 | |
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231 | #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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232 | |
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233 | #define NORTH 0 |
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234 | #define SOUTH 1 |
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235 | #define EAST 2 |
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236 | #define WEST 3 |
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237 | |
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238 | #define cluster(x,y) ((y) + ((x) << 4)) |
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239 | |
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240 | //////////////////////////////////////////////////////////// |
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241 | // DEBUG Parameters default values |
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242 | //////////////////////i///////////////////////////////////// |
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243 | |
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244 | #define MAX_FROZEN_CYCLES 1000000 |
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245 | |
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246 | ///////////////////////////////////////////////////////// |
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247 | // Physical segments definition |
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248 | ///////////////////////////////////////////////////////// |
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249 | |
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250 | // All physical segments base addresses and sizes are defined |
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251 | // in the hard_config.h file. For replicated segments, the |
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252 | // base address is incremented by a cluster offset: |
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253 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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254 | |
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255 | //////////////////////////////////////////////////////////////////////// |
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256 | // SRCID definition |
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257 | //////////////////////////////////////////////////////////////////////// |
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258 | // All initiators are in the same indexing space (14 bits). |
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259 | // The SRCID is structured in two fields: |
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260 | // - The 8 MSB bits define the cluster index (left aligned) |
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261 | // - The 6 LSB bits define the local index. |
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262 | // Two different initiators cannot have the same SRCID, but a given |
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263 | // initiator can have two alias SRCIDs: |
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264 | // - Internal initiators (procs, mwmr) are replicated in all clusters, |
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265 | // and each initiator has one single SRCID. |
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266 | // - External initiators (disk, cdma) are not replicated, but can be |
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267 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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268 | // They have the same local index, but two different cluster indexes. |
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269 | // |
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270 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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271 | // and external initiators, they must have different local indexes. |
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272 | // Consequence: For a local interconnect, the INI_ID port index |
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273 | // is NOT equal to the SRCID local index, and the local interconnect |
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274 | // must make a translation: SRCID => INI_ID |
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275 | //////////////////////////////////////////////////////////////////////// |
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276 | |
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277 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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278 | #define MWMR_LOCAL_SRCID 0x8 |
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279 | #define IOBX_LOCAL_SRCID 0x9 |
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280 | #define MEMC_LOCAL_SRCID 0xA |
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281 | #define CDMA_LOCAL_SRCID 0xB |
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282 | #define DISK_LOCAL_SRCID 0xC |
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283 | #define IOPI_LOCAL_SRCID 0xD |
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284 | |
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285 | /////////////////////////////////////////////////////////////////////// |
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286 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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287 | /////////////////////////////////////////////////////////////////////// |
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288 | |
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289 | #define INT_MEMC_TGT_ID 0 |
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290 | #define INT_XICU_TGT_ID 1 |
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291 | #define INT_MWMR_TGT_ID 2 |
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292 | #define INT_IOBX_TGT_ID 3 |
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293 | |
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294 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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295 | #define INT_MWMR_INI_ID (NB_PROCS_MAX) |
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296 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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297 | |
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298 | /////////////////////////////////////////////////////////////////////// |
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299 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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300 | /////////////////////////////////////////////////////////////////////// |
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301 | |
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302 | #define RAM_XRAM_TGT_ID 0 |
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303 | |
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304 | #define RAM_MEMC_INI_ID 0 |
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305 | #define RAM_IOBX_INI_ID 1 |
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306 | |
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307 | /////////////////////////////////////////////////////////////////////// |
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308 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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309 | /////////////////////////////////////////////////////////////////////// |
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310 | |
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311 | #define IOX_FBUF_TGT_ID 0 |
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312 | #define IOX_DISK_TGT_ID 1 |
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313 | #define IOX_MNIC_TGT_ID 2 |
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314 | #define IOX_CDMA_TGT_ID 3 |
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315 | #define IOX_BROM_TGT_ID 4 |
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316 | #define IOX_MTTY_TGT_ID 5 |
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317 | #define IOX_IOPI_TGT_ID 6 |
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318 | #define IOX_IOB0_TGT_ID 7 |
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319 | #define IOX_IOB1_TGT_ID 8 |
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320 | |
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321 | #define IOX_DISK_INI_ID 0 |
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322 | #define IOX_CDMA_INI_ID 1 |
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323 | #define IOX_IOPI_INI_ID 2 |
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324 | #define IOX_IOB0_INI_ID 3 |
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325 | #define IOX_IOB1_INI_ID 4 |
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326 | |
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327 | //////////////////////////////////////////////////////////////////////// |
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328 | int _main(int argc, char *argv[]) |
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329 | //////////////////////////////////////////////////////////////////////// |
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330 | { |
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331 | using namespace sc_core; |
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332 | using namespace soclib::caba; |
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333 | using namespace soclib::common; |
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334 | |
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335 | char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code |
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336 | size_t ncycles = 4000000000; // simulated cycles |
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337 | char disk_name[256] = DISK_IMAGE_NAME; // pathname: disk image |
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338 | ssize_t threads = 1; // simulator's threads number |
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339 | bool debug_ok = false; // trace activated |
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340 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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341 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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342 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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343 | bool debug_iob = false; // trace iob0 & iob1 when true |
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344 | uint32_t debug_from = 0; // trace start cycle |
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345 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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346 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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347 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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348 | size_t x_width = X_WIDTH; // # of bits for x |
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349 | size_t y_width = Y_WIDTH; // # of bits for y |
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350 | size_t p_width = P_WIDTH; // # of bits for lpid |
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351 | |
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352 | #if USE_OPENMP |
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353 | size_t simul_period = 1000000; |
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354 | #else |
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355 | size_t simul_period = 1; |
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356 | #endif |
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357 | |
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358 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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359 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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360 | |
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361 | assert( P_WIDTH <= 4 and |
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362 | "ERROR: we must have P_WIDTH <= 4"); |
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363 | |
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364 | ////////////// command line arguments ////////////////////// |
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365 | if (argc > 1) |
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366 | { |
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367 | for (int n = 1; n < argc; n = n + 2) |
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368 | { |
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369 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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370 | { |
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371 | ncycles = atoi(argv[n+1]); |
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372 | } |
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373 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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374 | { |
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375 | debug_ok = true; |
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376 | debug_from = atoi(argv[n+1]); |
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377 | } |
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378 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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379 | { |
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380 | strcpy(disk_name, argv[n+1]); |
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381 | } |
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382 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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383 | { |
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384 | debug_memc_id = atoi(argv[n+1]); |
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385 | size_t x = debug_memc_id >> 4; |
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386 | size_t y = debug_memc_id & 0xF; |
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387 | if( (x>=XMAX) || (y>=YMAX) ) |
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388 | { |
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389 | std::cout << "MEMCID parameter doesn't fit XMAX/YMAX" << std::endl; |
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390 | std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; |
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391 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
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392 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
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393 | exit(0); |
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394 | } |
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395 | } |
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396 | else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1<argc) ) |
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397 | { |
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398 | debug_xram_id = atoi(argv[n+1]); |
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399 | size_t x = debug_xram_id >> 4; |
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400 | size_t y = debug_xram_id & 0xF; |
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401 | if( (x>=XMAX) || (y>=YMAX) ) |
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402 | { |
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403 | std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; |
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404 | exit(0); |
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405 | } |
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406 | } |
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407 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
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408 | { |
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409 | debug_iob = atoi(argv[n+1]); |
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410 | } |
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411 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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412 | { |
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413 | debug_proc_id = atoi(argv[n+1]); |
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414 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
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415 | size_t x = cluster_xy >> 4; |
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416 | size_t y = cluster_xy & 0xF; |
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417 | if( (x>=XMAX) || (y>=YMAX) ) |
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418 | { |
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419 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
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420 | std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; |
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421 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
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422 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
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423 | exit(0); |
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424 | } |
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425 | } |
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426 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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427 | { |
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428 | threads = atoi(argv[n+1]); |
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429 | threads = (threads < 1) ? 1 : threads; |
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430 | } |
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431 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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432 | { |
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433 | frozen_cycles = atoi(argv[n+1]); |
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434 | } |
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435 | else |
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436 | { |
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437 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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438 | std::cout << " The order is not important." << std::endl; |
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439 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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440 | std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; |
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441 | std::cout << " - DEBUG debug_start_cycle" << std::endl; |
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442 | std::cout << " - THREADS simulator's threads number" << std::endl; |
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443 | std::cout << " - FROZEN max_number_of_lines" << std::endl; |
---|
444 | std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; |
---|
445 | std::cout << " - PROCID index_proc_to_be_traced" << std::endl; |
---|
446 | std::cout << " - IOB non_zero_value" << std::endl; |
---|
447 | exit(0); |
---|
448 | } |
---|
449 | } |
---|
450 | } |
---|
451 | |
---|
452 | // checking hardware parameters |
---|
453 | assert( (XMAX <= 16) and |
---|
454 | "Error in tsar_generic_iob : XMAX parameter cannot be larger than 16" ); |
---|
455 | |
---|
456 | assert( (YMAX <= 16) and |
---|
457 | "Error in tsar_generic_iob : YMAX parameter cannot be larger than 16" ); |
---|
458 | |
---|
459 | assert( (NB_PROCS_MAX <= 8) and |
---|
460 | "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
461 | |
---|
462 | assert( (XCU_NB_HWI > NB_PROCS_MAX) and |
---|
463 | "Error in tsar_generic_iob : XCU_NB_HWI must be larger than NB_PROCS_MAX" ); |
---|
464 | |
---|
465 | assert( (XCU_NB_PTI >= NB_PROCS_MAX) and |
---|
466 | "Error in tsar_generic_iob : XCU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); |
---|
467 | |
---|
468 | assert( (XCU_NB_WTI >= 4*NB_PROCS_MAX) and |
---|
469 | "Error in tsar_generic_iob : XCU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
470 | |
---|
471 | assert( (XCU_NB_OUT >= 4*NB_PROCS_MAX) and |
---|
472 | "Error in tsar_generic_iob : XCU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
473 | |
---|
474 | assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and |
---|
475 | "Error in tsar_generic_iob : NB_TTY_CHANNELS parameter cannot be larger than 16" ); |
---|
476 | |
---|
477 | assert( (NB_NIC_CHANNELS <= 2) and |
---|
478 | "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 2" ); |
---|
479 | |
---|
480 | assert( (NB_CMA_CHANNELS <= 4) and |
---|
481 | "Error in tsar_generic_iob : NB_CMA_CHANNELS parameter cannot be larger than 4" ); |
---|
482 | |
---|
483 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
---|
484 | "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); |
---|
485 | |
---|
486 | assert( ((USE_MWR_CPY + USE_MWR_GCD + USE_MWR_DCT) == 1) and |
---|
487 | "Error in tsar_generic_iob : No MWR coprocessor found in hard_config.h"); |
---|
488 | |
---|
489 | assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and |
---|
490 | "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); |
---|
491 | |
---|
492 | std::cout << std::endl << std::dec |
---|
493 | << " - XMAX = " << XMAX << std::endl |
---|
494 | << " - YMAX = " << YMAX << std::endl |
---|
495 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
496 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
497 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
498 | << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl |
---|
499 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
500 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
501 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
502 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
503 | << " - NCYCLES = " << ncycles << std::endl |
---|
504 | << " - SOFT_FILENAME = " << soft_name << std::endl |
---|
505 | << " - DISK_IMAGENAME = " << disk_name << std::endl |
---|
506 | << " - OPENMP THREADS = " << threads << std::endl |
---|
507 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
508 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
509 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl |
---|
510 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
511 | |
---|
512 | std::cout << std::endl; |
---|
513 | |
---|
514 | #if USE_OPENMP |
---|
515 | omp_set_dynamic(false); |
---|
516 | omp_set_num_threads(threads); |
---|
517 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
518 | #endif |
---|
519 | |
---|
520 | // Define VciParams objects |
---|
521 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
522 | vci_plen_width, |
---|
523 | vci_address_width, |
---|
524 | vci_rerror_width, |
---|
525 | vci_clen_width, |
---|
526 | vci_rflag_width, |
---|
527 | vci_srcid_width, |
---|
528 | vci_pktid_width, |
---|
529 | vci_trdid_width, |
---|
530 | vci_wrplen_width> vci_param_int; |
---|
531 | |
---|
532 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
533 | vci_plen_width, |
---|
534 | vci_address_width, |
---|
535 | vci_rerror_width, |
---|
536 | vci_clen_width, |
---|
537 | vci_rflag_width, |
---|
538 | vci_srcid_width, |
---|
539 | vci_pktid_width, |
---|
540 | vci_trdid_width, |
---|
541 | vci_wrplen_width> vci_param_ext; |
---|
542 | |
---|
543 | ///////////////////////////////////////////////////////////////////// |
---|
544 | // INT network mapping table |
---|
545 | // - two levels address decoding for commands |
---|
546 | // - two levels srcid decoding for responses |
---|
547 | // - NB_PROCS_MAX + 2 (MWMR, IOBX) local initiators per cluster |
---|
548 | // - 4 local targets (MEMC, XICU, MWMR, IOBX) per cluster |
---|
549 | ///////////////////////////////////////////////////////////////////// |
---|
550 | MappingTable maptab_int( vci_address_width, |
---|
551 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
552 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
553 | 0x00FF000000); |
---|
554 | |
---|
555 | for (size_t x = 0; x < XMAX; x++) |
---|
556 | { |
---|
557 | for (size_t y = 0; y < YMAX; y++) |
---|
558 | { |
---|
559 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
560 | << (vci_address_width-x_width-y_width); |
---|
561 | bool config = true; |
---|
562 | bool cacheable = true; |
---|
563 | |
---|
564 | // the four following segments are defined in all clusters |
---|
565 | |
---|
566 | std::ostringstream smemc_conf; |
---|
567 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
568 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
569 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
570 | |
---|
571 | std::ostringstream smemc_xram; |
---|
572 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
573 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
574 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
---|
575 | |
---|
576 | std::ostringstream sxicu; |
---|
577 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
578 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
579 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
---|
580 | |
---|
581 | std::ostringstream smwmr; |
---|
582 | smwmr << "int_seg_mwmr_" << x << "_" << y; |
---|
583 | maptab_int.add(Segment(smwmr.str(), SEG_MWR_BASE+offset, SEG_MWR_SIZE, |
---|
584 | IntTab(cluster(x,y), INT_MWMR_TGT_ID), not cacheable)); |
---|
585 | |
---|
586 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
587 | |
---|
588 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
589 | { |
---|
590 | std::ostringstream siobx; |
---|
591 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
592 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
593 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
594 | |
---|
595 | std::ostringstream stty; |
---|
596 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
597 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
598 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
599 | |
---|
600 | std::ostringstream sfbf; |
---|
601 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
602 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
603 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
604 | |
---|
605 | std::ostringstream sdsk; |
---|
606 | sdsk << "int_seg_disk_" << x << "_" << y; |
---|
607 | maptab_int.add(Segment(sdsk.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
608 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
609 | |
---|
610 | std::ostringstream snic; |
---|
611 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
612 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
613 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
614 | |
---|
615 | std::ostringstream srom; |
---|
616 | srom << "int_seg_brom_" << x << "_" << y; |
---|
617 | maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
618 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); |
---|
619 | |
---|
620 | std::ostringstream sdma; |
---|
621 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
622 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
623 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
624 | |
---|
625 | std::ostringstream spic; |
---|
626 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
627 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
628 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
629 | } |
---|
630 | |
---|
631 | // This define the mapping between the SRCIDs |
---|
632 | // and the port index on the local interconnect. |
---|
633 | |
---|
634 | maptab_int.srcid_map( IntTab( cluster(x,y), MWMR_LOCAL_SRCID ), |
---|
635 | IntTab( cluster(x,y), INT_MWMR_INI_ID ) ); |
---|
636 | |
---|
637 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
---|
638 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
639 | |
---|
640 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
---|
641 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
642 | |
---|
643 | for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) |
---|
644 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
---|
645 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
---|
646 | } |
---|
647 | } |
---|
648 | std::cout << "INT network " << maptab_int << std::endl; |
---|
649 | |
---|
650 | ///////////////////////////////////////////////////////////////////////// |
---|
651 | // RAM network mapping table |
---|
652 | // - two levels address decoding for commands |
---|
653 | // - two levels srcid decoding for responses |
---|
654 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
655 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
656 | // - 1 local target (XRAM) per cluster |
---|
657 | //////////////////////////////////////////////////////////////////////// |
---|
658 | MappingTable maptab_ram( vci_address_width, |
---|
659 | IntTab(x_width+y_width, 0), |
---|
660 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
661 | 0x00FF000000); |
---|
662 | |
---|
663 | for (size_t x = 0; x < XMAX; x++) |
---|
664 | { |
---|
665 | for (size_t y = 0; y < YMAX ; y++) |
---|
666 | { |
---|
667 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
668 | << (vci_address_width-x_width-y_width); |
---|
669 | |
---|
670 | std::ostringstream sxram; |
---|
671 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
672 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
673 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
674 | } |
---|
675 | } |
---|
676 | |
---|
677 | // This define the mapping between the initiators SRCID |
---|
678 | // and the port index on the RAM local interconnect. |
---|
679 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
680 | |
---|
681 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
682 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
683 | |
---|
684 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
685 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
686 | |
---|
687 | maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), |
---|
688 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
689 | |
---|
690 | maptab_ram.srcid_map( IntTab( cluster_iob1, DISK_LOCAL_SRCID ), |
---|
691 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
692 | |
---|
693 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
694 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
695 | |
---|
696 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
697 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
698 | |
---|
699 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
700 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
701 | |
---|
702 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
703 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
704 | |
---|
705 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
706 | |
---|
707 | /////////////////////////////////////////////////////////////////////// |
---|
708 | // IOX network mapping table |
---|
709 | // - two levels address decoding for commands (9, 7) bits |
---|
710 | // - two levels srcid decoding for responses |
---|
711 | // - 5 initiators (IOB0, IOB1, DISK, CDMA, IOPI) |
---|
712 | // - 9 targets (IOB0, IOB1, DISK, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
713 | // |
---|
714 | // Address bit 32 is used to determine if a command must be routed to |
---|
715 | // IOB0 or IOB1. |
---|
716 | /////////////////////////////////////////////////////////////////////// |
---|
717 | MappingTable maptab_iox( |
---|
718 | vci_address_width, |
---|
719 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
---|
720 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
---|
721 | 0x00FF000000); |
---|
722 | |
---|
723 | // External peripherals segments |
---|
724 | // When there is more than one cluster, external peripherals can be accessed |
---|
725 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
726 | |
---|
727 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
728 | << (vci_address_width - x_width - y_width); |
---|
729 | |
---|
730 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
731 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
732 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
733 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
734 | maptab_iox.add(Segment("iox_seg_disk_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
735 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
736 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
737 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
738 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
739 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
740 | maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, |
---|
741 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
742 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
743 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
744 | |
---|
745 | if ( cluster_iob0 != cluster_iob1 ) |
---|
746 | { |
---|
747 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
748 | << (vci_address_width - x_width - y_width); |
---|
749 | |
---|
750 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
751 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
752 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
753 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
754 | maptab_iox.add(Segment("iox_seg_disk_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
755 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
756 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
757 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
758 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
759 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
760 | maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, |
---|
761 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
762 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
763 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
764 | } |
---|
765 | |
---|
766 | // If there is more than one cluster, external peripherals |
---|
767 | // can access RAM through two segments (IOB0 / IOB1). |
---|
768 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
769 | // and the choice depends on address bit A[32]. |
---|
770 | for (size_t x = 0; x < XMAX; x++) |
---|
771 | { |
---|
772 | for (size_t y = 0; y < YMAX ; y++) |
---|
773 | { |
---|
774 | const bool wti = true; |
---|
775 | const bool cacheable = true; |
---|
776 | |
---|
777 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
778 | << (vci_address_width-x_width-y_width); |
---|
779 | |
---|
780 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
781 | |
---|
782 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
783 | { |
---|
784 | std::ostringstream sxcu0; |
---|
785 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
786 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
787 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
788 | |
---|
789 | std::ostringstream siob0; |
---|
790 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
791 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
792 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
793 | } |
---|
794 | else // USE IOB1 |
---|
795 | { |
---|
796 | std::ostringstream sxcu1; |
---|
797 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
798 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
799 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
800 | |
---|
801 | std::ostringstream siob1; |
---|
802 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
803 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
804 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
805 | } |
---|
806 | } |
---|
807 | } |
---|
808 | |
---|
809 | // This define the mapping between the external initiators (SRCID) |
---|
810 | // and the port index on the IOX local interconnect. |
---|
811 | |
---|
812 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
813 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
814 | maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , |
---|
815 | IntTab( 0, IOX_DISK_INI_ID ) ); |
---|
816 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
817 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
818 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
819 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
820 | |
---|
821 | if ( cluster_iob0 != cluster_iob1 ) |
---|
822 | { |
---|
823 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
824 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
825 | } |
---|
826 | |
---|
827 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
828 | |
---|
829 | //////////////////// |
---|
830 | // Signals |
---|
831 | /////////////////// |
---|
832 | |
---|
833 | sc_clock signal_clk("clk"); |
---|
834 | sc_signal<bool> signal_resetn("resetn"); |
---|
835 | |
---|
836 | sc_signal<bool> signal_irq_false; |
---|
837 | sc_signal<bool> signal_irq_disk; |
---|
838 | sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; |
---|
839 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
840 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
841 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
842 | |
---|
843 | // VCI signals for IOX network |
---|
844 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
845 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
846 | VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); |
---|
847 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
848 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
849 | |
---|
850 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
851 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
852 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
853 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
854 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
855 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
---|
856 | VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); |
---|
857 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
858 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
---|
859 | |
---|
860 | // Horizontal inter-clusters INT_CMD DSPIN |
---|
861 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_inc = |
---|
862 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX); |
---|
863 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_dec = |
---|
864 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX); |
---|
865 | |
---|
866 | // Horizontal inter-clusters INT_RSP DSPIN |
---|
867 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_inc = |
---|
868 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX); |
---|
869 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_dec = |
---|
870 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX); |
---|
871 | |
---|
872 | // Horizontal inter-clusters INT_M2P DSPIN |
---|
873 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_inc = |
---|
874 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_inc", XMAX-1, YMAX); |
---|
875 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_dec = |
---|
876 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_dec", XMAX-1, YMAX); |
---|
877 | |
---|
878 | // Horizontal inter-clusters INT_P2M DSPIN |
---|
879 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_inc = |
---|
880 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_inc", XMAX-1, YMAX); |
---|
881 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_dec = |
---|
882 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_dec", XMAX-1, YMAX); |
---|
883 | |
---|
884 | // Horizontal inter-clusters INT_CLA DSPIN |
---|
885 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_inc = |
---|
886 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_inc", XMAX-1, YMAX); |
---|
887 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_dec = |
---|
888 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_dec", XMAX-1, YMAX); |
---|
889 | |
---|
890 | |
---|
891 | // Vertical inter-clusters INT_CMD DSPIN |
---|
892 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_inc = |
---|
893 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1); |
---|
894 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_dec = |
---|
895 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1); |
---|
896 | |
---|
897 | // Vertical inter-clusters INT_RSP DSPIN |
---|
898 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_inc = |
---|
899 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1); |
---|
900 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_dec = |
---|
901 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1); |
---|
902 | |
---|
903 | // Vertical inter-clusters INT_M2P DSPIN |
---|
904 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_inc = |
---|
905 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_inc", XMAX, YMAX-1); |
---|
906 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_dec = |
---|
907 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_dec", XMAX, YMAX-1); |
---|
908 | |
---|
909 | // Vertical inter-clusters INT_P2M DSPIN |
---|
910 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_inc = |
---|
911 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_inc", XMAX, YMAX-1); |
---|
912 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_dec = |
---|
913 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_dec", XMAX, YMAX-1); |
---|
914 | |
---|
915 | // Vertical inter-clusters INT_CLA DSPIN |
---|
916 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_inc = |
---|
917 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_inc", XMAX, YMAX-1); |
---|
918 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_dec = |
---|
919 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_dec", XMAX, YMAX-1); |
---|
920 | |
---|
921 | |
---|
922 | // Mesh boundaries INT_CMD DSPIN |
---|
923 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_in = |
---|
924 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4); |
---|
925 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_out = |
---|
926 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4); |
---|
927 | |
---|
928 | // Mesh boundaries INT_RSP DSPIN |
---|
929 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_in = |
---|
930 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4); |
---|
931 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_out = |
---|
932 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4); |
---|
933 | |
---|
934 | // Mesh boundaries INT_M2P DSPIN |
---|
935 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_in = |
---|
936 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2p_in", XMAX, YMAX, 4); |
---|
937 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_out = |
---|
938 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2P_out", XMAX, YMAX, 4); |
---|
939 | |
---|
940 | // Mesh boundaries INT_P2M DSPIN |
---|
941 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_in = |
---|
942 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_in", XMAX, YMAX, 4); |
---|
943 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_out = |
---|
944 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_out", XMAX, YMAX, 4); |
---|
945 | |
---|
946 | // Mesh boundaries INT_CLA DSPIN |
---|
947 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_in = |
---|
948 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_in", XMAX, YMAX, 4); |
---|
949 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_out = |
---|
950 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_out", XMAX, YMAX, 4); |
---|
951 | |
---|
952 | |
---|
953 | // Horizontal inter-clusters RAM_CMD DSPIN |
---|
954 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
955 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
956 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
957 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
958 | |
---|
959 | // Horizontal inter-clusters RAM_RSP DSPIN |
---|
960 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
961 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
962 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
963 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
964 | |
---|
965 | // Vertical inter-clusters RAM_CMD DSPIN |
---|
966 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
967 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
968 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
969 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
970 | |
---|
971 | // Vertical inter-clusters RAM_RSP DSPIN |
---|
972 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
973 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
974 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
975 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
976 | |
---|
977 | // Mesh boundaries RAM_CMD DSPIN |
---|
978 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
979 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
980 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
981 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
982 | |
---|
983 | // Mesh boundaries RAM_RSP DSPIN |
---|
984 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
985 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
986 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
987 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
988 | |
---|
989 | // SD card signals |
---|
990 | sc_signal<bool> signal_sdc_clk; |
---|
991 | sc_signal<bool> signal_sdc_cmd_enable_to_card; |
---|
992 | sc_signal<bool> signal_sdc_cmd_value_to_card; |
---|
993 | sc_signal<bool> signal_sdc_dat_enable_to_card; |
---|
994 | sc_signal<bool> signal_sdc_dat_value_to_card[4]; |
---|
995 | sc_signal<bool> signal_sdc_cmd_enable_from_card; |
---|
996 | sc_signal<bool> signal_sdc_cmd_value_from_card; |
---|
997 | sc_signal<bool> signal_sdc_dat_enable_from_card; |
---|
998 | sc_signal<bool> signal_sdc_dat_value_from_card[4]; |
---|
999 | |
---|
1000 | //////////////////////////// |
---|
1001 | // Loader |
---|
1002 | //////////////////////////// |
---|
1003 | |
---|
1004 | #if USE_ALMOS |
---|
1005 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
1006 | almos_archinfo_pathname, |
---|
1007 | almos_kernel_pathname); |
---|
1008 | #else |
---|
1009 | soclib::common::Loader loader(soft_name); |
---|
1010 | #endif |
---|
1011 | |
---|
1012 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
1013 | proc_iss::set_loader(loader); |
---|
1014 | |
---|
1015 | //////////////////////////////////////// |
---|
1016 | // Instanciated Hardware Components |
---|
1017 | //////////////////////////////////////// |
---|
1018 | |
---|
1019 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
1020 | |
---|
1021 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
1022 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; |
---|
1023 | |
---|
1024 | // IOX network |
---|
1025 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
1026 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
1027 | maptab_iox, |
---|
1028 | nb_iox_targets, |
---|
1029 | nb_iox_initiators ); |
---|
1030 | // boot ROM |
---|
1031 | VciSimpleRom<vci_param_ext>* brom; |
---|
1032 | brom = new VciSimpleRom<vci_param_ext>( "brom", |
---|
1033 | IntTab(0, IOX_BROM_TGT_ID), |
---|
1034 | maptab_iox, |
---|
1035 | loader ); |
---|
1036 | // Network Controller |
---|
1037 | VciMultiNic<vci_param_ext>* mnic; |
---|
1038 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
1039 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
1040 | maptab_iox, |
---|
1041 | NB_NIC_CHANNELS, |
---|
1042 | 0, // mac_4 address |
---|
1043 | 0, // mac_2 address |
---|
1044 | 1, // NIC_MODE_SYNTHESIS |
---|
1045 | 12); // INTER_FRAME_GAP |
---|
1046 | |
---|
1047 | // Frame Buffer |
---|
1048 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
1049 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
1050 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
1051 | maptab_iox, |
---|
1052 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
1053 | |
---|
1054 | // Disk |
---|
1055 | std::vector<std::string> filenames; |
---|
1056 | filenames.push_back(disk_name); // one single disk |
---|
1057 | |
---|
1058 | #if ( USE_IOC_HBA ) |
---|
1059 | |
---|
1060 | VciMultiAhci<vci_param_ext>* disk; |
---|
1061 | disk = new VciMultiAhci<vci_param_ext>( "disk", |
---|
1062 | maptab_iox, |
---|
1063 | IntTab(0, DISK_LOCAL_SRCID), |
---|
1064 | IntTab(0, IOX_DISK_TGT_ID), |
---|
1065 | filenames, |
---|
1066 | 512, // block size |
---|
1067 | 64, // burst size (bytes) |
---|
1068 | 0 ); // disk latency |
---|
1069 | #elif ( USE_IOC_BDV ) |
---|
1070 | |
---|
1071 | VciBlockDeviceTsar<vci_param_ext>* disk; |
---|
1072 | disk = new VciBlockDeviceTsar<vci_param_ext>( "disk", |
---|
1073 | maptab_iox, |
---|
1074 | IntTab(0, DISK_LOCAL_SRCID), |
---|
1075 | IntTab(0, IOX_DISK_TGT_ID), |
---|
1076 | disk_name, |
---|
1077 | 512, // block size |
---|
1078 | 64, // burst size (bytes) |
---|
1079 | 0 ); // disk latency |
---|
1080 | #elif ( USE_IOC_SDC ) |
---|
1081 | |
---|
1082 | VciAhciSdc<vci_param_ext>* disk; |
---|
1083 | disk = new VciAhciSdc<vci_param_ext>( "disk", |
---|
1084 | maptab_iox, |
---|
1085 | IntTab(0, DISK_LOCAL_SRCID), |
---|
1086 | IntTab(0, IOX_DISK_TGT_ID), |
---|
1087 | 64 ); // burst size (bytes) |
---|
1088 | SdCard* card; |
---|
1089 | card = new SdCard( "card", |
---|
1090 | disk_name, |
---|
1091 | 10, // RX one block latency |
---|
1092 | 10 ); // TX one block latency |
---|
1093 | #endif |
---|
1094 | |
---|
1095 | // Chained Buffer DMA controller |
---|
1096 | VciChbufDma<vci_param_ext>* cdma; |
---|
1097 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
1098 | maptab_iox, |
---|
1099 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
1100 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
1101 | 64, // burst size (bytes) |
---|
1102 | NB_CMA_CHANNELS, |
---|
1103 | 4 ); // number of pipelined bursts |
---|
1104 | |
---|
1105 | // Multi-TTY controller |
---|
1106 | std::vector<std::string> vect_names; |
---|
1107 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
1108 | { |
---|
1109 | std::ostringstream term_name; |
---|
1110 | term_name << "term" << tid; |
---|
1111 | |
---|
1112 | vect_names.push_back(term_name.str().c_str()); |
---|
1113 | } |
---|
1114 | VciMultiTty<vci_param_ext>* mtty; |
---|
1115 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
1116 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
1117 | maptab_iox, |
---|
1118 | vect_names); |
---|
1119 | |
---|
1120 | // IOPIC |
---|
1121 | VciIopic<vci_param_ext>* iopi; |
---|
1122 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
1123 | maptab_iox, |
---|
1124 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
1125 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
1126 | 32 ); // number of input HWI |
---|
1127 | // Clusters |
---|
1128 | TsarIobCluster<vci_param_int, |
---|
1129 | vci_param_ext, |
---|
1130 | dspin_int_cmd_width, |
---|
1131 | dspin_int_rsp_width, |
---|
1132 | dspin_ram_cmd_width, |
---|
1133 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
1134 | |
---|
1135 | unsigned int coproc_type; |
---|
1136 | if ( USE_MWR_CPY ) coproc_type = MWR_COPROC_CPY; |
---|
1137 | if ( USE_MWR_DCT ) coproc_type = MWR_COPROC_DCT; |
---|
1138 | if ( USE_MWR_GCD ) coproc_type = MWR_COPROC_GCD; |
---|
1139 | |
---|
1140 | #if USE_OPENMP |
---|
1141 | #pragma omp parallel |
---|
1142 | { |
---|
1143 | #pragma omp for |
---|
1144 | #endif |
---|
1145 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
1146 | { |
---|
1147 | size_t x = i / YMAX; |
---|
1148 | size_t y = i % YMAX; |
---|
1149 | |
---|
1150 | #if USE_OPENMP |
---|
1151 | #pragma omp critical |
---|
1152 | { |
---|
1153 | #endif |
---|
1154 | std::cout << std::endl; |
---|
1155 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
1156 | std::cout << std::endl; |
---|
1157 | |
---|
1158 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
---|
1159 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
---|
1160 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
1161 | |
---|
1162 | const int iox_iob_ini_id = is_iob0 ? |
---|
1163 | IOX_IOB0_INI_ID : |
---|
1164 | IOX_IOB1_INI_ID ; |
---|
1165 | const int iox_iob_tgt_id = is_iob0 ? |
---|
1166 | IOX_IOB0_TGT_ID : |
---|
1167 | IOX_IOB1_TGT_ID ; |
---|
1168 | |
---|
1169 | |
---|
1170 | std::ostringstream sc; |
---|
1171 | sc << "cluster_" << x << "_" << y; |
---|
1172 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
1173 | vci_param_ext, |
---|
1174 | dspin_int_cmd_width, |
---|
1175 | dspin_int_rsp_width, |
---|
1176 | dspin_ram_cmd_width, |
---|
1177 | dspin_ram_rsp_width> |
---|
1178 | ( |
---|
1179 | sc.str().c_str(), |
---|
1180 | NB_PROCS_MAX, |
---|
1181 | x, |
---|
1182 | y, |
---|
1183 | XMAX, |
---|
1184 | YMAX, |
---|
1185 | |
---|
1186 | maptab_int, |
---|
1187 | maptab_ram, |
---|
1188 | maptab_iox, |
---|
1189 | |
---|
1190 | x_width, |
---|
1191 | y_width, |
---|
1192 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
1193 | p_width, |
---|
1194 | |
---|
1195 | INT_MEMC_TGT_ID, |
---|
1196 | INT_XICU_TGT_ID, |
---|
1197 | INT_MWMR_TGT_ID, |
---|
1198 | INT_IOBX_TGT_ID, |
---|
1199 | |
---|
1200 | INT_PROC_INI_ID, |
---|
1201 | INT_MWMR_INI_ID, |
---|
1202 | INT_IOBX_INI_ID, |
---|
1203 | |
---|
1204 | RAM_XRAM_TGT_ID, |
---|
1205 | |
---|
1206 | RAM_MEMC_INI_ID, |
---|
1207 | RAM_IOBX_INI_ID, |
---|
1208 | |
---|
1209 | is_io_cluster, |
---|
1210 | iox_iob_tgt_id, |
---|
1211 | iox_iob_ini_id, |
---|
1212 | |
---|
1213 | MEMC_WAYS, |
---|
1214 | MEMC_SETS, |
---|
1215 | L1_IWAYS, |
---|
1216 | L1_ISETS, |
---|
1217 | L1_DWAYS, |
---|
1218 | L1_DSETS, |
---|
1219 | XRAM_LATENCY, |
---|
1220 | XCU_NB_HWI, |
---|
1221 | XCU_NB_PTI, |
---|
1222 | XCU_NB_WTI, |
---|
1223 | XCU_NB_OUT, |
---|
1224 | |
---|
1225 | coproc_type, |
---|
1226 | |
---|
1227 | loader, |
---|
1228 | |
---|
1229 | frozen_cycles, |
---|
1230 | debug_from, |
---|
1231 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
1232 | debug_ok and (cluster(x,y) == debug_proc_id), |
---|
1233 | debug_ok and debug_iob |
---|
1234 | ); |
---|
1235 | |
---|
1236 | #if USE_OPENMP |
---|
1237 | } // end critical |
---|
1238 | #endif |
---|
1239 | } // end for |
---|
1240 | #if USE_OPENMP |
---|
1241 | } |
---|
1242 | #endif |
---|
1243 | |
---|
1244 | std::cout << std::endl; |
---|
1245 | |
---|
1246 | /////////////////////////////////////////////////////////////////////////////// |
---|
1247 | // Net-list |
---|
1248 | /////////////////////////////////////////////////////////////////////////////// |
---|
1249 | |
---|
1250 | // IOX network connexion |
---|
1251 | iox_network->p_clk (signal_clk); |
---|
1252 | iox_network->p_resetn (signal_resetn); |
---|
1253 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
1254 | iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); |
---|
1255 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
1256 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
1257 | |
---|
1258 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
1259 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
1260 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
1261 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
1262 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
---|
1263 | iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); |
---|
1264 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
1265 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
1266 | |
---|
1267 | if (cluster_iob0 != cluster_iob1) |
---|
1268 | { |
---|
1269 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
1270 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
1271 | } |
---|
1272 | |
---|
1273 | // DISK connexion |
---|
1274 | |
---|
1275 | #if ( USE_IOC_HBA ) |
---|
1276 | |
---|
1277 | disk->p_clk (signal_clk); |
---|
1278 | disk->p_resetn (signal_resetn); |
---|
1279 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
1280 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
1281 | disk->p_channel_irq[0] (signal_irq_disk); |
---|
1282 | |
---|
1283 | #elif ( USE_IOC_BDV ) |
---|
1284 | |
---|
1285 | disk->p_clk (signal_clk); |
---|
1286 | disk->p_resetn (signal_resetn); |
---|
1287 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
1288 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
1289 | disk->p_irq (signal_irq_disk); |
---|
1290 | |
---|
1291 | #elif ( USE_IOC_SDC ) |
---|
1292 | |
---|
1293 | disk->p_clk (signal_clk); |
---|
1294 | disk->p_resetn (signal_resetn); |
---|
1295 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
1296 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
1297 | disk->p_irq (signal_irq_disk); |
---|
1298 | |
---|
1299 | disk->p_sdc_clk (signal_sdc_clk); |
---|
1300 | disk->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_to_card); |
---|
1301 | disk->p_sdc_cmd_value_out (signal_sdc_cmd_value_to_card); |
---|
1302 | disk->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_from_card); |
---|
1303 | disk->p_sdc_cmd_value_in (signal_sdc_cmd_value_from_card); |
---|
1304 | disk->p_sdc_dat_enable_out (signal_sdc_dat_enable_to_card); |
---|
1305 | disk->p_sdc_dat_value_out[0] (signal_sdc_dat_value_to_card[0]); |
---|
1306 | disk->p_sdc_dat_value_out[1] (signal_sdc_dat_value_to_card[1]); |
---|
1307 | disk->p_sdc_dat_value_out[2] (signal_sdc_dat_value_to_card[2]); |
---|
1308 | disk->p_sdc_dat_value_out[3] (signal_sdc_dat_value_to_card[3]); |
---|
1309 | disk->p_sdc_dat_enable_in (signal_sdc_dat_enable_from_card); |
---|
1310 | disk->p_sdc_dat_value_in[0] (signal_sdc_dat_value_from_card[0]); |
---|
1311 | disk->p_sdc_dat_value_in[1] (signal_sdc_dat_value_from_card[1]); |
---|
1312 | disk->p_sdc_dat_value_in[2] (signal_sdc_dat_value_from_card[2]); |
---|
1313 | disk->p_sdc_dat_value_in[3] (signal_sdc_dat_value_from_card[3]); |
---|
1314 | |
---|
1315 | card->p_clk (signal_clk); |
---|
1316 | card->p_resetn (signal_resetn); |
---|
1317 | |
---|
1318 | card->p_sdc_clk (signal_sdc_clk); |
---|
1319 | card->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_from_card); |
---|
1320 | card->p_sdc_cmd_value_out (signal_sdc_cmd_value_from_card); |
---|
1321 | card->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_to_card); |
---|
1322 | card->p_sdc_cmd_value_in (signal_sdc_cmd_value_to_card); |
---|
1323 | card->p_sdc_dat_enable_out (signal_sdc_dat_enable_from_card); |
---|
1324 | card->p_sdc_dat_value_out[0] (signal_sdc_dat_value_from_card[0]); |
---|
1325 | card->p_sdc_dat_value_out[1] (signal_sdc_dat_value_from_card[1]); |
---|
1326 | card->p_sdc_dat_value_out[2] (signal_sdc_dat_value_from_card[2]); |
---|
1327 | card->p_sdc_dat_value_out[3] (signal_sdc_dat_value_from_card[3]); |
---|
1328 | card->p_sdc_dat_enable_in (signal_sdc_dat_enable_to_card); |
---|
1329 | card->p_sdc_dat_value_in[0] (signal_sdc_dat_value_to_card[0]); |
---|
1330 | card->p_sdc_dat_value_in[1] (signal_sdc_dat_value_to_card[1]); |
---|
1331 | card->p_sdc_dat_value_in[2] (signal_sdc_dat_value_to_card[2]); |
---|
1332 | card->p_sdc_dat_value_in[3] (signal_sdc_dat_value_to_card[3]); |
---|
1333 | |
---|
1334 | #endif |
---|
1335 | |
---|
1336 | std::cout << " - DISK connected" << std::endl; |
---|
1337 | |
---|
1338 | // FBUF connexion |
---|
1339 | fbuf->p_clk (signal_clk); |
---|
1340 | fbuf->p_resetn (signal_resetn); |
---|
1341 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
1342 | |
---|
1343 | std::cout << " - FBUF connected" << std::endl; |
---|
1344 | |
---|
1345 | // MNIC connexion |
---|
1346 | mnic->p_clk (signal_clk); |
---|
1347 | mnic->p_resetn (signal_resetn); |
---|
1348 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
1349 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
1350 | { |
---|
1351 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
1352 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
1353 | } |
---|
1354 | |
---|
1355 | std::cout << " - MNIC connected" << std::endl; |
---|
1356 | |
---|
1357 | // BROM connexion |
---|
1358 | brom->p_clk (signal_clk); |
---|
1359 | brom->p_resetn (signal_resetn); |
---|
1360 | brom->p_vci (signal_vci_tgt_brom); |
---|
1361 | |
---|
1362 | std::cout << " - BROM connected" << std::endl; |
---|
1363 | |
---|
1364 | // MTTY connexion |
---|
1365 | mtty->p_clk (signal_clk); |
---|
1366 | mtty->p_resetn (signal_resetn); |
---|
1367 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
1368 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
1369 | { |
---|
1370 | mtty->p_irq[i] (signal_irq_mtty_rx[i]); |
---|
1371 | } |
---|
1372 | std::cout << " - MTTY connected" << std::endl; |
---|
1373 | |
---|
1374 | // CDMA connexion |
---|
1375 | cdma->p_clk (signal_clk); |
---|
1376 | cdma->p_resetn (signal_resetn); |
---|
1377 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
1378 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
1379 | for ( size_t i=0 ; i<(NB_CMA_CHANNELS) ; i++) |
---|
1380 | { |
---|
1381 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
1382 | } |
---|
1383 | |
---|
1384 | std::cout << " - CDMA connected" << std::endl; |
---|
1385 | |
---|
1386 | // IOPI connexion |
---|
1387 | iopi->p_clk (signal_clk); |
---|
1388 | iopi->p_resetn (signal_resetn); |
---|
1389 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
1390 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
1391 | for ( size_t i=0 ; i<32 ; i++) |
---|
1392 | { |
---|
1393 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
1394 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
1395 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
1396 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
1397 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
1398 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
1399 | else if(i < 9) iopi->p_hwi[i] (signal_irq_disk); |
---|
1400 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
1401 | else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
1402 | else iopi->p_hwi[i] (signal_irq_false); |
---|
1403 | } |
---|
1404 | |
---|
1405 | std::cout << " - IOPIC connected" << std::endl; |
---|
1406 | |
---|
1407 | |
---|
1408 | // IOB0 cluster connexion to IOX network |
---|
1409 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
1410 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
1411 | |
---|
1412 | // IOB1 cluster connexion to IOX network |
---|
1413 | // (only when there is more than 1 cluster) |
---|
1414 | if ( cluster_iob0 != cluster_iob1 ) |
---|
1415 | { |
---|
1416 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
1417 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
1418 | } |
---|
1419 | |
---|
1420 | // All clusters Clock & RESET connexions |
---|
1421 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
1422 | { |
---|
1423 | for (size_t y = 0; y < YMAX; y++) |
---|
1424 | { |
---|
1425 | clusters[x][y]->p_clk (signal_clk); |
---|
1426 | clusters[x][y]->p_resetn (signal_resetn); |
---|
1427 | } |
---|
1428 | } |
---|
1429 | |
---|
1430 | // Inter Clusters horizontal connections |
---|
1431 | if (XMAX > 1) |
---|
1432 | { |
---|
1433 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
1434 | { |
---|
1435 | for (size_t y = 0; y < YMAX; y++) |
---|
1436 | { |
---|
1437 | clusters[x][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
1438 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
1439 | clusters[x][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
1440 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
1441 | |
---|
1442 | clusters[x][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
1443 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
1444 | clusters[x][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
1445 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
1446 | |
---|
1447 | clusters[x][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
1448 | clusters[x+1][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
1449 | clusters[x][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
1450 | clusters[x+1][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
1451 | |
---|
1452 | clusters[x][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
1453 | clusters[x+1][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
1454 | clusters[x][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
1455 | clusters[x+1][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
1456 | |
---|
1457 | clusters[x][y]->p_dspin_int_cla_out[EAST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
1458 | clusters[x+1][y]->p_dspin_int_cla_in[WEST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
1459 | clusters[x][y]->p_dspin_int_cla_in[EAST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
1460 | clusters[x+1][y]->p_dspin_int_cla_out[WEST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
1461 | |
---|
1462 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1463 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1464 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1465 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1466 | |
---|
1467 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1468 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1469 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1470 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1471 | } |
---|
1472 | } |
---|
1473 | } |
---|
1474 | |
---|
1475 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
1476 | |
---|
1477 | // Inter Clusters vertical connections |
---|
1478 | if (YMAX > 1) |
---|
1479 | { |
---|
1480 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
1481 | { |
---|
1482 | for (size_t x = 0; x < XMAX; x++) |
---|
1483 | { |
---|
1484 | clusters[x][y]->p_dspin_int_cmd_out[NORTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
1485 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
1486 | clusters[x][y]->p_dspin_int_cmd_in[NORTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
1487 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
1488 | |
---|
1489 | clusters[x][y]->p_dspin_int_rsp_out[NORTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
1490 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
1491 | clusters[x][y]->p_dspin_int_rsp_in[NORTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
1492 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
1493 | |
---|
1494 | clusters[x][y]->p_dspin_int_m2p_out[NORTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
1495 | clusters[x][y+1]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
1496 | clusters[x][y]->p_dspin_int_m2p_in[NORTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
1497 | clusters[x][y+1]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
1498 | |
---|
1499 | clusters[x][y]->p_dspin_int_p2m_out[NORTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
1500 | clusters[x][y+1]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
1501 | clusters[x][y]->p_dspin_int_p2m_in[NORTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
1502 | clusters[x][y+1]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
1503 | |
---|
1504 | clusters[x][y]->p_dspin_int_cla_out[NORTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
1505 | clusters[x][y+1]->p_dspin_int_cla_in[SOUTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
1506 | clusters[x][y]->p_dspin_int_cla_in[NORTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
1507 | clusters[x][y+1]->p_dspin_int_cla_out[SOUTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
1508 | |
---|
1509 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1510 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1511 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1512 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1513 | |
---|
1514 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1515 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1516 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1517 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1518 | } |
---|
1519 | } |
---|
1520 | } |
---|
1521 | |
---|
1522 | std::cout << "Vertical connections established" << std::endl; |
---|
1523 | |
---|
1524 | // East & West boundary cluster connections |
---|
1525 | for (size_t y = 0; y < YMAX; y++) |
---|
1526 | { |
---|
1527 | clusters[0][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_false_int_cmd_in[0][y][WEST]); |
---|
1528 | clusters[0][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_false_int_cmd_out[0][y][WEST]); |
---|
1529 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST]); |
---|
1530 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST]); |
---|
1531 | |
---|
1532 | clusters[0][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_false_int_rsp_in[0][y][WEST]); |
---|
1533 | clusters[0][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_false_int_rsp_out[0][y][WEST]); |
---|
1534 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST]); |
---|
1535 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST]); |
---|
1536 | |
---|
1537 | clusters[0][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_false_int_m2p_in[0][y][WEST]); |
---|
1538 | clusters[0][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_false_int_m2p_out[0][y][WEST]); |
---|
1539 | clusters[XMAX-1][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_false_int_m2p_in[XMAX-1][y][EAST]); |
---|
1540 | clusters[XMAX-1][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_false_int_m2p_out[XMAX-1][y][EAST]); |
---|
1541 | |
---|
1542 | clusters[0][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_false_int_p2m_in[0][y][WEST]); |
---|
1543 | clusters[0][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_false_int_p2m_out[0][y][WEST]); |
---|
1544 | clusters[XMAX-1][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_false_int_p2m_in[XMAX-1][y][EAST]); |
---|
1545 | clusters[XMAX-1][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_false_int_p2m_out[XMAX-1][y][EAST]); |
---|
1546 | |
---|
1547 | clusters[0][y]->p_dspin_int_cla_in[WEST] (signal_dspin_false_int_cla_in[0][y][WEST]); |
---|
1548 | clusters[0][y]->p_dspin_int_cla_out[WEST] (signal_dspin_false_int_cla_out[0][y][WEST]); |
---|
1549 | clusters[XMAX-1][y]->p_dspin_int_cla_in[EAST] (signal_dspin_false_int_cla_in[XMAX-1][y][EAST]); |
---|
1550 | clusters[XMAX-1][y]->p_dspin_int_cla_out[EAST] (signal_dspin_false_int_cla_out[XMAX-1][y][EAST]); |
---|
1551 | |
---|
1552 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
1553 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
1554 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
1555 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
1556 | |
---|
1557 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
1558 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
1559 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
1560 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
1561 | } |
---|
1562 | |
---|
1563 | std::cout << "East & West boundaries established" << std::endl; |
---|
1564 | |
---|
1565 | // North & South boundary clusters connections |
---|
1566 | for (size_t x = 0; x < XMAX; x++) |
---|
1567 | { |
---|
1568 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_false_int_cmd_in[x][0][SOUTH]); |
---|
1569 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_false_int_cmd_out[x][0][SOUTH]); |
---|
1570 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH]); |
---|
1571 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH]); |
---|
1572 | |
---|
1573 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_false_int_rsp_in[x][0][SOUTH]); |
---|
1574 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_false_int_rsp_out[x][0][SOUTH]); |
---|
1575 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH]); |
---|
1576 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH]); |
---|
1577 | |
---|
1578 | clusters[x][0]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_false_int_m2p_in[x][0][SOUTH]); |
---|
1579 | clusters[x][0]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_false_int_m2p_out[x][0][SOUTH]); |
---|
1580 | clusters[x][YMAX-1]->p_dspin_int_m2p_in[NORTH] (signal_dspin_false_int_m2p_in[x][YMAX-1][NORTH]); |
---|
1581 | clusters[x][YMAX-1]->p_dspin_int_m2p_out[NORTH] (signal_dspin_false_int_m2p_out[x][YMAX-1][NORTH]); |
---|
1582 | |
---|
1583 | clusters[x][0]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_false_int_p2m_in[x][0][SOUTH]); |
---|
1584 | clusters[x][0]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_false_int_p2m_out[x][0][SOUTH]); |
---|
1585 | clusters[x][YMAX-1]->p_dspin_int_p2m_in[NORTH] (signal_dspin_false_int_p2m_in[x][YMAX-1][NORTH]); |
---|
1586 | clusters[x][YMAX-1]->p_dspin_int_p2m_out[NORTH] (signal_dspin_false_int_p2m_out[x][YMAX-1][NORTH]); |
---|
1587 | |
---|
1588 | clusters[x][0]->p_dspin_int_cla_in[SOUTH] (signal_dspin_false_int_cla_in[x][0][SOUTH]); |
---|
1589 | clusters[x][0]->p_dspin_int_cla_out[SOUTH] (signal_dspin_false_int_cla_out[x][0][SOUTH]); |
---|
1590 | clusters[x][YMAX-1]->p_dspin_int_cla_in[NORTH] (signal_dspin_false_int_cla_in[x][YMAX-1][NORTH]); |
---|
1591 | clusters[x][YMAX-1]->p_dspin_int_cla_out[NORTH] (signal_dspin_false_int_cla_out[x][YMAX-1][NORTH]); |
---|
1592 | |
---|
1593 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
1594 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
1595 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
1596 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
1597 | |
---|
1598 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
1599 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
1600 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
1601 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
1602 | } |
---|
1603 | |
---|
1604 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
1605 | |
---|
1606 | //////////////////////////////////////////////////////// |
---|
1607 | // Simulation |
---|
1608 | /////////////////////////////////////////////////////// |
---|
1609 | |
---|
1610 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
1611 | |
---|
1612 | signal_resetn = false; |
---|
1613 | signal_irq_false = false; |
---|
1614 | |
---|
1615 | // network boundaries signals |
---|
1616 | for (size_t x = 0; x < XMAX ; x++) |
---|
1617 | { |
---|
1618 | for (size_t y = 0; y < YMAX ; y++) |
---|
1619 | { |
---|
1620 | for (size_t a = 0; a < 4; a++) |
---|
1621 | { |
---|
1622 | signal_dspin_false_int_cmd_in[x][y][a].write = false; |
---|
1623 | signal_dspin_false_int_cmd_in[x][y][a].read = true; |
---|
1624 | signal_dspin_false_int_cmd_out[x][y][a].write = false; |
---|
1625 | signal_dspin_false_int_cmd_out[x][y][a].read = true; |
---|
1626 | |
---|
1627 | signal_dspin_false_int_rsp_in[x][y][a].write = false; |
---|
1628 | signal_dspin_false_int_rsp_in[x][y][a].read = true; |
---|
1629 | signal_dspin_false_int_rsp_out[x][y][a].write = false; |
---|
1630 | signal_dspin_false_int_rsp_out[x][y][a].read = true; |
---|
1631 | |
---|
1632 | signal_dspin_false_int_m2p_in[x][y][a].write = false; |
---|
1633 | signal_dspin_false_int_m2p_in[x][y][a].read = true; |
---|
1634 | signal_dspin_false_int_m2p_out[x][y][a].write = false; |
---|
1635 | signal_dspin_false_int_m2p_out[x][y][a].read = true; |
---|
1636 | |
---|
1637 | signal_dspin_false_int_p2m_in[x][y][a].write = false; |
---|
1638 | signal_dspin_false_int_p2m_in[x][y][a].read = true; |
---|
1639 | signal_dspin_false_int_p2m_out[x][y][a].write = false; |
---|
1640 | signal_dspin_false_int_p2m_out[x][y][a].read = true; |
---|
1641 | |
---|
1642 | signal_dspin_false_int_cla_in[x][y][a].write = false; |
---|
1643 | signal_dspin_false_int_cla_in[x][y][a].read = true; |
---|
1644 | signal_dspin_false_int_cla_out[x][y][a].write = false; |
---|
1645 | signal_dspin_false_int_cla_out[x][y][a].read = true; |
---|
1646 | |
---|
1647 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
1648 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
1649 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
1650 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
1651 | |
---|
1652 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
1653 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
1654 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
1655 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
1656 | } |
---|
1657 | } |
---|
1658 | } |
---|
1659 | |
---|
1660 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1661 | signal_resetn = true; |
---|
1662 | |
---|
1663 | |
---|
1664 | // simulation loop |
---|
1665 | struct timeval t1,t2; |
---|
1666 | gettimeofday(&t1, NULL); |
---|
1667 | |
---|
1668 | |
---|
1669 | for ( size_t n = 0; n < ncycles ; n += simul_period ) |
---|
1670 | { |
---|
1671 | // stats display |
---|
1672 | if( (n % 1000000) == 0) |
---|
1673 | { |
---|
1674 | gettimeofday(&t2, NULL); |
---|
1675 | |
---|
1676 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
1677 | (uint64_t) t1.tv_usec / 1000; |
---|
1678 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
1679 | (uint64_t) t2.tv_usec / 1000; |
---|
1680 | std::cerr << "### cycle = " << std::dec << n |
---|
1681 | << " / frequency = " |
---|
1682 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
---|
1683 | << std::endl; |
---|
1684 | |
---|
1685 | gettimeofday(&t1, NULL); |
---|
1686 | } |
---|
1687 | |
---|
1688 | // Monitor a specific address for one L1 cache |
---|
1689 | // clusters[0][0]->proc[0]->cache_monitor(0x800080ULL); |
---|
1690 | |
---|
1691 | // Monitor a specific address for one L2 cache (single word if second argument true) |
---|
1692 | // clusters[0][0]->memc->cache_monitor( 0x00FF8000ULL, false ); |
---|
1693 | |
---|
1694 | // Monitor a specific address for one XRAM |
---|
1695 | // clusters[0][0]->xram->start_monitor( 0x600800ULL , 64); |
---|
1696 | |
---|
1697 | if ( debug_ok and (n > debug_from) ) |
---|
1698 | { |
---|
1699 | std::cout << "****************** cycle " << std::dec << n ; |
---|
1700 | std::cout << " ************************************************" << std::endl; |
---|
1701 | |
---|
1702 | // trace proc[debug_proc_id] |
---|
1703 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
1704 | { |
---|
1705 | size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; |
---|
1706 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
1707 | size_t x = cluster_xy >> 4; |
---|
1708 | size_t y = cluster_xy & 0xF; |
---|
1709 | |
---|
1710 | clusters[x][y]->proc[l]->print_trace(0x1); |
---|
1711 | std::ostringstream proc_signame; |
---|
1712 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
1713 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
1714 | |
---|
1715 | clusters[x][y]->xicu->print_trace(1); |
---|
1716 | std::ostringstream xicu_signame; |
---|
1717 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
1718 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
1719 | |
---|
1720 | // coprocessor in cluster(x,y) |
---|
1721 | // clusters[x][y]->mwmr->print_trace(); |
---|
1722 | // std::ostringstream mwmr_tgt_signame; |
---|
1723 | // mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; |
---|
1724 | // clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); |
---|
1725 | // std::ostringstream mwmr_ini_signame; |
---|
1726 | // mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; |
---|
1727 | // clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); |
---|
1728 | // if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); |
---|
1729 | // if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); |
---|
1730 | // if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); |
---|
1731 | |
---|
1732 | // local interrupts in cluster(x,y) |
---|
1733 | if( clusters[x][y]->signal_irq_memc.read() ) |
---|
1734 | std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y |
---|
1735 | << " ACTIVE" << std::endl; |
---|
1736 | |
---|
1737 | if( clusters[x][y]->signal_irq_mwmr.read() ) |
---|
1738 | std::cout << "### IRQ_MWR_" << std::dec << x << "_" << y |
---|
1739 | << " ACTIVE" << std::endl; |
---|
1740 | |
---|
1741 | for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) |
---|
1742 | { |
---|
1743 | if( clusters[x][y]->signal_proc_it[c].read() ) |
---|
1744 | std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c |
---|
1745 | << " ACTIVE" << std::endl; |
---|
1746 | } |
---|
1747 | } |
---|
1748 | |
---|
1749 | // trace memc[debug_memc_id] |
---|
1750 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
1751 | { |
---|
1752 | size_t x = debug_memc_id >> 4; |
---|
1753 | size_t y = debug_memc_id & 0xF; |
---|
1754 | |
---|
1755 | clusters[x][y]->memc->print_trace(0); |
---|
1756 | std::ostringstream smemc_tgt; |
---|
1757 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
1758 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
1759 | std::ostringstream smemc_ini; |
---|
1760 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
1761 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
1762 | |
---|
1763 | clusters[x][y]->xram->print_trace(); |
---|
1764 | std::ostringstream sxram_tgt; |
---|
1765 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
1766 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
1767 | } |
---|
1768 | |
---|
1769 | |
---|
1770 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
1771 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
1772 | { |
---|
1773 | size_t x = debug_xram_id >> 4; |
---|
1774 | size_t y = debug_xram_id & 0xF; |
---|
1775 | |
---|
1776 | clusters[x][y]->xram->print_trace(); |
---|
1777 | std::ostringstream sxram_tgt; |
---|
1778 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
1779 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
1780 | |
---|
1781 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
1782 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
1783 | } |
---|
1784 | |
---|
1785 | // trace iob, iox and external peripherals |
---|
1786 | if ( debug_iob ) |
---|
1787 | { |
---|
1788 | // clusters[0][0]->iob->print_trace(); |
---|
1789 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
1790 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
1791 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
1792 | // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
1793 | // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
1794 | |
---|
1795 | // cdma->print_trace(); |
---|
1796 | // signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); |
---|
1797 | // signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); |
---|
1798 | |
---|
1799 | // brom->print_trace(); |
---|
1800 | // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); |
---|
1801 | |
---|
1802 | // mtty->print_trace(); |
---|
1803 | // signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); |
---|
1804 | |
---|
1805 | disk->print_trace(); |
---|
1806 | signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); |
---|
1807 | signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); |
---|
1808 | |
---|
1809 | #if ( USE_IOC_SDC ) |
---|
1810 | card->print_trace(); |
---|
1811 | #endif |
---|
1812 | |
---|
1813 | // mnic->print_trace( 0x000 ); |
---|
1814 | // signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
1815 | |
---|
1816 | // fbuf->print_trace(); |
---|
1817 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); |
---|
1818 | |
---|
1819 | // iopi->print_trace(); |
---|
1820 | // signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
1821 | // signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
1822 | |
---|
1823 | // iox_network->print_trace(); |
---|
1824 | |
---|
1825 | // interrupts |
---|
1826 | if ( signal_irq_disk.read() ) |
---|
1827 | std::cout << "### IRQ_DISK ACTIVE" << std::endl; |
---|
1828 | |
---|
1829 | if ( signal_irq_mtty_rx[0].read() ) |
---|
1830 | std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; |
---|
1831 | |
---|
1832 | if ( signal_irq_mnic_rx[0].read() ) |
---|
1833 | std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
1834 | |
---|
1835 | if ( signal_irq_mnic_tx[0].read() ) |
---|
1836 | std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
1837 | } |
---|
1838 | } |
---|
1839 | |
---|
1840 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
1841 | } |
---|
1842 | return EXIT_SUCCESS; |
---|
1843 | } |
---|
1844 | |
---|
1845 | int sc_main (int argc, char *argv[]) |
---|
1846 | { |
---|
1847 | try { |
---|
1848 | return _main(argc, argv); |
---|
1849 | } catch (std::exception &e) { |
---|
1850 | std::cout << e.what() << std::endl; |
---|
1851 | } catch (...) { |
---|
1852 | std::cout << "Unknown exception occured" << std::endl; |
---|
1853 | throw; |
---|
1854 | } |
---|
1855 | return 1; |
---|
1856 | } |
---|
1857 | |
---|
1858 | |
---|
1859 | // Local Variables: |
---|
1860 | // tab-width: 3 |
---|
1861 | // c-basic-offset: 3 |
---|
1862 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
1863 | // indent-tabs-mode: nil |
---|
1864 | // End: |
---|
1865 | |
---|
1866 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
1867 | |
---|
1868 | |
---|
1869 | |
---|