1 | /////////////////////////////////////////////////////////////////////////////// |
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2 | // File: top.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : august 2013 |
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6 | // This program is released under the GNU public license |
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7 | /////////////////////////////////////////////////////////////////////////////// |
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8 | // This file define a generic TSAR architecture with an IO network emulating |
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9 | // an external bus (i.e. Hypertransport) to access external peripherals: |
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10 | // |
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11 | // - BROM : boot ROM |
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12 | // - FBUF : Frame Buffer |
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13 | // - MTTY : multi TTY (up to 15 channels) |
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14 | // - MNIC : Network controller (up to 2 channels) |
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15 | // - CDMA : Chained Buffer controller (up to 4 channels) |
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16 | // - BDEV : Dlock Device controler (1 channel) |
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17 | // |
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18 | // The internal physical address space is 40 bits. |
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19 | // |
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20 | // It contains a 2D mesh of XMAX*YMAX clusters, and 3 networks: |
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21 | // |
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22 | // 1) the INT network supports Read/Write transactions |
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23 | // between processors and L2 caches or peripherals. |
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24 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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25 | // It supports also coherence transactions between L1 & L2 caches. |
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26 | // 3) the RAM network is emulating the 3D network between L2 caches |
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27 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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28 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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29 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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30 | // 4) the IOX network connects the two IO bridge components to the |
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31 | // 6 external peripheral controllers. |
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32 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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33 | // |
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34 | // The external peripherals IRQs are connected to the XICU component |
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35 | // in cluster(0,0): therefore, the number of channels for the external |
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36 | // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports... |
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37 | // |
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38 | // In all clusters, the IRQs are connected to XICU as follow: |
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39 | // - IRQ_IN[0] to IRQ_IN[3] not connected (reserved for context switch) |
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40 | // - IRQ_IN[4] to IRQ_IN[7] are connected to 4 MDMA channels |
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41 | // |
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42 | // In external peripheral IRQs are connected in cluster(0,0) only: |
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43 | // - IRQ_IN[8] to IRQ_IN[9] are connected to 2 NIC_RX channels. |
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44 | // - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels. |
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45 | // - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels |
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46 | // - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels |
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47 | // - IRQ_IN[31] is connected to BDEV |
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48 | // |
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49 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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50 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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51 | // connected to the three networks (INT, RAM, IOX). |
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52 | // The number of clusters cannot be larger than 256. |
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53 | // The number of processors per cluster cannot be larger than 4. |
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54 | // |
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55 | // - It uses two dspin_local_crossbar per cluster to implement the |
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56 | // local interconnect correponding to the INT network. |
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57 | // - It uses two dspin_local_crossbar per cluster to implement the |
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58 | // local interconnect correponding to the coherence INT network. |
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59 | // - It uses two virtual_dspin_router per cluster to implement |
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60 | // the INT network (routing both the direct and coherence trafic). |
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61 | // - It uses two dspin_router per cluster to implement the RAM network. |
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62 | // - It uses the vci_cc_vcache_wrapper. |
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63 | // - It uses the vci_mem_cache. |
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64 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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65 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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66 | // |
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67 | // The TsarIobCluster component is defined in files |
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68 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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69 | // |
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70 | // The main hardware parameters must be defined in the hard_config.h file : |
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71 | // - XMAX : number of clusters in a row (power of 2) |
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72 | // - YMAX : number of clusters in a column (power of 2) |
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73 | // - CLUSTER_SIZE : size of the segment allocated to a cluster |
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74 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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75 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) |
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76 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16) |
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77 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9) |
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78 | // |
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79 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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80 | // - XRAM_LATENCY : external ram latency |
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81 | // - MEMC_WAYS : L2 cache number of ways |
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82 | // - MEMC_SETS : L2 cache number of sets |
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83 | // - L1_IWAYS |
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84 | // - L1_ISETS |
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85 | // - L1_DWAYS |
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86 | // - L1_DSETS |
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87 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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88 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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89 | // - BDEV_SECTOR_SIZE : block size for block drvice |
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90 | // - BDEV_IMAGE_NAME : file pathname for block device |
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91 | // - NIC_RX_NAME : file pathname for NIC received packets |
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92 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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93 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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94 | // |
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95 | // General policy for 40 bits physical address decoding: |
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96 | // All physical segments base addresses are multiple of 1 Mbytes |
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97 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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98 | // The (x_width + y_width) MSB bits (left aligned) define |
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99 | // the cluster index, and the LADR bits define the local index: |
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100 | // | X_ID | Y_ID |---| LADR | OFFSET | |
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101 | // |x_width|y_width|---| 8 | 24 | |
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102 | // |
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103 | // General policy for 14 bits SRCID decoding: |
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104 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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105 | // | X_ID | Y_ID |---| L_ID | |
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106 | // |x_width|y_width|---| 6 | |
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107 | ///////////////////////////////////////////////////////////////////////// |
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108 | |
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109 | #include <systemc> |
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110 | #include <sys/time.h> |
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111 | #include <iostream> |
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112 | #include <sstream> |
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113 | #include <cstdlib> |
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114 | #include <cstdarg> |
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115 | #include <stdint.h> |
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116 | |
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117 | #include "gdbserver.h" |
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118 | #include "mapping_table.h" |
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119 | |
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120 | #include "tsar_iob_cluster.h" |
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121 | #include "vci_chbuf_dma.h" |
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122 | #include "vci_multi_tty.h" |
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123 | #include "vci_multi_nic.h" |
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124 | #include "vci_simple_rom.h" |
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125 | #include "vci_block_device_tsar.h" |
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126 | #include "vci_framebuffer.h" |
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127 | #include "vci_iox_network.h" |
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128 | |
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129 | #include "alloc_elems.h" |
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130 | |
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131 | /////////////////////////////////////////////////// |
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132 | // OS |
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133 | /////////////////////////////////////////////////// |
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134 | #define USE_ALMOS 0 |
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135 | |
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136 | #define almos_bootloader_pathname "bootloader.bin" |
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137 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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138 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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139 | |
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140 | /////////////////////////////////////////////////// |
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141 | // Parallelisation |
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142 | /////////////////////////////////////////////////// |
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143 | #define USE_OPENMP 0 |
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144 | |
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145 | #if USE_OPENMP |
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146 | #include <omp.h> |
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147 | #endif |
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148 | |
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149 | /////////////////////////////////////////////////////////// |
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150 | // DSPIN parameters |
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151 | /////////////////////////////////////////////////////////// |
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152 | |
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153 | #define dspin_int_cmd_width 39 |
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154 | #define dspin_int_rsp_width 32 |
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155 | |
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156 | #define dspin_ram_cmd_width 64 |
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157 | #define dspin_ram_rsp_width 64 |
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158 | |
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159 | /////////////////////////////////////////////////////////// |
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160 | // VCI fields width for the 3 VCI networks |
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161 | /////////////////////////////////////////////////////////// |
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162 | |
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163 | #define vci_cell_width_int 4 |
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164 | #define vci_cell_width_ext 8 |
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165 | |
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166 | #define vci_plen_width 8 |
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167 | #define vci_address_width 40 |
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168 | #define vci_rerror_width 1 |
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169 | #define vci_clen_width 1 |
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170 | #define vci_rflag_width 1 |
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171 | #define vci_srcid_width 14 |
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172 | #define vci_pktid_width 4 |
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173 | #define vci_trdid_width 4 |
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174 | #define vci_wrplen_width 1 |
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175 | |
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176 | //////////////////////////////////////////////////////////// |
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177 | // Main Hardware Parameters values |
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178 | //////////////////////i///////////////////////////////////// |
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179 | |
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180 | #include "giet_vm/hard_config.h" |
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181 | |
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182 | //////////////////////////////////////////////////////////// |
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183 | // Secondary Hardware Parameters values |
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184 | //////////////////////i///////////////////////////////////// |
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185 | |
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186 | #define XMAX CLUSTER_X |
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187 | #define YMAX CLUSTER_Y |
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188 | |
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189 | #define XRAM_LATENCY 0 |
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190 | |
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191 | #define MEMC_WAYS 16 |
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192 | #define MEMC_SETS 256 |
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193 | |
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194 | #define L1_IWAYS 4 |
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195 | #define L1_ISETS 64 |
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196 | |
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197 | #define L1_DWAYS 4 |
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198 | #define L1_DSETS 64 |
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199 | |
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200 | #define FBUF_X_SIZE 128 |
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201 | #define FBUF_Y_SIZE 128 |
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202 | |
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203 | #define BDEV_SECTOR_SIZE 512 |
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204 | #define BDEV_IMAGE_NAME "giet_vm/display/images.raw" |
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205 | |
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206 | #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" |
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207 | #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" |
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208 | #define NIC_TIMEOUT 10000 |
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209 | |
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210 | #define NORTH 0 |
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211 | #define SOUTH 1 |
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212 | #define EAST 2 |
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213 | #define WEST 3 |
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214 | |
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215 | #define cluster(x,y) ((y) + YMAX*(x)) |
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216 | |
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217 | //////////////////////////////////////////////////////////// |
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218 | // Software to be loaded in ROM & RAM |
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219 | //////////////////////i///////////////////////////////////// |
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220 | |
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221 | #define BOOT_SOFT_NAME "giet_vm/soft.elf" |
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222 | |
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223 | //////////////////////////////////////////////////////////// |
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224 | // DEBUG Parameters default values |
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225 | //////////////////////i///////////////////////////////////// |
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226 | |
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227 | #define MAX_FROZEN_CYCLES 10000 |
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228 | |
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229 | ///////////////////////////////////////////////////////// |
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230 | // Physical segments definition |
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231 | ///////////////////////////////////////////////////////// |
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232 | |
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233 | // Non replicated peripherals |
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234 | |
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235 | #define BROM_BASE 0x00BFC00000 |
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236 | #define BROM_SIZE 0x0000100000 // 1 M Kbytes |
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237 | |
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238 | #define IOBX_BASE 0x00BE000000 |
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239 | #define IOBX_SIZE 0x0000001000 // 4 K Kbytes |
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240 | |
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241 | #define BDEV_BASE 0x00B3000000 |
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242 | #define BDEV_SIZE 0x0000001000 // 4 Kbytes |
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243 | |
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244 | #define MTTY_BASE 0x00B4000000 |
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245 | #define MTTY_SIZE 0x0000001000 * NB_TTY_CHANNELS // 4 Kbytes |
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246 | |
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247 | #define MNIC_BASE 0x00B5000000 |
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248 | #define MNIC_SIZE 0x0000080000 // 512 Kbytes |
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249 | |
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250 | #define CDMA_BASE 0x00B6000000 |
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251 | #define CDMA_SIZE 0x0000001000 * (NB_NIC_CHANNELS * 2) // 4 Kbytes per channel |
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252 | |
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253 | #define FBUF_BASE 0x00B7000000 |
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254 | #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE |
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255 | |
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256 | // replicated segments : address is incremented by a cluster offset |
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257 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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258 | |
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259 | #define XRAM_BASE 0x0000000000 |
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260 | #define XRAM_SIZE 0x0010000000 // 256 Mbytes |
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261 | |
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262 | #define XICU_BASE 0x00B0000000 |
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263 | #define XICU_SIZE 0x0000001000 // 4 Kbytes |
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264 | |
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265 | #define MDMA_BASE 0x00B1000000 |
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266 | #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel |
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267 | |
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268 | #define MEMC_BASE 0x00B2000000 |
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269 | #define MEMC_SIZE 0x0000001000 // 4 Kbytes |
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270 | |
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271 | |
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272 | //////////////////////////////////////////////////////////////////////// |
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273 | // SRCID definition |
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274 | //////////////////////////////////////////////////////////////////////// |
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275 | // All initiators are in the same indexing space (14 bits). |
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276 | // The SRCID is structured in two fields: |
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277 | // - The 10 MSB bits define the cluster index (left aligned) |
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278 | // - The 4 LSB bits define the local index. |
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279 | // Two different initiators cannot have the same SRCID, but a given |
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280 | // initiator can have two alias SRCIDs: |
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281 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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282 | // and each initiator has one single SRCID. |
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283 | // - External initiators (bdev, cdma) are not replicated, but can be |
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284 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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285 | // They have the same local index, but two different cluster indexes. |
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286 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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287 | // and external initiators, they must have different local indexes. |
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288 | // Consequence: For a local interconnect, the INI_ID port index |
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289 | // is NOT equal to the SRCID local index, and the local interconnect |
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290 | // must make a translation: SRCID => INI_ID (port index) |
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291 | //////////////////////////////////////////////////////////////////////// |
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292 | |
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293 | #define PROC_LOCAL_SRCID 0 // from 0 to 7 |
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294 | #define MDMA_LOCAL_SRCID 8 |
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295 | #define IOBX_LOCAL_SRCID 9 |
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296 | #define BDEV_LOCAL_SRCID 10 |
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297 | #define CDMA_LOCAL_SRCID 11 |
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298 | #define MEMC_LOCAL_SRCID 12 |
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299 | |
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300 | //////////////////////////////////////////////////////////////////// |
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301 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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302 | //////////////////////////////////////////////////////////////////// |
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303 | |
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304 | #define INT_MEMC_TGT_ID 0 |
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305 | #define INT_XICU_TGT_ID 1 |
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306 | #define INT_MDMA_TGT_ID 2 |
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307 | #define INT_IOBX_TGT_ID 3 |
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308 | |
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309 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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310 | #define INT_MDMA_INI_ID NB_PROCS_MAX |
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311 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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312 | |
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313 | //////////////////////////////////////////////////////////////////// |
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314 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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315 | //////////////////////////////////////////////////////////////////// |
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316 | |
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317 | #define RAM_XRAM_TGT_ID 0 |
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318 | |
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319 | #define RAM_MEMC_INI_ID 0 |
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320 | #define RAM_IOBX_INI_ID 1 |
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321 | |
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322 | //////////////////////////////////////////////////////////////////// |
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323 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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324 | //////////////////////////////////////////////////////////////////// |
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325 | |
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326 | #define IOX_IOB0_TGT_ID 0 // don't change this value |
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327 | #define IOX_IOB1_TGT_ID 1 // don't change this value |
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328 | #define IOX_FBUF_TGT_ID 2 |
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329 | #define IOX_BDEV_TGT_ID 3 |
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330 | #define IOX_MNIC_TGT_ID 4 |
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331 | #define IOX_CDMA_TGT_ID 5 |
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332 | #define IOX_BROM_TGT_ID 6 |
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333 | #define IOX_MTTY_TGT_ID 7 |
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334 | |
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335 | #define IOX_IOB0_INI_ID 0 // Don't change this value |
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336 | #define IOX_IOB1_INI_ID 1 // Don't change this value |
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337 | #define IOX_BDEV_INI_ID 2 |
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338 | #define IOX_CDMA_INI_ID 3 |
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339 | |
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340 | ///////////////////////////////////////////////////////////////////// |
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341 | int _main(int argc, char *argv[]) |
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342 | ///////////////////////////////////////////////////////////////////// |
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343 | { |
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344 | using namespace sc_core; |
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345 | using namespace soclib::caba; |
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346 | using namespace soclib::common; |
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347 | |
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348 | |
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349 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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350 | size_t ncycles = 1000000000; // simulated cycles |
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351 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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352 | char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file |
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353 | char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file |
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354 | ssize_t threads_nr = 1; // simulator's threads number |
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355 | bool debug_ok = false; // trace activated |
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356 | size_t debug_period = 1; // trace period |
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357 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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358 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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359 | bool debug_iob = false; // trace iob0 & iob1 when true |
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360 | uint32_t debug_from = 0; // trace start cycle |
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361 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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362 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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363 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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364 | size_t block_size = BDEV_SECTOR_SIZE; // disk block size |
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365 | |
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366 | ////////////// command line arguments ////////////////////// |
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367 | if (argc > 1) |
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368 | { |
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369 | for (int n = 1; n < argc; n = n + 2) |
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370 | { |
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371 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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372 | { |
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373 | ncycles = atoi(argv[n+1]); |
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374 | } |
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375 | else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) |
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376 | { |
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377 | strcpy(soft_name, argv[n+1]); |
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378 | } |
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379 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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380 | { |
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381 | debug_ok = true; |
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382 | debug_from = atoi(argv[n+1]); |
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383 | } |
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384 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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385 | { |
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386 | strcpy(disk_name, argv[n+1]); |
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387 | } |
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388 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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389 | { |
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390 | debug_memc_id = atoi(argv[n+1]); |
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391 | assert( (debug_memc_id < (XMAX*YMAX) ) && |
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392 | "debug_memc_id larger than XMAX * YMAX" ); |
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393 | } |
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394 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
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395 | { |
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396 | debug_iob = atoi(argv[n+1]); |
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397 | } |
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398 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
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399 | { |
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400 | debug_proc_id = atoi(argv[n+1]); |
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401 | assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) && |
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402 | "debug_proc_id larger than XMAX * YMAX * NB_PROCS" ); |
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403 | } |
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404 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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405 | { |
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406 | threads_nr = atoi(argv[n+1]); |
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407 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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408 | } |
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409 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
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410 | { |
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411 | frozen_cycles = atoi(argv[n+1]); |
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412 | } |
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413 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
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414 | { |
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415 | debug_period = atoi(argv[n+1]); |
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416 | } |
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417 | else |
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418 | { |
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419 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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420 | std::cout << " The order is not important." << std::endl; |
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421 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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422 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
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423 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
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424 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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425 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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426 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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427 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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428 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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429 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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430 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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431 | std::cout << " -IOBID index_iob_to_be_traced" << std::endl; |
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432 | exit(0); |
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433 | } |
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434 | } |
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435 | } |
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436 | |
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437 | // checking hardware parameters |
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438 | assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or |
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439 | (XMAX == 8) or (XMAX == 16) ) and |
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440 | "The XMAX parameter must be 1, 2, 4, 8 or 16" ); |
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441 | |
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442 | assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or |
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443 | (YMAX == 8) or (YMAX == 16) ) and |
---|
444 | "The YMAX parameter must be 1, 2, 4, 8 or 16" ); |
---|
445 | |
---|
446 | assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or (NB_PROCS_MAX == 4) ) and |
---|
447 | "The NB_PROCS_MAX parameter must be 1, 2, 4" ); |
---|
448 | |
---|
449 | assert( (NB_DMA_CHANNELS == 4) and |
---|
450 | "The NB_DMA_CHANNELS parameter must be 4" ); |
---|
451 | |
---|
452 | assert( (NB_TTY_CHANNELS < 16) and |
---|
453 | "The NB_TTY_CHANNELS parameter must be smaller than 16" ); |
---|
454 | |
---|
455 | assert( (NB_NIC_CHANNELS == 2) and |
---|
456 | "The NB_NIC_CHANNELS parameter must be 2" ); |
---|
457 | |
---|
458 | std::cout << std::endl; |
---|
459 | std::cout << " - XMAX = " << XMAX << std::endl; |
---|
460 | std::cout << " - YMAX = " << YMAX << std::endl; |
---|
461 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
---|
462 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
---|
463 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
---|
464 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
---|
465 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
---|
466 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
---|
467 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
---|
468 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
---|
469 | |
---|
470 | std::cout << std::endl; |
---|
471 | |
---|
472 | #if USE_OPENMP |
---|
473 | omp_set_dynamic(false); |
---|
474 | omp_set_num_threads(threads_nr); |
---|
475 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
476 | #endif |
---|
477 | |
---|
478 | // Define VciParams objects |
---|
479 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
480 | vci_plen_width, |
---|
481 | vci_address_width, |
---|
482 | vci_rerror_width, |
---|
483 | vci_clen_width, |
---|
484 | vci_rflag_width, |
---|
485 | vci_srcid_width, |
---|
486 | vci_pktid_width, |
---|
487 | vci_trdid_width, |
---|
488 | vci_wrplen_width> vci_param_int; |
---|
489 | |
---|
490 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
491 | vci_plen_width, |
---|
492 | vci_address_width, |
---|
493 | vci_rerror_width, |
---|
494 | vci_clen_width, |
---|
495 | vci_rflag_width, |
---|
496 | vci_srcid_width, |
---|
497 | vci_pktid_width, |
---|
498 | vci_trdid_width, |
---|
499 | vci_wrplen_width> vci_param_ext; |
---|
500 | |
---|
501 | // Define parameters depending on mesh size |
---|
502 | size_t x_width; |
---|
503 | size_t y_width; |
---|
504 | |
---|
505 | if (XMAX == 1) x_width = 0; |
---|
506 | else if (XMAX == 2) x_width = 1; |
---|
507 | else if (XMAX <= 4) x_width = 2; |
---|
508 | else if (XMAX <= 8) x_width = 3; |
---|
509 | else x_width = 4; |
---|
510 | |
---|
511 | if (YMAX == 1) y_width = 0; |
---|
512 | else if (YMAX == 2) y_width = 1; |
---|
513 | else if (YMAX <= 4) y_width = 2; |
---|
514 | else if (YMAX <= 8) y_width = 3; |
---|
515 | else y_width = 4; |
---|
516 | |
---|
517 | ///////////////////////////////////////////////////////////////////// |
---|
518 | // INT network mapping table |
---|
519 | // - two levels address decoding for commands |
---|
520 | // - two levels srcid decoding for responses |
---|
521 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
522 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
523 | ///////////////////////////////////////////////////////////////////// |
---|
524 | MappingTable maptab_int( vci_address_width, |
---|
525 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
526 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
527 | 0x00FF000000); |
---|
528 | |
---|
529 | for (size_t x = 0; x < XMAX; x++) |
---|
530 | { |
---|
531 | for (size_t y = 0; y < YMAX; y++) |
---|
532 | { |
---|
533 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
534 | << (vci_address_width-x_width-y_width); |
---|
535 | bool config = true; |
---|
536 | |
---|
537 | // the four following segments are defined in all clusters |
---|
538 | |
---|
539 | std::ostringstream smemc_conf; |
---|
540 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
541 | maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, |
---|
542 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), true, config )); |
---|
543 | |
---|
544 | std::ostringstream smemc_xram; |
---|
545 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
546 | maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, |
---|
547 | IntTab(cluster(x,y),INT_MEMC_TGT_ID), true)); |
---|
548 | |
---|
549 | std::ostringstream sxicu; |
---|
550 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
551 | maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, |
---|
552 | IntTab(cluster(x,y),INT_XICU_TGT_ID), false)); |
---|
553 | |
---|
554 | std::ostringstream smdma; |
---|
555 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
556 | maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, |
---|
557 | IntTab(cluster(x,y),INT_MDMA_TGT_ID), false)); |
---|
558 | |
---|
559 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
560 | |
---|
561 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
562 | { |
---|
563 | std::ostringstream siobx; |
---|
564 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
565 | maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, |
---|
566 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false, config )); |
---|
567 | |
---|
568 | std::ostringstream stty; |
---|
569 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
570 | maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, |
---|
571 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); |
---|
572 | |
---|
573 | std::ostringstream sfbf; |
---|
574 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
575 | maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, |
---|
576 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); |
---|
577 | |
---|
578 | std::ostringstream sbdv; |
---|
579 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
580 | maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, |
---|
581 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); |
---|
582 | |
---|
583 | std::ostringstream snic; |
---|
584 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
585 | maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, |
---|
586 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); |
---|
587 | |
---|
588 | std::ostringstream srom; |
---|
589 | srom << "int_seg_brom_" << x << "_" << y; |
---|
590 | maptab_int.add(Segment(srom.str(), BROM_BASE+offset, BROM_SIZE, |
---|
591 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), true)); |
---|
592 | |
---|
593 | std::ostringstream sdma; |
---|
594 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
595 | maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, |
---|
596 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); |
---|
597 | } |
---|
598 | |
---|
599 | // This define the mapping between the SRCIDs |
---|
600 | // and the port index on the local interconnect. |
---|
601 | |
---|
602 | maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), INT_MDMA_INI_ID ); |
---|
603 | |
---|
604 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), INT_IOBX_INI_ID ); |
---|
605 | |
---|
606 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) |
---|
607 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), INT_PROC_INI_ID+p ); |
---|
608 | } |
---|
609 | } |
---|
610 | std::cout << "INT network " << maptab_int << std::endl; |
---|
611 | |
---|
612 | ///////////////////////////////////////////////////////////////////////// |
---|
613 | // RAM network mapping table |
---|
614 | // - two levels address decoding for commands |
---|
615 | // - two levels srcid decoding for responses |
---|
616 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
617 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
618 | // - 1 local target (XRAM) per cluster |
---|
619 | //////////////////////////////////////////////////////////////////////// |
---|
620 | MappingTable maptab_ram( vci_address_width, |
---|
621 | IntTab(x_width+y_width, 16 - x_width - y_width), |
---|
622 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
623 | 0x00FF000000); |
---|
624 | |
---|
625 | for (size_t x = 0; x < XMAX; x++) |
---|
626 | { |
---|
627 | for (size_t y = 0; y < YMAX ; y++) |
---|
628 | { |
---|
629 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
630 | << (vci_address_width-x_width-y_width); |
---|
631 | |
---|
632 | std::ostringstream sxram; |
---|
633 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
634 | maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, |
---|
635 | XRAM_SIZE, IntTab(cluster(x,y), 0), false)); |
---|
636 | } |
---|
637 | } |
---|
638 | |
---|
639 | // This define the mapping between the initiators (identified by their |
---|
640 | // global SRCID) and the port index on the RAM local interconnect. |
---|
641 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
642 | |
---|
643 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); |
---|
644 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); |
---|
645 | |
---|
646 | maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); |
---|
647 | maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); |
---|
648 | |
---|
649 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), RAM_MEMC_INI_ID ); |
---|
650 | |
---|
651 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
652 | |
---|
653 | /////////////////////////////////////////////////////////////////////// |
---|
654 | // IOX network mapping table |
---|
655 | // - two levels address decoding for commands |
---|
656 | // - two levels srcid decoding for responses |
---|
657 | // - 4 initiators (IOB0, IOB1, BDEV, CDMA) |
---|
658 | // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) |
---|
659 | /////////////////////////////////////////////////////////////////////// |
---|
660 | MappingTable maptab_iox( vci_address_width, |
---|
661 | IntTab(x_width+y_width, 16 - x_width - y_width), |
---|
662 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
663 | 0x00FF000000); |
---|
664 | |
---|
665 | // compute base addresses for cluster_iob0 and cluster_iob1 |
---|
666 | uint64_t iob0_base = ((uint64_t)cluster_iob0) << (vci_address_width - x_width - y_width); |
---|
667 | uint64_t iob1_base = ((uint64_t)cluster_iob1) << (vci_address_width - x_width - y_width); |
---|
668 | |
---|
669 | // Each peripheral can be accessed through two segments, |
---|
670 | // depending on the used IOB (IOB0 or IOB1). |
---|
671 | maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, |
---|
672 | IntTab(cluster_iob0,IOX_MTTY_TGT_ID), false)); |
---|
673 | |
---|
674 | maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, |
---|
675 | IntTab(cluster_iob1,IOX_MTTY_TGT_ID), false)); |
---|
676 | |
---|
677 | maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, |
---|
678 | IntTab(cluster_iob0,IOX_FBUF_TGT_ID), false)); |
---|
679 | |
---|
680 | maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, |
---|
681 | IntTab(cluster_iob1,IOX_FBUF_TGT_ID), false)); |
---|
682 | |
---|
683 | maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, |
---|
684 | IntTab(cluster_iob0,IOX_BDEV_TGT_ID), false)); |
---|
685 | |
---|
686 | maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, |
---|
687 | IntTab(cluster_iob1,IOX_BDEV_TGT_ID), false)); |
---|
688 | |
---|
689 | maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, |
---|
690 | IntTab(cluster_iob0,IOX_MNIC_TGT_ID), false)); |
---|
691 | |
---|
692 | maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, |
---|
693 | IntTab(cluster_iob1,IOX_MNIC_TGT_ID), false)); |
---|
694 | |
---|
695 | maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, |
---|
696 | IntTab(cluster_iob0,IOX_CDMA_TGT_ID), false)); |
---|
697 | |
---|
698 | maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, |
---|
699 | IntTab(cluster_iob1,IOX_CDMA_TGT_ID), false)); |
---|
700 | |
---|
701 | maptab_iox.add(Segment("iox_seg_brom_0", BROM_BASE + iob0_base, BROM_SIZE, |
---|
702 | IntTab(cluster_iob0,IOX_BROM_TGT_ID), false)); |
---|
703 | |
---|
704 | maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, |
---|
705 | IntTab(cluster_iob1,IOX_BROM_TGT_ID), false)); |
---|
706 | |
---|
707 | // Each physical RAM can be accessed through IOB0, or through IOB1. |
---|
708 | // if IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
709 | // and the choice depends on on address bit A[39]. |
---|
710 | // if IOMMU is activated the addresses use only 32 bits (virtual addresses), |
---|
711 | // and the choice depends on address bit A[31]. |
---|
712 | for (size_t x = 0; x < XMAX; x++) |
---|
713 | { |
---|
714 | for (size_t y = 0; y < YMAX ; y++) |
---|
715 | { |
---|
716 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
717 | << (vci_address_width-x_width-y_width); |
---|
718 | |
---|
719 | if ( x < (XMAX/2) ) // send command to XRAM through IOB0 |
---|
720 | { |
---|
721 | std::ostringstream siob0; |
---|
722 | siob0 << "iox_seg_xram_" << x << "_" << y; |
---|
723 | maptab_iox.add(Segment(siob0.str(), offset, 0x80000000, |
---|
724 | IntTab(cluster_iob0,IOX_IOB0_TGT_ID), false)); |
---|
725 | } |
---|
726 | else // send command to XRAM through IOB1 |
---|
727 | { |
---|
728 | std::ostringstream siob1; |
---|
729 | siob1 << "iox_seg_xram_" << x << "_" << y; |
---|
730 | maptab_iox.add(Segment(siob1.str(), offset, 0x80000000, |
---|
731 | IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); |
---|
732 | } |
---|
733 | } |
---|
734 | } |
---|
735 | // useful when IOMMU activated |
---|
736 | maptab_iox.add(Segment("iox_seg_xram ", 0xc0000000, 0x40000000, |
---|
737 | IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); |
---|
738 | |
---|
739 | // This define the mapping between the initiators (identified by the SRCID) |
---|
740 | // and the port index on the IOX local interconnect. |
---|
741 | // External initiator have two alias SRCID (iob0 / iob1 access) |
---|
742 | |
---|
743 | maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); |
---|
744 | maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); |
---|
745 | |
---|
746 | maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); |
---|
747 | maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); |
---|
748 | |
---|
749 | for (size_t x = 0; x < XMAX; x++) |
---|
750 | { |
---|
751 | for (size_t y = 0; y < YMAX ; y++) |
---|
752 | { |
---|
753 | if ( x < (XMAX/2) ) // send response to proc or mdma through IOB0 |
---|
754 | { |
---|
755 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB0_INI_ID ); |
---|
756 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB0_INI_ID ); |
---|
757 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB0_INI_ID ); |
---|
758 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB0_INI_ID ); |
---|
759 | maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB0_INI_ID ); |
---|
760 | } |
---|
761 | else // send response to proc or mdma through IOB1 |
---|
762 | { |
---|
763 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB1_INI_ID ); |
---|
764 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB1_INI_ID ); |
---|
765 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB1_INI_ID ); |
---|
766 | maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB1_INI_ID ); |
---|
767 | maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB1_INI_ID ); |
---|
768 | } |
---|
769 | } |
---|
770 | } |
---|
771 | |
---|
772 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
773 | |
---|
774 | //////////////////// |
---|
775 | // Signals |
---|
776 | /////////////////// |
---|
777 | |
---|
778 | sc_clock signal_clk("clk"); |
---|
779 | sc_signal<bool> signal_resetn("resetn"); |
---|
780 | |
---|
781 | sc_signal<bool> signal_unused_irq[32]; |
---|
782 | sc_signal<bool> signal_irq_bdev; |
---|
783 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
784 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
785 | sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; |
---|
786 | sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; |
---|
787 | |
---|
788 | // VCI signals for IOX network |
---|
789 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
790 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
791 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
792 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
793 | |
---|
794 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
795 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
796 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
797 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
798 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
799 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
---|
800 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
801 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
802 | |
---|
803 | // Horizontal inter-clusters INT network DSPIN |
---|
804 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
805 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); |
---|
806 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
807 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); |
---|
808 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
809 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); |
---|
810 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
811 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); |
---|
812 | |
---|
813 | // Vertical inter-clusters INT network DSPIN |
---|
814 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
815 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); |
---|
816 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
817 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); |
---|
818 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
819 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); |
---|
820 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
821 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); |
---|
822 | |
---|
823 | // Mesh boundaries INT network DSPIN |
---|
824 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
825 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); |
---|
826 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
827 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); |
---|
828 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
829 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); |
---|
830 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
831 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); |
---|
832 | |
---|
833 | |
---|
834 | // Horizontal inter-clusters RAM network DSPIN |
---|
835 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
836 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
837 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
838 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
839 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
840 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
841 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
842 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
843 | |
---|
844 | // Vertical inter-clusters RAM network DSPIN |
---|
845 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
846 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
847 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
848 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
849 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
850 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
851 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
852 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
853 | |
---|
854 | // Mesh boundaries RAM network DSPIN |
---|
855 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
856 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
857 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
858 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
859 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
860 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
861 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
862 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
863 | |
---|
864 | //////////////////////////// |
---|
865 | // Loader |
---|
866 | //////////////////////////// |
---|
867 | |
---|
868 | #if USE_ALMOS |
---|
869 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
870 | almos_archinfo_pathname, |
---|
871 | almos_kernel_pathname); |
---|
872 | #else |
---|
873 | soclib::common::Loader loader(soft_name); |
---|
874 | #endif |
---|
875 | |
---|
876 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
877 | proc_iss::set_loader(loader); |
---|
878 | |
---|
879 | //////////////////////////////////////// |
---|
880 | // Instanciated Hardware Components |
---|
881 | //////////////////////////////////////// |
---|
882 | |
---|
883 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
884 | |
---|
885 | // IOX network |
---|
886 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
887 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
888 | maptab_iox, |
---|
889 | 0, // cluster_id |
---|
890 | 8, // number of targets |
---|
891 | 4 ); // number of initiators |
---|
892 | // boot ROM |
---|
893 | VciSimpleRom<vci_param_ext>* iox_brom; |
---|
894 | iox_brom = new VciSimpleRom<vci_param_ext>( "iox_brom", |
---|
895 | IntTab(0, IOX_BROM_TGT_ID), |
---|
896 | maptab_iox, |
---|
897 | loader ); |
---|
898 | // Network Controller |
---|
899 | VciMultiNic<vci_param_ext>* iox_mnic; |
---|
900 | iox_mnic = new VciMultiNic<vci_param_ext>( "iox_mnic", |
---|
901 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
902 | maptab_iox, |
---|
903 | NB_NIC_CHANNELS, |
---|
904 | nic_rx_name, |
---|
905 | nic_tx_name, |
---|
906 | 0, // mac_4 address |
---|
907 | 0 ); // mac_2 address |
---|
908 | |
---|
909 | // Frame Buffer |
---|
910 | VciFrameBuffer<vci_param_ext>* iox_fbuf; |
---|
911 | iox_fbuf = new VciFrameBuffer<vci_param_ext>( "iox_fbuf", |
---|
912 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
913 | maptab_iox, |
---|
914 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
915 | |
---|
916 | // Block Device |
---|
917 | VciBlockDeviceTsar<vci_param_ext>* iox_bdev; |
---|
918 | iox_bdev = new VciBlockDeviceTsar<vci_param_ext>( "iox_bdev", |
---|
919 | maptab_iox, |
---|
920 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
921 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
922 | disk_name, |
---|
923 | block_size, |
---|
924 | 64); // burst size (bytes) |
---|
925 | |
---|
926 | // Chained Buffer DMA controller |
---|
927 | VciChbufDma<vci_param_ext>* iox_cdma; |
---|
928 | iox_cdma = new VciChbufDma<vci_param_ext>( "iox_cdma", |
---|
929 | maptab_iox, |
---|
930 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
931 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
932 | 64, // burst size (bytes) |
---|
933 | 2*NB_NIC_CHANNELS ); |
---|
934 | // Multi-TTY controller |
---|
935 | std::vector<std::string> vect_names; |
---|
936 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
937 | { |
---|
938 | std::ostringstream term_name; |
---|
939 | term_name << "term" << tid; |
---|
940 | vect_names.push_back(term_name.str().c_str()); |
---|
941 | } |
---|
942 | VciMultiTty<vci_param_ext>* iox_mtty; |
---|
943 | iox_mtty = new VciMultiTty<vci_param_ext>( "iox_mtty", |
---|
944 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
945 | maptab_iox, |
---|
946 | vect_names); |
---|
947 | // Clusters |
---|
948 | TsarIobCluster<vci_param_int, |
---|
949 | vci_param_ext, |
---|
950 | dspin_int_cmd_width, |
---|
951 | dspin_int_rsp_width, |
---|
952 | dspin_ram_cmd_width, |
---|
953 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
954 | |
---|
955 | #if USE_OPENMP |
---|
956 | #pragma omp parallel |
---|
957 | { |
---|
958 | #pragma omp for |
---|
959 | #endif |
---|
960 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
961 | { |
---|
962 | size_t x = i / YMAX; |
---|
963 | size_t y = i % YMAX; |
---|
964 | |
---|
965 | #if USE_OPENMP |
---|
966 | #pragma omp critical |
---|
967 | { |
---|
968 | #endif |
---|
969 | std::cout << std::endl; |
---|
970 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
971 | std::cout << std::endl; |
---|
972 | |
---|
973 | std::ostringstream sc; |
---|
974 | sc << "cluster_" << x << "_" << y; |
---|
975 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
976 | vci_param_ext, |
---|
977 | dspin_int_cmd_width, |
---|
978 | dspin_int_rsp_width, |
---|
979 | dspin_ram_cmd_width, |
---|
980 | dspin_ram_rsp_width> |
---|
981 | ( |
---|
982 | sc.str().c_str(), |
---|
983 | NB_PROCS_MAX, |
---|
984 | NB_DMA_CHANNELS, |
---|
985 | x, |
---|
986 | y, |
---|
987 | XMAX, |
---|
988 | YMAX, |
---|
989 | |
---|
990 | maptab_int, |
---|
991 | maptab_ram, |
---|
992 | maptab_iox, |
---|
993 | |
---|
994 | x_width, |
---|
995 | y_width, |
---|
996 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
997 | |
---|
998 | INT_MEMC_TGT_ID, |
---|
999 | INT_XICU_TGT_ID, |
---|
1000 | INT_MDMA_TGT_ID, |
---|
1001 | INT_IOBX_TGT_ID, |
---|
1002 | |
---|
1003 | INT_PROC_INI_ID, |
---|
1004 | INT_MDMA_INI_ID, |
---|
1005 | INT_IOBX_INI_ID, |
---|
1006 | |
---|
1007 | RAM_XRAM_TGT_ID, |
---|
1008 | |
---|
1009 | RAM_MEMC_INI_ID, |
---|
1010 | RAM_MEMC_INI_ID, |
---|
1011 | |
---|
1012 | MEMC_WAYS, |
---|
1013 | MEMC_SETS, |
---|
1014 | L1_IWAYS, |
---|
1015 | L1_ISETS, |
---|
1016 | L1_DWAYS, |
---|
1017 | L1_DSETS, |
---|
1018 | XRAM_LATENCY, |
---|
1019 | |
---|
1020 | loader, |
---|
1021 | |
---|
1022 | frozen_cycles, |
---|
1023 | debug_from, |
---|
1024 | debug_ok and (cluster(x,y) == debug_memc_id), |
---|
1025 | debug_ok and (cluster(x,y) == debug_proc_id), |
---|
1026 | debug_ok and debug_iob |
---|
1027 | ); |
---|
1028 | |
---|
1029 | #if USE_OPENMP |
---|
1030 | } // end critical |
---|
1031 | #endif |
---|
1032 | } // end for |
---|
1033 | #if USE_OPENMP |
---|
1034 | } |
---|
1035 | #endif |
---|
1036 | |
---|
1037 | std::cout << std::endl; |
---|
1038 | |
---|
1039 | /////////////////////////////////////////////////////////////////////////////// |
---|
1040 | // Net-list |
---|
1041 | /////////////////////////////////////////////////////////////////////////////// |
---|
1042 | |
---|
1043 | // IOX network connexion |
---|
1044 | iox_network->p_clk (signal_clk); |
---|
1045 | iox_network->p_resetn (signal_resetn); |
---|
1046 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
1047 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
1048 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
1049 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
1050 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
1051 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
1052 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
1053 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
1054 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
1055 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
---|
1056 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
1057 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
1058 | |
---|
1059 | // BDEV connexion |
---|
1060 | iox_bdev->p_clk (signal_clk); |
---|
1061 | iox_bdev->p_resetn (signal_resetn); |
---|
1062 | iox_bdev->p_irq (signal_irq_bdev); |
---|
1063 | iox_bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
1064 | iox_bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
1065 | |
---|
1066 | std::cout << " - BDEV connected" << std::endl; |
---|
1067 | |
---|
1068 | // FBUF connexion |
---|
1069 | iox_fbuf->p_clk (signal_clk); |
---|
1070 | iox_fbuf->p_resetn (signal_resetn); |
---|
1071 | iox_fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
1072 | |
---|
1073 | std::cout << " - FBUF connected" << std::endl; |
---|
1074 | |
---|
1075 | // MNIC connexion |
---|
1076 | iox_mnic->p_clk (signal_clk); |
---|
1077 | iox_mnic->p_resetn (signal_resetn); |
---|
1078 | iox_mnic->p_vci (signal_vci_tgt_mnic); |
---|
1079 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
1080 | { |
---|
1081 | iox_mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
1082 | iox_mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
1083 | } |
---|
1084 | |
---|
1085 | std::cout << " - MNIC connected" << std::endl; |
---|
1086 | |
---|
1087 | // BROM connexion |
---|
1088 | iox_brom->p_clk (signal_clk); |
---|
1089 | iox_brom->p_resetn (signal_resetn); |
---|
1090 | iox_brom->p_vci (signal_vci_tgt_brom); |
---|
1091 | |
---|
1092 | std::cout << " - BROM connected" << std::endl; |
---|
1093 | |
---|
1094 | // MTTY connexion |
---|
1095 | iox_mtty->p_clk (signal_clk); |
---|
1096 | iox_mtty->p_resetn (signal_resetn); |
---|
1097 | iox_mtty->p_vci (signal_vci_tgt_mtty); |
---|
1098 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
1099 | { |
---|
1100 | iox_mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
1101 | } |
---|
1102 | |
---|
1103 | std::cout << " - MTTY connected" << std::endl; |
---|
1104 | |
---|
1105 | // CDMA connexion |
---|
1106 | iox_cdma->p_clk (signal_clk); |
---|
1107 | iox_cdma->p_resetn (signal_resetn); |
---|
1108 | iox_cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
1109 | iox_cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
1110 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) |
---|
1111 | { |
---|
1112 | iox_cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
1113 | } |
---|
1114 | |
---|
1115 | std::cout << " - CDMA connected" << std::endl; |
---|
1116 | |
---|
1117 | // IRQ connexions (for cluster_iob0 only) |
---|
1118 | size_t mx = 16 + NB_TTY_CHANNELS; |
---|
1119 | for ( size_t n=0 ; n<32 ; n++ ) |
---|
1120 | { |
---|
1121 | if ( n < 8 ) clusters[0][0]->p_irq[n]->bind (signal_unused_irq[n]); |
---|
1122 | else if ( n < 10 ) clusters[0][0]->p_irq[n]->bind (signal_irq_mnic_rx[n-8]); |
---|
1123 | else if ( n < 12 ) clusters[0][0]->p_irq[n]->bind (signal_irq_mnic_tx[n-10]); |
---|
1124 | else if ( n < 16 ) clusters[0][0]->p_irq[n]->bind (signal_irq_cdma[n-12]); |
---|
1125 | else if ( n < mx ) clusters[0][0]->p_irq[n]->bind (signal_irq_mtty[n-16]); |
---|
1126 | else if ( n < 31 ) clusters[0][0]->p_irq[n]->bind (signal_unused_irq[n]); |
---|
1127 | else clusters[0][0]->p_irq[n]->bind (signal_irq_bdev); |
---|
1128 | } |
---|
1129 | |
---|
1130 | // IOB0 cluster connexion to IOX network |
---|
1131 | clusters[0][0]->p_vci_iox_ini->bind (signal_vci_ini_iob0); |
---|
1132 | clusters[0][0]->p_vci_iox_tgt->bind (signal_vci_tgt_iob0); |
---|
1133 | |
---|
1134 | // IOB1 cluster connexion to IOX network |
---|
1135 | clusters[XMAX-1][YMAX-1]->p_vci_iox_ini->bind (signal_vci_ini_iob1); |
---|
1136 | clusters[XMAX-1][YMAX-1]->p_vci_iox_tgt->bind (signal_vci_tgt_iob1); |
---|
1137 | |
---|
1138 | // All clusters Clock & RESET connexions |
---|
1139 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
1140 | { |
---|
1141 | for (size_t y = 0; y < YMAX; y++) |
---|
1142 | { |
---|
1143 | clusters[x][y]->p_clk (signal_clk); |
---|
1144 | clusters[x][y]->p_resetn (signal_resetn); |
---|
1145 | } |
---|
1146 | } |
---|
1147 | |
---|
1148 | // Inter Clusters horizontal connections |
---|
1149 | if (XMAX > 1) |
---|
1150 | { |
---|
1151 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
1152 | { |
---|
1153 | for (size_t y = 0; y < YMAX; y++) |
---|
1154 | { |
---|
1155 | for (size_t k = 0; k < 3; k++) |
---|
1156 | { |
---|
1157 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
1158 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
1159 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
1160 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
1161 | } |
---|
1162 | |
---|
1163 | for (size_t k = 0; k < 2; k++) |
---|
1164 | { |
---|
1165 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
1166 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
1167 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
1168 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
1169 | } |
---|
1170 | |
---|
1171 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1172 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
1173 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1174 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
1175 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1176 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
1177 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1178 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
1179 | } |
---|
1180 | } |
---|
1181 | } |
---|
1182 | |
---|
1183 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
1184 | |
---|
1185 | // Inter Clusters vertical connections |
---|
1186 | if (YMAX > 1) |
---|
1187 | { |
---|
1188 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
1189 | { |
---|
1190 | for (size_t x = 0; x < XMAX; x++) |
---|
1191 | { |
---|
1192 | for (size_t k = 0; k < 3; k++) |
---|
1193 | { |
---|
1194 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
1195 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
1196 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
1197 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
1198 | } |
---|
1199 | |
---|
1200 | for (size_t k = 0; k < 2; k++) |
---|
1201 | { |
---|
1202 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
1203 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
1204 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
1205 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
1206 | } |
---|
1207 | |
---|
1208 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1209 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
1210 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1211 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
1212 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1213 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
1214 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1215 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
1216 | } |
---|
1217 | } |
---|
1218 | } |
---|
1219 | |
---|
1220 | std::cout << "Vertical connections established" << std::endl; |
---|
1221 | |
---|
1222 | // East & West boundary cluster connections |
---|
1223 | for (size_t y = 0; y < YMAX; y++) |
---|
1224 | { |
---|
1225 | for (size_t k = 0; k < 3; k++) |
---|
1226 | { |
---|
1227 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
1228 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
1229 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); |
---|
1230 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); |
---|
1231 | } |
---|
1232 | |
---|
1233 | for (size_t k = 0; k < 2; k++) |
---|
1234 | { |
---|
1235 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
1236 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
1237 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); |
---|
1238 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); |
---|
1239 | } |
---|
1240 | |
---|
1241 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
1242 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
1243 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
1244 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
1245 | |
---|
1246 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
1247 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
1248 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
1249 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
1250 | } |
---|
1251 | |
---|
1252 | std::cout << "East & West boundaries established" << std::endl; |
---|
1253 | |
---|
1254 | // North & South boundary clusters connections |
---|
1255 | for (size_t x = 0; x < XMAX; x++) |
---|
1256 | { |
---|
1257 | for (size_t k = 0; k < 3; k++) |
---|
1258 | { |
---|
1259 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
1260 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
1261 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); |
---|
1262 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); |
---|
1263 | } |
---|
1264 | |
---|
1265 | for (size_t k = 0; k < 2; k++) |
---|
1266 | { |
---|
1267 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
1268 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
1269 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); |
---|
1270 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); |
---|
1271 | } |
---|
1272 | |
---|
1273 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
1274 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
1275 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
1276 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
1277 | |
---|
1278 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
1279 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
1280 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
1281 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
1282 | } |
---|
1283 | |
---|
1284 | std::cout << "North & South boundaries established" << std::endl; |
---|
1285 | |
---|
1286 | //////////////////////////////////////////////////////// |
---|
1287 | // Simulation |
---|
1288 | /////////////////////////////////////////////////////// |
---|
1289 | |
---|
1290 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
1291 | signal_resetn = false; |
---|
1292 | |
---|
1293 | // network boundaries signals |
---|
1294 | for (size_t x = 0; x < XMAX ; x++) |
---|
1295 | { |
---|
1296 | for (size_t y = 0; y < YMAX ; y++) |
---|
1297 | { |
---|
1298 | for (size_t a = 0; a < 4; a++) |
---|
1299 | { |
---|
1300 | for (size_t k = 0; k < 3; k++) |
---|
1301 | { |
---|
1302 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
1303 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
1304 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
1305 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
1306 | } |
---|
1307 | |
---|
1308 | for (size_t k = 0; k < 2; k++) |
---|
1309 | { |
---|
1310 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
1311 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
1312 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
1313 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
1314 | } |
---|
1315 | |
---|
1316 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
1317 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
1318 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
1319 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
1320 | |
---|
1321 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
1322 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
1323 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
1324 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
1325 | } |
---|
1326 | } |
---|
1327 | } |
---|
1328 | |
---|
1329 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1330 | signal_resetn = true; |
---|
1331 | |
---|
1332 | for (size_t n = 1; n < ncycles; n++) |
---|
1333 | { |
---|
1334 | // Monitor a specific address for L1 & L2 caches |
---|
1335 | // clusters[1][0]->proc[0]->cache_monitor(0x4000ULL); |
---|
1336 | // clusters[0][0]->memc->cache_monitor( 0x25000ULL); |
---|
1337 | |
---|
1338 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
1339 | { |
---|
1340 | std::cout << "****************** cycle " << std::dec << n ; |
---|
1341 | std::cout << " ************************************************" << std::endl; |
---|
1342 | |
---|
1343 | // trace proc[debug_proc_id] |
---|
1344 | if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX ) |
---|
1345 | { |
---|
1346 | |
---|
1347 | size_t l = debug_proc_id % NB_PROCS_MAX ; |
---|
1348 | size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; |
---|
1349 | size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; |
---|
1350 | |
---|
1351 | clusters[x][y]->proc[l]->print_trace(1); |
---|
1352 | |
---|
1353 | std::ostringstream proc_signame; |
---|
1354 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
1355 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
1356 | |
---|
1357 | std::ostringstream p2m_signame; |
---|
1358 | p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; |
---|
1359 | clusters[x][y]->signal_int_dspin_p2m_proc[l].print_trace(p2m_signame.str()); |
---|
1360 | |
---|
1361 | std::ostringstream m2p_signame; |
---|
1362 | m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; |
---|
1363 | clusters[x][y]->signal_int_dspin_m2p_proc[l].print_trace(m2p_signame.str()); |
---|
1364 | |
---|
1365 | // std::ostringstream p_cmd_signame; |
---|
1366 | // p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; |
---|
1367 | // clusters[x][y]->signal_int_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); |
---|
1368 | |
---|
1369 | // std::ostringstream p_rsp_signame; |
---|
1370 | // p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; |
---|
1371 | // clusters[x][y]->signal_int_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); |
---|
1372 | |
---|
1373 | // trace INT routers and xbar in a given cluster |
---|
1374 | // clusters[x][y]->int_xbar_m2p_c->print_trace(); |
---|
1375 | // clusters[x][y]->int_router_cmd->print_trace(1); |
---|
1376 | // clusters[x][y]->int_xbar_rsp_d->print_trace(); |
---|
1377 | // clusters[x][y]->int_xbar_cmd_d->print_trace(); |
---|
1378 | // clusters[x][y]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); |
---|
1379 | // clusters[x][y]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); |
---|
1380 | // clusters[x][y]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); |
---|
1381 | // clusters[x][y]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); |
---|
1382 | } |
---|
1383 | |
---|
1384 | // trace memc[debug_memc_id] |
---|
1385 | if ( debug_memc_id < XMAX*YMAX ) |
---|
1386 | { |
---|
1387 | size_t x = debug_memc_id / YMAX; |
---|
1388 | size_t y = debug_memc_id % YMAX; |
---|
1389 | |
---|
1390 | clusters[x][y]->memc->print_trace(); |
---|
1391 | |
---|
1392 | std::ostringstream smemc_tgt; |
---|
1393 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
1394 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
1395 | |
---|
1396 | std::ostringstream smemc_ini; |
---|
1397 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
1398 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
1399 | |
---|
1400 | // clusters[x][y]->ram_router_cmd->print_trace(); |
---|
1401 | // clusters[x][y]->ram_xbar_cmd->print_trace(); |
---|
1402 | |
---|
1403 | // std::ostringstream sg2l; |
---|
1404 | // sg2l << "[SIG]G2L_" << x << "_" << y; |
---|
1405 | // clusters[x][y]->signal_ram_dspin_cmd_g2l.print_trace(sg2l.str()); |
---|
1406 | |
---|
1407 | clusters[x][y]->xram->print_trace(); |
---|
1408 | |
---|
1409 | std::ostringstream sxram_tgt; |
---|
1410 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
1411 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
1412 | |
---|
1413 | std::ostringstream sm2p; |
---|
1414 | sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; |
---|
1415 | clusters[x][y]->signal_int_dspin_m2p_memc.print_trace(sm2p.str()); |
---|
1416 | |
---|
1417 | std::ostringstream sp2m; |
---|
1418 | sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; |
---|
1419 | clusters[x][y]->signal_int_dspin_p2m_memc.print_trace(sp2m.str()); |
---|
1420 | |
---|
1421 | // std::ostringstream m_cmd_signame; |
---|
1422 | // m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; |
---|
1423 | // clusters[x][y]->signal_int_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); |
---|
1424 | |
---|
1425 | // std::ostringstream m_rsp_signame; |
---|
1426 | // m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; |
---|
1427 | // clusters[x][y]->signal_int_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); |
---|
1428 | |
---|
1429 | std::ostringstream siob_ini; |
---|
1430 | siob_ini << "[SIG]IOB_INI_" << x << "_" << y; |
---|
1431 | clusters[x][y]->signal_ram_vci_ini_iobx.print_trace(siob_ini.str()); |
---|
1432 | } |
---|
1433 | |
---|
1434 | // trace components iob |
---|
1435 | if ( debug_iob ) |
---|
1436 | { |
---|
1437 | clusters[0][0]->iob->print_trace(); |
---|
1438 | clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0 INT" ); |
---|
1439 | clusters[0][0]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB0 INT CMD"); |
---|
1440 | clusters[0][0]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB0 INT RSP"); |
---|
1441 | |
---|
1442 | clusters[XMAX-1][YMAX-1]->iob->print_trace(); |
---|
1443 | clusters[XMAX-1][YMAX-1]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB1 INT" ); |
---|
1444 | clusters[XMAX-1][YMAX-1]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB1 INT CMD"); |
---|
1445 | clusters[XMAX-1][YMAX-1]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB1 INT RSP"); |
---|
1446 | } |
---|
1447 | |
---|
1448 | // trace external peripherals |
---|
1449 | iox_network->print_trace(); |
---|
1450 | |
---|
1451 | signal_vci_ini_iob0.print_trace("[SIG]IOB0 INI IOX"); |
---|
1452 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0 TGT IOX"); |
---|
1453 | signal_vci_ini_iob1.print_trace("[SIG]IOB1 INI IOX"); |
---|
1454 | signal_vci_tgt_iob1.print_trace("[SIG]IOB1 TGT IOX"); |
---|
1455 | |
---|
1456 | iox_brom->print_trace(); |
---|
1457 | signal_vci_tgt_brom.print_trace("[SIG]BROM"); |
---|
1458 | |
---|
1459 | // iox_mtty->print_trace(); |
---|
1460 | // signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); |
---|
1461 | |
---|
1462 | // iox_bdev->print_trace(); |
---|
1463 | // signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
1464 | // signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
1465 | |
---|
1466 | // iox_fbuf->print_trace(); |
---|
1467 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
1468 | |
---|
1469 | } |
---|
1470 | |
---|
1471 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
1472 | } |
---|
1473 | return EXIT_SUCCESS; |
---|
1474 | } |
---|
1475 | |
---|
1476 | int sc_main (int argc, char *argv[]) |
---|
1477 | { |
---|
1478 | try { |
---|
1479 | return _main(argc, argv); |
---|
1480 | } catch (std::exception &e) { |
---|
1481 | std::cout << e.what() << std::endl; |
---|
1482 | } catch (...) { |
---|
1483 | std::cout << "Unknown exception occured" << std::endl; |
---|
1484 | throw; |
---|
1485 | } |
---|
1486 | return 1; |
---|
1487 | } |
---|
1488 | |
---|
1489 | |
---|
1490 | // Local Variables: |
---|
1491 | // tab-width: 3 |
---|
1492 | // c-basic-offset: 3 |
---|
1493 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
1494 | // indent-tabs-mode: nil |
---|
1495 | // End: |
---|
1496 | |
---|
1497 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
1498 | |
---|
1499 | |
---|
1500 | |
---|