[450] | 1 | |
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| 2 | # -*- python -*- |
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| 3 | |
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| 4 | Module('caba:tsar_iob_cluster', |
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[693] | 5 | classname = 'soclib::caba::TsarIobCluster', |
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[450] | 6 | |
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[693] | 7 | tmpl_parameters = [ |
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| 8 | parameter.Module('vci_param_int', default = 'caba:vci_param', |
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[450] | 9 | cell_size = parameter.Reference('vci_data_width_int')), |
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[693] | 10 | parameter.Module('vci_param_ext', default = 'caba:vci_param', |
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[450] | 11 | cell_size = parameter.Reference('vci_data_width_ext')), |
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[693] | 12 | parameter.Int('dspin_int_cmd_width'), |
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| 13 | parameter.Int('dspin_int_rsp_width'), |
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| 14 | parameter.Int('dspin_ram_cmd_width'), |
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| 15 | parameter.Int('dspin_ram_rsp_width'), |
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| 16 | ], |
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[450] | 17 | |
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[693] | 18 | header_files = [ |
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[450] | 19 | '../source/include/tsar_iob_cluster.h', |
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| 20 | ], |
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| 21 | |
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[693] | 22 | implementation_files = [ |
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[450] | 23 | '../source/src/tsar_iob_cluster.cpp', |
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| 24 | ], |
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| 25 | |
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[693] | 26 | uses = [ |
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| 27 | Uses('caba:base_module'), |
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| 28 | Uses('common:mapping_table'), |
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| 29 | Uses('common:iss2'), |
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| 30 | Uses('common:elf_file_loader'), |
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[450] | 31 | |
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| 32 | # internal network components |
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[693] | 33 | Uses('caba:vci_cc_vcache_wrapper', |
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[450] | 34 | cell_size = parameter.Reference('vci_data_width_int'), |
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| 35 | dspin_in_width = parameter.Reference('dspin_int_cmd_width'), |
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| 36 | dspin_out_width = parameter.Reference('dspin_int_rsp_width'), |
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| 37 | iss_t = 'common:gdb_iss', |
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| 38 | gdb_iss_t = 'common:mips32el'), |
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| 39 | |
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[693] | 40 | Uses('caba:vci_mem_cache', |
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[836] | 41 | memc_cell_size_int = parameter.Reference('vci_data_width_int'), |
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| 42 | memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), |
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| 43 | memc_dspin_in_width = parameter.Reference('dspin_int_rsp_width'), |
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| 44 | memc_dspin_out_width = parameter.Reference('dspin_int_cmd_width')), |
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[450] | 45 | |
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| 46 | Uses('caba:vci_xicu', |
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| 47 | cell_size = parameter.Reference('vci_data_width_int')), |
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| 48 | |
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[693] | 49 | Uses('caba:vci_multi_dma', |
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[450] | 50 | cell_size = parameter.Reference('vci_data_width_int')), |
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| 51 | |
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[693] | 52 | Uses('caba:vci_local_crossbar', |
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| 53 | cell_size = parameter.Reference('vci_data_width_int')), |
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| 54 | |
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[450] | 55 | Uses('caba:dspin_local_crossbar', |
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| 56 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
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| 57 | |
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| 58 | Uses('caba:dspin_local_crossbar', |
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| 59 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
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| 60 | |
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[718] | 61 | Uses('caba:dspin_local_crossbar', |
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| 62 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
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| 63 | |
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| 64 | Uses('caba:dspin_local_crossbar', |
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| 65 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
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| 66 | |
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[450] | 67 | Uses('caba:vci_dspin_initiator_wrapper', |
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| 68 | cell_size = parameter.Reference('vci_data_width_int'), |
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| 69 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
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| 70 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
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| 71 | |
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| 72 | Uses('caba:vci_dspin_target_wrapper', |
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| 73 | cell_size = parameter.Reference('vci_data_width_int'), |
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| 74 | dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), |
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| 75 | dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), |
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| 76 | |
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| 77 | Uses('caba:virtual_dspin_router', |
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| 78 | flit_width = parameter.Reference('dspin_int_cmd_width')), |
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| 79 | |
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| 80 | Uses('caba:virtual_dspin_router', |
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| 81 | flit_width = parameter.Reference('dspin_int_rsp_width')), |
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| 82 | |
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| 83 | # RAM network components |
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| 84 | Uses('caba:vci_dspin_initiator_wrapper', |
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| 85 | cell_size = parameter.Reference('vci_data_width_ext'), |
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| 86 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
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| 87 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
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| 88 | |
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| 89 | Uses('caba:vci_dspin_target_wrapper', |
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| 90 | cell_size = parameter.Reference('vci_data_width_ext'), |
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| 91 | dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), |
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| 92 | dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), |
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| 93 | |
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[718] | 94 | Uses('caba:dspin_router', |
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[450] | 95 | flit_width = parameter.Reference('dspin_ram_cmd_width')), |
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| 96 | |
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[718] | 97 | Uses('caba:dspin_router', |
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[450] | 98 | flit_width = parameter.Reference('dspin_ram_rsp_width')), |
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| 99 | |
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[693] | 100 | Uses('caba:vci_simple_ram', |
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[450] | 101 | cell_size = parameter.Reference('vci_data_width_ext')), |
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| 102 | |
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| 103 | # IOX network components |
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| 104 | Uses('caba:vci_io_bridge', |
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| 105 | iob_cell_size_int = parameter.Reference('vci_data_width_int'), |
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| 106 | iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), |
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[693] | 107 | ], |
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[450] | 108 | |
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[693] | 109 | ports = [ |
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| 110 | Port('caba:bit_in', 'p_resetn', auto = 'resetn'), |
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| 111 | Port('caba:clock_in', 'p_clk', auto = 'clock'), |
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[450] | 112 | |
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[693] | 113 | Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], |
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[450] | 114 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
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[693] | 115 | Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], |
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[450] | 116 | dspin_data_size = parameter.Reference('dspin_int_cmd_width')), |
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[693] | 117 | Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], |
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[450] | 118 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
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[693] | 119 | Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], |
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[450] | 120 | dspin_data_size = parameter.Reference('dspin_int_rsp_width')), |
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| 121 | |
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[693] | 122 | Port('caba:dspin_output', 'p_ram_cmd_out', [4], |
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[450] | 123 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
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[693] | 124 | Port('caba:dspin_input', 'p_ram_cmd_in', [4], |
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[450] | 125 | dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), |
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[693] | 126 | Port('caba:dspin_output', 'p_ram_rsp_out', [4], |
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[450] | 127 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
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[693] | 128 | Port('caba:dspin_input', 'p_ram_rsp_in', [4], |
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[450] | 129 | dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), |
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[693] | 130 | ], |
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[450] | 131 | ) |
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| 132 | |
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| 133 | |
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