[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.h |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 10 | #define SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 11 | |
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| 12 | #include <systemc> |
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| 13 | #include <sys/time.h> |
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| 14 | #include <iostream> |
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| 15 | #include <sstream> |
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| 16 | #include <cstdlib> |
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| 17 | #include <cstdarg> |
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| 18 | |
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| 19 | #include "gdbserver.h" |
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| 20 | #include "mapping_table.h" |
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| 21 | #include "mips32.h" |
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| 22 | #include "vci_simple_ram.h" |
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| 23 | #include "vci_xicu.h" |
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[693] | 24 | #include "vci_local_crossbar.h" |
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[450] | 25 | #include "dspin_local_crossbar.h" |
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| 26 | #include "vci_dspin_initiator_wrapper.h" |
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| 27 | #include "vci_dspin_target_wrapper.h" |
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[718] | 28 | #include "dspin_router.h" |
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[1051] | 29 | #include "vci_multi_dma.h" |
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[450] | 30 | #include "vci_mem_cache.h" |
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| 31 | #include "vci_cc_vcache_wrapper.h" |
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| 32 | #include "vci_io_bridge.h" |
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| 33 | |
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[693] | 34 | namespace soclib { namespace caba { |
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[450] | 35 | |
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| 36 | /////////////////////////////////////////////////////////////////////////// |
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| 37 | template<typename vci_param_int, |
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| 38 | typename vci_param_ext, |
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| 39 | size_t dspin_int_cmd_width, |
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| 40 | size_t dspin_int_rsp_width, |
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| 41 | size_t dspin_ram_cmd_width, |
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| 42 | size_t dspin_ram_rsp_width> |
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| 43 | class TsarIobCluster |
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| 44 | /////////////////////////////////////////////////////////////////////////// |
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| 45 | : public soclib::caba::BaseModule |
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| 46 | { |
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| 47 | |
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| 48 | public: |
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| 49 | |
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[693] | 50 | // Ports |
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| 51 | sc_in<bool> p_clk; |
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| 52 | sc_in<bool> p_resetn; |
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[450] | 53 | |
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[550] | 54 | // Thes two ports are used to connect IOB to IOX nework in top cell |
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| 55 | soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; |
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| 56 | soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; |
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[450] | 57 | |
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[550] | 58 | // These arrays of ports are used to connect the INT & RAM networks in top cell |
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[1002] | 59 | soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_cmd_out; |
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| 60 | soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_cmd_in; |
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| 61 | soclib::caba::DspinOutput<dspin_int_rsp_width>* p_dspin_int_rsp_out; |
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| 62 | soclib::caba::DspinInput<dspin_int_rsp_width>* p_dspin_int_rsp_in; |
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| 63 | soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_m2p_out; |
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| 64 | soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_m2p_in; |
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| 65 | soclib::caba::DspinOutput<dspin_int_rsp_width>* p_dspin_int_p2m_out; |
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| 66 | soclib::caba::DspinInput<dspin_int_rsp_width>* p_dspin_int_p2m_in; |
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| 67 | soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_cla_out; |
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| 68 | soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_cla_in; |
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[450] | 69 | |
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[693] | 70 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; |
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| 71 | soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; |
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[450] | 72 | soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; |
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| 73 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; |
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| 74 | |
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| 75 | // interrupt signals |
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[693] | 76 | sc_signal<bool> signal_false; |
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[959] | 77 | sc_signal<bool> signal_proc_it[32]; |
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[1051] | 78 | sc_signal<bool> signal_irq_mdma[8]; |
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[693] | 79 | sc_signal<bool> signal_irq_memc; |
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| 80 | |
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| 81 | // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars |
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| 82 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; |
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| 83 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; |
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[1002] | 84 | |
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| 85 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; |
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| 86 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; |
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| 87 | |
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[693] | 88 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; |
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| 89 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; |
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[1002] | 90 | |
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[693] | 91 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; |
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| 92 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; |
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[450] | 93 | |
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[1002] | 94 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_l2g_c; |
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| 95 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_g2l_c; |
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| 96 | |
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[693] | 97 | // INT network VCI signals between VCI components and VCI local crossbar |
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| 98 | VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; |
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[1051] | 99 | VciSignals<vci_param_int> signal_int_vci_ini_mdma; |
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[693] | 100 | VciSignals<vci_param_int> signal_int_vci_ini_iobx; |
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[450] | 101 | |
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[693] | 102 | VciSignals<vci_param_int> signal_int_vci_tgt_memc; |
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| 103 | VciSignals<vci_param_int> signal_int_vci_tgt_xicu; |
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[1051] | 104 | VciSignals<vci_param_int> signal_int_vci_tgt_mdma; |
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[693] | 105 | VciSignals<vci_param_int> signal_int_vci_tgt_iobx; |
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[450] | 106 | |
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[693] | 107 | VciSignals<vci_param_int> signal_int_vci_l2g; |
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| 108 | VciSignals<vci_param_int> signal_int_vci_g2l; |
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[450] | 109 | |
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[693] | 110 | // Coherence DSPIN signals between DSPIN local crossbars and CC components |
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| 111 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; |
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[1002] | 112 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_memc; |
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[693] | 113 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; |
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| 114 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; |
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[1002] | 115 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_proc[8]; |
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[693] | 116 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; |
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[450] | 117 | |
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[693] | 118 | // RAM network VCI signals between VCI components and VCI/DSPIN wrappers |
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| 119 | VciSignals<vci_param_ext> signal_ram_vci_ini_memc; |
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| 120 | VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; |
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| 121 | VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; |
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[450] | 122 | |
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[718] | 123 | // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar |
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| 124 | // and routers |
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[693] | 125 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; |
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| 126 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; |
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| 127 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; |
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| 128 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; |
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[718] | 129 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i; |
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| 130 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i; |
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| 131 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar; |
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| 132 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar; |
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| 133 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; |
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| 134 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; |
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[450] | 135 | |
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| 136 | ////////////////////////////////////// |
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| 137 | // Hardwate Components (pointers) |
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| 138 | ////////////////////////////////////// |
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| 139 | VciCcVCacheWrapper<vci_param_int, |
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| 140 | dspin_int_cmd_width, |
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| 141 | dspin_int_rsp_width, |
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| 142 | GdbServer<Mips32ElIss> >* proc[8]; |
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| 143 | |
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| 144 | VciMemCache<vci_param_int, |
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| 145 | vci_param_ext, |
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| 146 | dspin_int_rsp_width, |
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| 147 | dspin_int_cmd_width>* memc; |
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| 148 | |
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| 149 | VciDspinInitiatorWrapper<vci_param_ext, |
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| 150 | dspin_ram_cmd_width, |
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| 151 | dspin_ram_rsp_width>* memc_ram_wi; |
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| 152 | |
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[693] | 153 | VciXicu<vci_param_int>* xicu; |
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[450] | 154 | |
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[1051] | 155 | VciMultiDma<vci_param_int>* mdma; |
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[450] | 156 | |
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[693] | 157 | VciLocalCrossbar<vci_param_int>* int_xbar_d; |
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| 158 | |
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[450] | 159 | VciDspinInitiatorWrapper<vci_param_int, |
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| 160 | dspin_int_cmd_width, |
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[693] | 161 | dspin_int_rsp_width>* int_wi_gate_d; |
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[450] | 162 | |
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| 163 | VciDspinTargetWrapper<vci_param_int, |
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| 164 | dspin_int_cmd_width, |
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[693] | 165 | dspin_int_rsp_width>* int_wt_gate_d; |
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[450] | 166 | |
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| 167 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; |
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| 168 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; |
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[468] | 169 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; |
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[450] | 170 | |
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[1002] | 171 | DspinRouter<dspin_int_cmd_width>* int_router_cmd; |
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| 172 | DspinRouter<dspin_int_rsp_width>* int_router_rsp; |
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| 173 | DspinRouter<dspin_int_cmd_width>* int_router_m2p; |
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| 174 | DspinRouter<dspin_int_rsp_width>* int_router_p2m; |
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| 175 | DspinRouter<dspin_int_cmd_width>* int_router_cla; |
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[450] | 176 | |
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| 177 | VciSimpleRam<vci_param_ext>* xram; |
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| 178 | |
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| 179 | VciDspinTargetWrapper<vci_param_ext, |
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| 180 | dspin_ram_cmd_width, |
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| 181 | dspin_ram_rsp_width>* xram_ram_wt; |
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[693] | 182 | |
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[718] | 183 | DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; |
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| 184 | DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; |
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[450] | 185 | |
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[1050] | 186 | // IO Network Components (not instanciated in all clusters) |
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| 187 | |
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[718] | 188 | DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; |
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| 189 | DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; |
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| 190 | |
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[450] | 191 | VciIoBridge<vci_param_int, |
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| 192 | vci_param_ext>* iob; |
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| 193 | |
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| 194 | VciDspinInitiatorWrapper<vci_param_ext, |
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| 195 | dspin_ram_cmd_width, |
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| 196 | dspin_ram_rsp_width>* iob_ram_wi; |
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[718] | 197 | |
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[450] | 198 | // cluster constructor |
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[693] | 199 | TsarIobCluster( sc_module_name insname, |
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[450] | 200 | size_t nb_procs, |
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| 201 | size_t x, // x coordinate |
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| 202 | size_t y, // y coordinate |
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| 203 | size_t xmax, |
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| 204 | size_t ymax, |
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| 205 | |
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| 206 | const soclib::common::MappingTable &mt_int, |
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| 207 | const soclib::common::MappingTable &mt_ext, |
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| 208 | const soclib::common::MappingTable &mt_iox, |
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| 209 | |
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[959] | 210 | size_t x_width, // x field bits |
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| 211 | size_t y_width, // y field bits |
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| 212 | size_t l_width, // l field bits |
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| 213 | size_t p_width, // p field bits |
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[450] | 214 | |
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[718] | 215 | size_t int_memc_tgt_id, |
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| 216 | size_t int_xicu_tgt_id, |
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[1051] | 217 | size_t int_mdma_tgt_id, |
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[718] | 218 | size_t int_iobx_tgt_id, |
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| 219 | size_t int_proc_ini_id, |
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[1051] | 220 | size_t int_mdma_ini_id, |
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[718] | 221 | size_t int_iobx_ini_id, |
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[450] | 222 | |
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[718] | 223 | size_t ram_xram_tgt_id, |
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| 224 | size_t ram_memc_ini_id, |
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| 225 | size_t ram_iobx_ini_id, |
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[450] | 226 | |
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[718] | 227 | bool is_io, |
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| 228 | size_t iox_iobx_tgt_id, |
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| 229 | size_t iox_iobx_ini_id, |
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[450] | 230 | |
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| 231 | size_t memc_ways, |
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| 232 | size_t memc_sets, |
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| 233 | size_t l1_i_ways, |
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| 234 | size_t l1_i_sets, |
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| 235 | size_t l1_d_ways, |
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[693] | 236 | size_t l1_d_sets, |
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[450] | 237 | size_t xram_latency, |
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[959] | 238 | size_t xcu_nb_hwi, |
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| 239 | size_t xcu_nb_pti, |
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| 240 | size_t xcu_nb_wti, |
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| 241 | size_t xcu_nb_irq, |
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[450] | 242 | |
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[972] | 243 | size_t coproc_type, |
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| 244 | |
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[959] | 245 | const Loader &loader, // loader for XRAM |
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[450] | 246 | |
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| 247 | uint32_t frozen_cycles, |
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[1030] | 248 | bool debug_ok, |
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| 249 | uint32_t debug_start_cycle, |
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| 250 | uint32_t debug_proc_id, |
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| 251 | uint32_t debug_memc_id, |
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| 252 | bool debug_iob ); |
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[450] | 253 | |
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[718] | 254 | protected: |
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| 255 | |
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| 256 | SC_HAS_PROCESS(TsarIobCluster); |
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| 257 | |
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| 258 | void init(); |
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| 259 | |
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[450] | 260 | }; |
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| 261 | |
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| 262 | }} |
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| 263 | |
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| 264 | #endif |
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[718] | 265 | |
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| 266 | // Local Variables: |
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| 267 | // tab-width: 3 |
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| 268 | // c-basic-offset: 3 |
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| 269 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 270 | // indent-tabs-mode: nil |
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| 271 | // End: |
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| 272 | |
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| 273 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 274 | // |
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