[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.h |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 10 | #define SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 11 | |
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| 12 | #include <systemc> |
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| 13 | #include <sys/time.h> |
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| 14 | #include <iostream> |
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| 15 | #include <sstream> |
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| 16 | #include <cstdlib> |
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| 17 | #include <cstdarg> |
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| 18 | |
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| 19 | #include "gdbserver.h" |
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| 20 | #include "mapping_table.h" |
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| 21 | #include "mips32.h" |
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| 22 | #include "vci_simple_ram.h" |
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| 23 | #include "vci_xicu.h" |
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[693] | 24 | #include "vci_local_crossbar.h" |
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[450] | 25 | #include "dspin_local_crossbar.h" |
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| 26 | #include "vci_dspin_initiator_wrapper.h" |
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| 27 | #include "vci_dspin_target_wrapper.h" |
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[550] | 28 | #include "dspin_router_tsar.h" |
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[450] | 29 | #include "virtual_dspin_router.h" |
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| 30 | #include "vci_multi_dma.h" |
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| 31 | #include "vci_mem_cache.h" |
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| 32 | #include "vci_cc_vcache_wrapper.h" |
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| 33 | #include "vci_io_bridge.h" |
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| 34 | |
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[693] | 35 | namespace soclib { namespace caba { |
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[450] | 36 | |
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| 37 | /////////////////////////////////////////////////////////////////////////// |
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| 38 | template<typename vci_param_int, |
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| 39 | typename vci_param_ext, |
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| 40 | size_t dspin_int_cmd_width, |
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| 41 | size_t dspin_int_rsp_width, |
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| 42 | size_t dspin_ram_cmd_width, |
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| 43 | size_t dspin_ram_rsp_width> |
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| 44 | class TsarIobCluster |
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| 45 | /////////////////////////////////////////////////////////////////////////// |
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| 46 | : public soclib::caba::BaseModule |
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| 47 | { |
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| 48 | |
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| 49 | public: |
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| 50 | |
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[693] | 51 | // Ports |
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| 52 | sc_in<bool> p_clk; |
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| 53 | sc_in<bool> p_resetn; |
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[450] | 54 | |
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[550] | 55 | // Thes two ports are used to connect IOB to IOX nework in top cell |
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| 56 | soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; |
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| 57 | soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; |
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[450] | 58 | |
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[550] | 59 | // These ports are used to connect IOB to RAM network in top cell |
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| 60 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; |
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| 61 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; |
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[450] | 62 | |
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[550] | 63 | // These arrays of ports are used to connect the INT & RAM networks in top cell |
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[693] | 64 | soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; |
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| 65 | soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; |
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[450] | 66 | soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; |
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| 67 | soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; |
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| 68 | |
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[693] | 69 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; |
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| 70 | soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; |
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[450] | 71 | soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; |
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| 72 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; |
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| 73 | |
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| 74 | // interrupt signals |
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[693] | 75 | sc_signal<bool> signal_false; |
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| 76 | sc_signal<bool> signal_proc_it[8]; |
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| 77 | sc_signal<bool> signal_irq_mdma[8]; |
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| 78 | sc_signal<bool> signal_irq_memc; |
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| 79 | |
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| 80 | // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars |
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| 81 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; |
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| 82 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; |
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| 83 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; |
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| 84 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; |
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| 85 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; |
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| 86 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; |
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| 87 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; |
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| 88 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; |
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| 89 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; |
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| 90 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; |
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[450] | 91 | |
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[693] | 92 | // INT network VCI signals between VCI components and VCI local crossbar |
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| 93 | VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; |
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| 94 | VciSignals<vci_param_int> signal_int_vci_ini_mdma; |
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| 95 | VciSignals<vci_param_int> signal_int_vci_ini_iobx; |
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[450] | 96 | |
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[693] | 97 | VciSignals<vci_param_int> signal_int_vci_tgt_memc; |
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| 98 | VciSignals<vci_param_int> signal_int_vci_tgt_xicu; |
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| 99 | VciSignals<vci_param_int> signal_int_vci_tgt_mdma; |
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| 100 | VciSignals<vci_param_int> signal_int_vci_tgt_iobx; |
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[450] | 101 | |
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[693] | 102 | VciSignals<vci_param_int> signal_int_vci_l2g; |
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| 103 | VciSignals<vci_param_int> signal_int_vci_g2l; |
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[450] | 104 | |
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[693] | 105 | // Coherence DSPIN signals between DSPIN local crossbars and CC components |
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| 106 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; |
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| 107 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; |
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| 108 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; |
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| 109 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; |
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| 110 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; |
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| 111 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; |
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[450] | 112 | |
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[693] | 113 | // RAM network VCI signals between VCI components and VCI/DSPIN wrappers |
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| 114 | VciSignals<vci_param_ext> signal_ram_vci_ini_memc; |
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| 115 | VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; |
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| 116 | VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; |
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[450] | 117 | |
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[550] | 118 | // RAM network DSPIN signals between VCI/DSPIN wrappers and routers |
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[693] | 119 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; |
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| 120 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; |
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| 121 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; |
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| 122 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; |
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[450] | 123 | |
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| 124 | ////////////////////////////////////// |
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| 125 | // Hardwate Components (pointers) |
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| 126 | ////////////////////////////////////// |
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| 127 | VciCcVCacheWrapper<vci_param_int, |
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| 128 | dspin_int_cmd_width, |
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| 129 | dspin_int_rsp_width, |
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| 130 | GdbServer<Mips32ElIss> >* proc[8]; |
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| 131 | |
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| 132 | VciMemCache<vci_param_int, |
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| 133 | vci_param_ext, |
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| 134 | dspin_int_rsp_width, |
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| 135 | dspin_int_cmd_width>* memc; |
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| 136 | |
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| 137 | VciDspinInitiatorWrapper<vci_param_ext, |
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| 138 | dspin_ram_cmd_width, |
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| 139 | dspin_ram_rsp_width>* memc_ram_wi; |
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| 140 | |
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[693] | 141 | VciXicu<vci_param_int>* xicu; |
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[450] | 142 | |
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| 143 | VciMultiDma<vci_param_int>* mdma; |
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| 144 | |
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[693] | 145 | VciLocalCrossbar<vci_param_int>* int_xbar_d; |
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| 146 | |
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[450] | 147 | VciDspinInitiatorWrapper<vci_param_int, |
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| 148 | dspin_int_cmd_width, |
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[693] | 149 | dspin_int_rsp_width>* int_wi_gate_d; |
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[450] | 150 | |
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| 151 | VciDspinTargetWrapper<vci_param_int, |
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| 152 | dspin_int_cmd_width, |
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[693] | 153 | dspin_int_rsp_width>* int_wt_gate_d; |
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[450] | 154 | |
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| 155 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; |
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| 156 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; |
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[468] | 157 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; |
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[450] | 158 | |
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[693] | 159 | VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; |
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[450] | 160 | VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; |
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| 161 | |
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| 162 | VciSimpleRam<vci_param_ext>* xram; |
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| 163 | |
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| 164 | VciDspinTargetWrapper<vci_param_ext, |
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| 165 | dspin_ram_cmd_width, |
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| 166 | dspin_ram_rsp_width>* xram_ram_wt; |
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[693] | 167 | |
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| 168 | DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; |
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[550] | 169 | DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; |
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[450] | 170 | |
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[693] | 171 | // IO Network Components (not instanciated in all clusters) |
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[450] | 172 | |
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| 173 | VciIoBridge<vci_param_int, |
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| 174 | vci_param_ext>* iob; |
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| 175 | |
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| 176 | VciDspinInitiatorWrapper<vci_param_ext, |
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| 177 | dspin_ram_cmd_width, |
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| 178 | dspin_ram_rsp_width>* iob_ram_wi; |
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[693] | 179 | |
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[450] | 180 | // cluster constructor |
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[693] | 181 | TsarIobCluster( sc_module_name insname, |
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[450] | 182 | size_t nb_procs, |
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| 183 | size_t nb_dmas, |
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| 184 | size_t x, // x coordinate |
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| 185 | size_t y, // y coordinate |
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| 186 | size_t xmax, |
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| 187 | size_t ymax, |
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| 188 | |
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| 189 | const soclib::common::MappingTable &mt_int, |
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| 190 | const soclib::common::MappingTable &mt_ext, |
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| 191 | const soclib::common::MappingTable &mt_iox, |
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| 192 | |
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[693] | 193 | size_t x_width, // x field bits |
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| 194 | size_t y_width, // y field bits |
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| 195 | size_t l_width, // l field bits |
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[450] | 196 | |
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[693] | 197 | size_t int_memc_tgtid, |
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| 198 | size_t int_xicu_tgtid, |
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| 199 | size_t int_mdma_tgtid, |
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| 200 | size_t int_iobx_tgtid, |
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[450] | 201 | |
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| 202 | size_t int_proc_srcid, |
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| 203 | size_t int_mdma_srcid, |
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| 204 | size_t int_iobx_srcid, |
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| 205 | |
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| 206 | size_t ext_xram_tgtid, |
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| 207 | |
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| 208 | size_t ext_memc_srcid, |
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| 209 | size_t ext_iobx_srcid, |
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| 210 | |
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| 211 | size_t memc_ways, |
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| 212 | size_t memc_sets, |
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| 213 | size_t l1_i_ways, |
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| 214 | size_t l1_i_sets, |
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| 215 | size_t l1_d_ways, |
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[693] | 216 | size_t l1_d_sets, |
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[450] | 217 | size_t xram_latency, |
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[714] | 218 | size_t xcu_nb_inputs, |
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[450] | 219 | |
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| 220 | const Loader &loader, // loader for XRAM |
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| 221 | |
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| 222 | uint32_t frozen_cycles, |
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| 223 | uint32_t start_debug_cycle, |
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| 224 | bool memc_debug_ok, |
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| 225 | bool proc_debug_ok, |
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| 226 | bool iob0_debug_ok ); |
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| 227 | |
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| 228 | }; |
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| 229 | |
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| 230 | }} |
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| 231 | |
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| 232 | #endif |
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