[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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[802] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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[802] | 12 | // - 2 dspin_local_crossbar for commands and responses. |
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[450] | 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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[718] | 17 | #define tmpl(x) \ |
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| 18 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 19 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 20 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 21 | x TsarIobCluster<\ |
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| 22 | vci_param_int , vci_param_ext,\ |
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| 23 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 24 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 25 | |
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[450] | 26 | namespace soclib { namespace caba { |
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| 27 | |
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[972] | 28 | ///////////////////////////////////////////////////////////////////////////// |
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[718] | 29 | tmpl(/**/)::TsarIobCluster( |
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[972] | 30 | ///////////////////////////////////////////////////////////////////////////// |
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[450] | 31 | sc_module_name insname, |
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| 32 | size_t nb_procs, |
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| 33 | size_t x_id, |
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| 34 | size_t y_id, |
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| 35 | size_t xmax, |
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| 36 | size_t ymax, |
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| 37 | |
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| 38 | const soclib::common::MappingTable &mt_int, |
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[802] | 39 | const soclib::common::MappingTable &mt_ram, |
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| 40 | const soclib::common::MappingTable &mt_iox, |
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[450] | 41 | |
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| 42 | size_t x_width, |
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| 43 | size_t y_width, |
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| 44 | size_t l_width, |
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[802] | 45 | size_t p_width, |
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[450] | 46 | |
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[718] | 47 | size_t int_memc_tgt_id, // local index |
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| 48 | size_t int_xicu_tgt_id, // local index |
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[1051] | 49 | size_t int_mdma_tgt_id, // local index |
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[718] | 50 | size_t int_iobx_tgt_id, // local index |
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[450] | 51 | |
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[718] | 52 | size_t int_proc_ini_id, // local index |
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[1051] | 53 | size_t int_mdma_ini_id, // local index |
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[718] | 54 | size_t int_iobx_ini_id, // local index |
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[450] | 55 | |
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[718] | 56 | size_t ram_xram_tgt_id, // local index |
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| 57 | size_t ram_memc_ini_id, // local index |
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| 58 | size_t ram_iobx_ini_id, // local index |
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[450] | 59 | |
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[1051] | 60 | bool is_io, // is IO cluster ( |
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[718] | 61 | size_t iox_iobx_tgt_id, // local_index |
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| 62 | size_t iox_iobx_ini_id, // local index |
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[450] | 63 | |
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| 64 | size_t memc_ways, |
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| 65 | size_t memc_sets, |
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| 66 | size_t l1_i_ways, |
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| 67 | size_t l1_i_sets, |
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| 68 | size_t l1_d_ways, |
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| 69 | size_t l1_d_sets, |
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| 70 | size_t xram_latency, |
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[959] | 71 | size_t xcu_nb_hwi, |
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| 72 | size_t xcu_nb_pti, |
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| 73 | size_t xcu_nb_wti, |
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| 74 | size_t xcu_nb_out, |
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[450] | 75 | |
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[972] | 76 | size_t coproc_type, |
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| 77 | |
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[450] | 78 | const Loader &loader, |
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| 79 | |
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| 80 | uint32_t frozen_cycles, |
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[1030] | 81 | bool debug_ok, |
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[450] | 82 | uint32_t debug_start_cycle, |
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[1030] | 83 | uint32_t debug_proc_id, |
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| 84 | uint32_t debug_memc_id, |
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| 85 | bool debug_iob ) |
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[450] | 86 | : soclib::caba::BaseModule(insname), |
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| 87 | p_clk("clk"), |
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| 88 | p_resetn("resetn") |
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| 89 | { |
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[972] | 90 | assert( (x_id < xmax) and (y_id < ymax) and |
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| 91 | "Error in tsar_iob_cluster : Illegal cluster coordinates"); |
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[450] | 92 | |
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[607] | 93 | size_t cluster_id = (x_id<<4) + y_id; |
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[450] | 94 | |
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| 95 | // Vectors of DSPIN ports for inter-cluster communications |
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[1002] | 96 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4); |
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| 97 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4); |
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[450] | 98 | |
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[1002] | 99 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4); |
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| 100 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4); |
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| 101 | |
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| 102 | p_dspin_int_m2p_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_m2p_in", 4); |
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| 103 | p_dspin_int_m2p_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_m2p_out", 4); |
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| 104 | |
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| 105 | p_dspin_int_p2m_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_p2m_in", 4); |
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| 106 | p_dspin_int_p2m_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_p2m_out", 4); |
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| 107 | |
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| 108 | p_dspin_int_cla_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cla_in", 4); |
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| 109 | p_dspin_int_cla_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cla_out", 4); |
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| 110 | |
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[450] | 111 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 112 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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[1002] | 113 | |
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[450] | 114 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 115 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 116 | |
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[718] | 117 | // VCI ports from IOB to IOX network (only in IO clusters) |
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| 118 | if ( is_io ) |
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[450] | 119 | { |
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[550] | 120 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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[802] | 121 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[450] | 122 | } |
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| 123 | |
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[1002] | 124 | ////////////////////////////////////////////////////////////////////////////////// |
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[450] | 125 | // Hardware components |
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[1002] | 126 | ////////////////////////////////////////////////////////////////////////////////// |
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[450] | 127 | |
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[1030] | 128 | size_t x_debug; |
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| 129 | size_t y_debug; |
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| 130 | size_t p_debug; |
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| 131 | |
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[1002] | 132 | //////////// PROCS ///////////////////////////////////////////////////////////// |
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[450] | 133 | for (size_t p = 0; p < nb_procs; p++) |
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[802] | 134 | { |
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[450] | 135 | std::ostringstream s_proc; |
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[1030] | 136 | x_debug = (debug_proc_id >> (y_width + p_width)) & ((1<<x_width)-1); |
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| 137 | y_debug = (debug_proc_id >> p_width ) & ((1<<y_width)-1); |
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| 138 | p_debug = (debug_proc_id ) & ((1<<p_width)-1); |
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| 139 | |
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| 140 | |
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[450] | 141 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 142 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 143 | dspin_int_cmd_width, |
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| 144 | dspin_int_rsp_width, |
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| 145 | GdbServer<Mips32ElIss> >( |
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| 146 | s_proc.str().c_str(), |
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[802] | 147 | (cluster_id << p_width) + p, // GLOBAL PROC_ID |
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[450] | 148 | mt_int, // Mapping Table INT network |
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| 149 | IntTab(cluster_id,p), // SRCID |
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| 150 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 151 | 8, // ITLB ways |
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| 152 | 8, // ITLB sets |
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| 153 | 8, // DTLB ways |
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| 154 | 8, // DTLB sets |
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[718] | 155 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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| 156 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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[450] | 157 | 4, // WBUF nlines |
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| 158 | 4, // WBUF nwords |
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| 159 | x_width, |
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| 160 | y_width, |
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| 161 | frozen_cycles, // max frozen cycles |
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| 162 | debug_start_cycle, |
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[1030] | 163 | debug_ok and (x_id == x_debug) and (y_id == y_debug) and (p_debug == p) ); |
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[450] | 164 | } |
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| 165 | |
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[1002] | 166 | //////////// MEMC ///////////////////////////////////////////////////////////// |
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[450] | 167 | std::ostringstream s_memc; |
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| 168 | s_memc << "memc_" << x_id << "_" << y_id; |
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[1030] | 169 | x_debug = (debug_memc_id >> y_width) & ((1<<x_width)-1); |
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| 170 | y_debug = (debug_memc_id ) & ((1<<y_width)-1); |
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[450] | 171 | memc = new VciMemCache<vci_param_int, |
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| 172 | vci_param_ext, |
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| 173 | dspin_int_rsp_width, |
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| 174 | dspin_int_cmd_width>( |
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| 175 | s_memc.str().c_str(), |
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[718] | 176 | mt_int, // Mapping Table INT network |
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| 177 | mt_ram, // Mapping Table RAM network |
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| 178 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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| 179 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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| 180 | x_width, // number of bits for x coordinate |
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| 181 | y_width, // number of bits for y coordinate |
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| 182 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 183 | 3, // MAX NUMBER OF COPIES |
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| 184 | 4096, // HEAP SIZE |
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| 185 | 8, // TRANSACTION TABLE DEPTH |
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| 186 | 8, // UPDATE TABLE DEPTH |
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| 187 | 8, // INVALIDATE TABLE DEPTH |
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[450] | 188 | debug_start_cycle, |
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[1034] | 189 | debug_ok and (x_id == x_debug) and (y_id == y_debug) ); |
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[450] | 190 | |
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| 191 | std::ostringstream s_wi_memc; |
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| 192 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 193 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 194 | dspin_ram_cmd_width, |
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| 195 | dspin_ram_rsp_width>( |
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| 196 | s_wi_memc.str().c_str(), |
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| 197 | x_width + y_width + l_width); |
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| 198 | |
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[1002] | 199 | /////////// XICU ////////////////////////////////////////////////////////////// |
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[450] | 200 | std::ostringstream s_xicu; |
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| 201 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 202 | xicu = new VciXicu<vci_param_int>( |
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| 203 | s_xicu.str().c_str(), |
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[718] | 204 | mt_int, // mapping table INT network |
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| 205 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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[959] | 206 | xcu_nb_pti, // number of timer IRQs |
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| 207 | xcu_nb_hwi, // number of hard IRQs |
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| 208 | xcu_nb_wti, // number of soft IRQs |
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| 209 | xcu_nb_out); // number of output IRQs |
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[450] | 210 | |
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[1051] | 211 | //////////// MDMA ////////////////////////////////////////////////////////////// |
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| 212 | std::ostringstream s_mdma; |
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| 213 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 214 | mdma = new VciMultiDma<vci_param_int>( |
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| 215 | s_mdma.str().c_str(), |
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[450] | 216 | mt_int, |
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[1051] | 217 | IntTab(cluster_id, int_mdma_ini_id), // SRCID |
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| 218 | IntTab(cluster_id, int_mdma_tgt_id), // TGTID |
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| 219 | 64, // burst size |
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| 220 | nb_procs ); // number of channels |
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[450] | 221 | |
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[1002] | 222 | /////////// VCI INT_CMD/RSP LOCAL_XBAR ////////////////////////////////////// |
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[718] | 223 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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| 224 | size_t nb_direct_targets = is_io ? 4 : 3; |
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[450] | 225 | |
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[693] | 226 | std::ostringstream s_int_xbar_d; |
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| 227 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 228 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 229 | s_int_xbar_d.str().c_str(), |
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[450] | 230 | mt_int, // mapping table |
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[693] | 231 | cluster_id, // cluster id |
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| 232 | nb_direct_initiators, // number of local initiators |
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[802] | 233 | nb_direct_targets, // number of local targets |
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[693] | 234 | 0 ); // default target |
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[450] | 235 | |
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[693] | 236 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 237 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 238 | << x_id << "_" << y_id; |
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| 239 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 240 | dspin_int_cmd_width, |
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| 241 | dspin_int_rsp_width>( |
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| 242 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 243 | x_width + y_width + l_width); |
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[450] | 244 | |
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[693] | 245 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 246 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 247 | << x_id << "_" << y_id; |
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| 248 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 249 | dspin_int_cmd_width, |
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| 250 | dspin_int_rsp_width>( |
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| 251 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 252 | x_width + y_width + l_width); |
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| 253 | |
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[1002] | 254 | //////////// DSPIN INT_M2P LOCAL_XBAR //////////////////////////////////////// |
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[450] | 255 | std::ostringstream s_int_xbar_m2p_c; |
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| 256 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 257 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 258 | s_int_xbar_m2p_c.str().c_str(), |
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| 259 | mt_int, // mapping table |
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| 260 | x_id, y_id, // cluster coordinates |
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| 261 | x_width, y_width, l_width, // several dests |
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| 262 | 1, // number of local sources |
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[802] | 263 | nb_procs, // number of local dests |
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| 264 | 2, 2, // fifo depths |
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[450] | 265 | true, // pseudo CMD |
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| 266 | false, // no routing table |
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| 267 | true ); // broacast |
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| 268 | |
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[1002] | 269 | //////////// DSPIN INT_P2M LOCAL_XBAR //////////////////////////////////////// |
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[450] | 270 | std::ostringstream s_int_xbar_p2m_c; |
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| 271 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 272 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 273 | s_int_xbar_p2m_c.str().c_str(), |
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| 274 | mt_int, // mapping table |
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| 275 | x_id, y_id, // cluster coordinates |
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| 276 | x_width, y_width, 0, // only one dest |
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| 277 | nb_procs, // number of local sources |
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| 278 | 1, // number of local dests |
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[802] | 279 | 2, 2, // fifo depths |
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[450] | 280 | false, // pseudo RSP |
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| 281 | false, // no routing table |
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[802] | 282 | false ); // no broacast |
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[450] | 283 | |
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[1002] | 284 | //////////// DSPIN INT_CLA LOCAL_XBAR //////////////////////////////////////// |
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[468] | 285 | std::ostringstream s_int_xbar_clack_c; |
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| 286 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 287 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 288 | s_int_xbar_clack_c.str().c_str(), |
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| 289 | mt_int, // mapping table |
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| 290 | x_id, y_id, // cluster coordinates |
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| 291 | x_width, y_width, l_width, |
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| 292 | 1, // number of local sources |
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[802] | 293 | nb_procs, // number of local targets |
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[468] | 294 | 1, 1, // fifo depths |
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[1050] | 295 | true, // pseudo CMD |
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[707] | 296 | false, // no routing table |
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[1050] | 297 | false); // no broadcast |
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[468] | 298 | |
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[1002] | 299 | //////////// DSPIN INT_CMD ROUTER //////////////////////////////////////////// |
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[450] | 300 | std::ostringstream s_int_router_cmd; |
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[1002] | 301 | s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id; |
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| 302 | int_router_cmd = new DspinRouter<dspin_int_cmd_width>( |
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[450] | 303 | s_int_router_cmd.str().c_str(), |
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| 304 | x_id,y_id, // coordinate in the mesh |
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| 305 | x_width, y_width, // x & y fields width |
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| 306 | 4,4); // input & output fifo depths |
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| 307 | |
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[1002] | 308 | //////////// DSPIN INT_RSP ROUTER //////////////////////////////////////////// |
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[450] | 309 | std::ostringstream s_int_router_rsp; |
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[1002] | 310 | s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id; |
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| 311 | int_router_rsp = new DspinRouter<dspin_int_rsp_width>( |
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[450] | 312 | s_int_router_rsp.str().c_str(), |
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[1002] | 313 | x_id,y_id, // coordinates in mesh |
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[450] | 314 | x_width, y_width, // x & y fields width |
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| 315 | 4,4); // input & output fifo depths |
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| 316 | |
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[1002] | 317 | //////////// DSPIN INT_M2P ROUTER //////////////////////////////////////////// |
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| 318 | std::ostringstream s_int_router_m2p; |
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| 319 | s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id; |
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| 320 | int_router_m2p = new DspinRouter<dspin_int_cmd_width>( |
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| 321 | s_int_router_m2p.str().c_str(), |
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| 322 | x_id,y_id, // coordinate in the mesh |
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| 323 | x_width, y_width, // x & y fields width |
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| 324 | 4,4, // input & output fifo depths |
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| 325 | true); // broadcast supported |
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| 326 | |
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| 327 | //////////// DSPIN INT_P2M ROUTER //////////////////////////////////////////// |
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| 328 | std::ostringstream s_int_router_p2m; |
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| 329 | s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id; |
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| 330 | int_router_p2m = new DspinRouter<dspin_int_rsp_width>( |
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| 331 | s_int_router_p2m.str().c_str(), |
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| 332 | x_id,y_id, // coordinates in mesh |
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| 333 | x_width, y_width, // x & y fields width |
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| 334 | 4,4); // input & output fifo depths |
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| 335 | |
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| 336 | //////////// DSPIN INT_CLA ROUTER //////////////////////////////////////////// |
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| 337 | std::ostringstream s_int_router_cla; |
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| 338 | s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id; |
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| 339 | int_router_cla = new DspinRouter<dspin_int_cmd_width>( |
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| 340 | s_int_router_cla.str().c_str(), |
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| 341 | x_id,y_id, // coordinate in the mesh |
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| 342 | x_width, y_width, // x & y fields width |
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| 343 | 4,4); // input & output fifo depths |
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| 344 | |
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| 345 | ////////////// XRAM ///////////////////////////////////////////////////////// |
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[450] | 346 | std::ostringstream s_xram; |
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| 347 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 348 | xram = new VciSimpleRam<vci_param_ext>( |
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| 349 | s_xram.str().c_str(), |
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[718] | 350 | IntTab(cluster_id, ram_xram_tgt_id), |
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[450] | 351 | mt_ram, |
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| 352 | loader, |
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| 353 | xram_latency); |
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| 354 | |
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| 355 | std::ostringstream s_wt_xram; |
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| 356 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
---|
| 357 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
---|
| 358 | dspin_ram_cmd_width, |
---|
| 359 | dspin_ram_rsp_width>( |
---|
| 360 | s_wt_xram.str().c_str(), |
---|
| 361 | x_width + y_width + l_width); |
---|
| 362 | |
---|
[1002] | 363 | //////////// DSPIN RAM_CMD ROUTER /////////////////////////////////////////// |
---|
[450] | 364 | std::ostringstream s_ram_router_cmd; |
---|
| 365 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
---|
[718] | 366 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
---|
[450] | 367 | s_ram_router_cmd.str().c_str(), |
---|
[584] | 368 | x_id, y_id, // router coordinates in mesh |
---|
| 369 | x_width, // x field width in first flit |
---|
| 370 | y_width, // y field width in first flit |
---|
[718] | 371 | 4, 4); // input & output fifo depths |
---|
[450] | 372 | |
---|
[1002] | 373 | //////////// DSPIN RAM_RSP ROUTER /////////////////////////////////////////// |
---|
[450] | 374 | std::ostringstream s_ram_router_rsp; |
---|
| 375 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
---|
[718] | 376 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
---|
[450] | 377 | s_ram_router_rsp.str().c_str(), |
---|
[584] | 378 | x_id, y_id, // coordinates in mesh |
---|
| 379 | x_width, // x field width in first flit |
---|
| 380 | y_width, // y field width in first flit |
---|
[718] | 381 | 4, 4); // input & output fifo depths |
---|
[450] | 382 | |
---|
[550] | 383 | |
---|
[1002] | 384 | ////////////////////// I/O CLUSTER ONLY /////////////////////////////////// |
---|
[718] | 385 | if ( is_io ) |
---|
[450] | 386 | { |
---|
[1002] | 387 | /////////// IO_BRIDGE //////////////////////////////////////////////////// |
---|
[450] | 388 | std::ostringstream s_iob; |
---|
[802] | 389 | s_iob << "iob_" << x_id << "_" << y_id; |
---|
[450] | 390 | iob = new VciIoBridge<vci_param_int, |
---|
[802] | 391 | vci_param_ext>( |
---|
[450] | 392 | s_iob.str().c_str(), |
---|
[718] | 393 | mt_ram, // EXT network maptab |
---|
| 394 | mt_int, // INT network maptab |
---|
| 395 | mt_iox, // IOX network maptab |
---|
| 396 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
---|
| 397 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
---|
| 398 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
---|
| 399 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
---|
| 400 | 16, // cache line words |
---|
| 401 | 8, // IOTLB ways |
---|
| 402 | 8, // IOTLB sets |
---|
[450] | 403 | debug_start_cycle, |
---|
[1030] | 404 | debug_iob ); |
---|
[802] | 405 | |
---|
[450] | 406 | std::ostringstream s_iob_ram_wi; |
---|
[802] | 407 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
---|
[450] | 408 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
---|
| 409 | dspin_ram_cmd_width, |
---|
| 410 | dspin_ram_rsp_width>( |
---|
| 411 | s_iob_ram_wi.str().c_str(), |
---|
[718] | 412 | vci_param_int::S); |
---|
| 413 | |
---|
[1002] | 414 | //////////// DSPIN RAM_CMD LOCAL_XBAR /////////////////////////////////// |
---|
[718] | 415 | std::ostringstream s_ram_xbar_cmd; |
---|
| 416 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
---|
| 417 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
---|
| 418 | s_ram_xbar_cmd.str().c_str(), // name |
---|
| 419 | mt_ram, // mapping table |
---|
| 420 | x_id, y_id, // x, y |
---|
| 421 | x_width, y_width, l_width, // x_width, y_width, l_width |
---|
| 422 | 2, 0, // local inputs, local outputs |
---|
| 423 | 2, 2, // in fifo, out fifo depths |
---|
| 424 | true, // is cmd ? |
---|
[1050] | 425 | false, // no routing table |
---|
| 426 | false); // no broadcast |
---|
[718] | 427 | |
---|
[1002] | 428 | //////////// DSPIN RAM_RSP LOCAL_XBAR /////////////////////////////////// |
---|
[718] | 429 | std::ostringstream s_ram_xbar_rsp; |
---|
| 430 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
---|
| 431 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
---|
| 432 | s_ram_xbar_rsp.str().c_str(), // name |
---|
| 433 | mt_ram, // mapping table |
---|
| 434 | x_id, y_id, // x, y |
---|
| 435 | x_width, y_width, l_width, // x_width, y_width, l_width |
---|
| 436 | 0, 2, // local inputs, local outputs |
---|
| 437 | 2, 2, // in fifo, out fifo depths |
---|
| 438 | false, // is cmd ? |
---|
[1050] | 439 | true, // use routing table |
---|
| 440 | false); // no broadcast |
---|
[1002] | 441 | |
---|
[550] | 442 | } // end if IO |
---|
[450] | 443 | |
---|
| 444 | //////////////////////////////////// |
---|
| 445 | // Connections are defined here |
---|
| 446 | //////////////////////////////////// |
---|
| 447 | |
---|
| 448 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
| 449 | // : local srcid[memc] = nb_procs |
---|
[802] | 450 | |
---|
[450] | 451 | //////////////////////////////////// Processors |
---|
| 452 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 453 | { |
---|
| 454 | proc[p]->p_clk (this->p_clk); |
---|
| 455 | proc[p]->p_resetn (this->p_resetn); |
---|
[1002] | 456 | |
---|
[450] | 457 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
[468] | 458 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 459 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
[1002] | 460 | proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]); |
---|
[707] | 461 | |
---|
| 462 | for ( size_t j = 0 ; j < 6 ; j++) |
---|
[450] | 463 | { |
---|
[707] | 464 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
---|
| 465 | else proc[p]->p_irq[j] (signal_false); |
---|
[450] | 466 | } |
---|
| 467 | } |
---|
| 468 | |
---|
[1002] | 469 | std::cout << " - processors connected" << std::endl; |
---|
| 470 | |
---|
[450] | 471 | ///////////////////////////////////// XICU |
---|
[468] | 472 | xicu->p_clk (this->p_clk); |
---|
| 473 | xicu->p_resetn (this->p_resetn); |
---|
| 474 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
[959] | 475 | for ( size_t i=0 ; i < xcu_nb_out ; i++) |
---|
[450] | 476 | { |
---|
[714] | 477 | xicu->p_irq[i] (signal_proc_it[i]); |
---|
[450] | 478 | } |
---|
[959] | 479 | for ( size_t i=0 ; i < xcu_nb_hwi ; i++) |
---|
[450] | 480 | { |
---|
[1051] | 481 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
---|
| 482 | else if ( i < (nb_procs+1) ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
---|
| 483 | else xicu->p_hwi[i] (signal_false); |
---|
[802] | 484 | } |
---|
[450] | 485 | |
---|
[1002] | 486 | std::cout << " - xcu connected" << std::endl; |
---|
| 487 | |
---|
[450] | 488 | ///////////////////////////////////// MEMC |
---|
[468] | 489 | memc->p_clk (this->p_clk); |
---|
| 490 | memc->p_resetn (this->p_resetn); |
---|
| 491 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 492 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 493 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 494 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
[1002] | 495 | memc->p_dspin_clack (signal_int_dspin_cla_memc); |
---|
[607] | 496 | memc->p_irq (signal_irq_memc); |
---|
[450] | 497 | |
---|
| 498 | // wrapper to RAM network |
---|
| 499 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 500 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 501 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 502 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 503 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
| 504 | |
---|
[1002] | 505 | std::cout << " - memc connected" << std::endl; |
---|
| 506 | |
---|
[450] | 507 | //////////////////////////////////// XRAM |
---|
[468] | 508 | xram->p_clk (this->p_clk); |
---|
| 509 | xram->p_resetn (this->p_resetn); |
---|
| 510 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 511 | |
---|
| 512 | // wrapper to RAM network |
---|
| 513 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 514 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 515 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 516 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 517 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
| 518 | |
---|
[1002] | 519 | std::cout << " - xram connected" << std::endl; |
---|
| 520 | |
---|
[1051] | 521 | /////////////////////////////////// MDMA |
---|
| 522 | mdma->p_clk (this->p_clk); |
---|
| 523 | mdma->p_resetn (this->p_resetn); |
---|
| 524 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 525 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
| 526 | for( size_t i = 0 ; i < nb_procs ; i++ ) |
---|
[972] | 527 | { |
---|
[1051] | 528 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
[972] | 529 | } |
---|
| 530 | |
---|
[1051] | 531 | std::cout << " - mdma connected" << std::endl; |
---|
[972] | 532 | |
---|
[1002] | 533 | //////////////////////////// RAM NETWORK ROUTERS |
---|
[707] | 534 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 535 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 536 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 537 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
[1002] | 538 | |
---|
[550] | 539 | for( size_t n=0 ; n<4 ; n++) |
---|
[450] | 540 | { |
---|
[707] | 541 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 542 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 543 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 544 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
[450] | 545 | } |
---|
[718] | 546 | |
---|
[707] | 547 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 548 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
[718] | 549 | |
---|
| 550 | if ( is_io ) |
---|
| 551 | { |
---|
| 552 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
---|
| 553 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
---|
| 554 | } |
---|
| 555 | else |
---|
| 556 | { |
---|
| 557 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 558 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 559 | } |
---|
[802] | 560 | |
---|
[1002] | 561 | ///////////////////////////// INT NETWORK ROUTERS |
---|
| 562 | int_router_cmd->p_clk (this->p_clk); |
---|
| 563 | int_router_cmd->p_resetn (this->p_resetn); |
---|
| 564 | int_router_rsp->p_clk (this->p_clk); |
---|
| 565 | int_router_rsp->p_resetn (this->p_resetn); |
---|
| 566 | int_router_m2p->p_clk (this->p_clk); |
---|
| 567 | int_router_m2p->p_resetn (this->p_resetn); |
---|
| 568 | int_router_p2m->p_clk (this->p_clk); |
---|
| 569 | int_router_p2m->p_resetn (this->p_resetn); |
---|
| 570 | int_router_cla->p_clk (this->p_clk); |
---|
| 571 | int_router_cla->p_resetn (this->p_resetn); |
---|
| 572 | |
---|
| 573 | // loop on N/S/E/W ports |
---|
| 574 | for (size_t i = 0; i < 4; i++) |
---|
| 575 | { |
---|
| 576 | int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]); |
---|
| 577 | int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]); |
---|
| 578 | |
---|
| 579 | int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]); |
---|
| 580 | int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]); |
---|
| 581 | |
---|
| 582 | int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]); |
---|
| 583 | int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]); |
---|
| 584 | |
---|
| 585 | int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]); |
---|
| 586 | int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]); |
---|
| 587 | |
---|
| 588 | int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]); |
---|
| 589 | int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]); |
---|
| 590 | } |
---|
| 591 | |
---|
| 592 | int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d); |
---|
| 593 | int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d); |
---|
| 594 | |
---|
| 595 | int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d); |
---|
| 596 | int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d); |
---|
| 597 | |
---|
| 598 | int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c); |
---|
| 599 | int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c); |
---|
| 600 | |
---|
| 601 | int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c); |
---|
| 602 | int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c); |
---|
| 603 | |
---|
| 604 | int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c); |
---|
| 605 | int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c); |
---|
| 606 | |
---|
| 607 | std::cout << " - internal routers connected" << std::endl; |
---|
| 608 | |
---|
| 609 | |
---|
| 610 | ///////////////////// CMD DSPIN local crossbar direct |
---|
| 611 | int_xbar_d->p_clk (this->p_clk); |
---|
| 612 | int_xbar_d->p_resetn (this->p_resetn); |
---|
| 613 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
---|
| 614 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
---|
| 615 | |
---|
| 616 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
---|
| 617 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
---|
[1051] | 618 | int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); |
---|
| 619 | int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); |
---|
[1002] | 620 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 621 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
---|
| 622 | |
---|
| 623 | if ( is_io ) |
---|
| 624 | { |
---|
| 625 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
---|
| 626 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
---|
| 627 | } |
---|
| 628 | |
---|
| 629 | int_wi_gate_d->p_clk (this->p_clk); |
---|
| 630 | int_wi_gate_d->p_resetn (this->p_resetn); |
---|
| 631 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
---|
| 632 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
---|
| 633 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
---|
| 634 | |
---|
| 635 | int_wt_gate_d->p_clk (this->p_clk); |
---|
| 636 | int_wt_gate_d->p_resetn (this->p_resetn); |
---|
| 637 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
---|
| 638 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
---|
| 639 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
---|
| 640 | |
---|
| 641 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
| 642 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
| 643 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
| 644 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 645 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
| 646 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
| 647 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 648 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
| 649 | |
---|
| 650 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 651 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 652 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
| 653 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
| 654 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 655 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
| 656 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 657 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 658 | |
---|
| 659 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 660 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 661 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
| 662 | int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c); |
---|
| 663 | int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c); |
---|
| 664 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc); |
---|
| 665 | for (size_t p = 0; p < nb_procs; p++) |
---|
| 666 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]); |
---|
| 667 | |
---|
| 668 | |
---|
[802] | 669 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
[718] | 670 | if ( is_io ) |
---|
[450] | 671 | { |
---|
| 672 | // IO bridge |
---|
[718] | 673 | iob->p_clk (this->p_clk); |
---|
| 674 | iob->p_resetn (this->p_resetn); |
---|
| 675 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 676 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 677 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 678 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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| 679 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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[550] | 680 | |
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[450] | 681 | // initiator wrapper to RAM network |
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[718] | 682 | iob_ram_wi->p_clk (this->p_clk); |
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| 683 | iob_ram_wi->p_resetn (this->p_resetn); |
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| 684 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
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| 685 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
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| 686 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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| 687 | |
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| 688 | // crossbar between MEMC and IOB to RAM network |
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| 689 | ram_xbar_cmd->p_clk (this->p_clk); |
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| 690 | ram_xbar_cmd->p_resetn (this->p_resetn); |
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| 691 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
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| 692 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
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| 693 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
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| 694 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
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| 695 | |
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| 696 | ram_xbar_rsp->p_clk (this->p_clk); |
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| 697 | ram_xbar_rsp->p_resetn (this->p_resetn); |
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| 698 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
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| 699 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
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| 700 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
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| 701 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
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[550] | 702 | } |
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[450] | 703 | |
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[739] | 704 | SC_METHOD(init); |
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[1031] | 705 | dont_initialize(); |
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[739] | 706 | |
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[450] | 707 | } // end constructor |
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| 708 | |
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[718] | 709 | tmpl(void)::init() |
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| 710 | { |
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| 711 | signal_ram_dspin_cmd_false.write = false; |
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[739] | 712 | signal_ram_dspin_rsp_false.read = true; |
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[972] | 713 | } |
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[718] | 714 | |
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[450] | 715 | }} |
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| 716 | |
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| 717 | |
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| 718 | // Local Variables: |
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| 719 | // tab-width: 3 |
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| 720 | // c-basic-offset: 3 |
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| 721 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 722 | // indent-tabs-mode: nil |
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| 723 | // End: |
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| 724 | |
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| 725 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 726 | |
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