[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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| 12 | // - 2 dspin_local_crossbar for commands and responses. |
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| 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | namespace soclib { namespace caba { |
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| 18 | |
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| 19 | ////////////////////////////////////////////////////////////////////////// |
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| 20 | // Constructor |
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| 21 | ////////////////////////////////////////////////////////////////////////// |
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| 22 | template<typename vci_param_int, |
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| 23 | typename vci_param_ext, |
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| 24 | size_t dspin_int_cmd_width, |
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| 25 | size_t dspin_int_rsp_width, |
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| 26 | size_t dspin_ram_cmd_width, |
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| 27 | size_t dspin_ram_rsp_width> |
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| 28 | TsarIobCluster<vci_param_int, |
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| 29 | vci_param_ext, |
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| 30 | dspin_int_cmd_width, |
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| 31 | dspin_int_rsp_width, |
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| 32 | dspin_ram_cmd_width, |
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| 33 | dspin_ram_rsp_width>::TsarIobCluster( |
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| 34 | ////////////////////////////////////////////////////////////////////////// |
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| 35 | sc_module_name insname, |
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| 36 | size_t nb_procs, |
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| 37 | size_t nb_dmas, |
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| 38 | size_t x_id, |
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| 39 | size_t y_id, |
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| 40 | size_t xmax, |
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| 41 | size_t ymax, |
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| 42 | |
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| 43 | const soclib::common::MappingTable &mt_int, |
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| 44 | const soclib::common::MappingTable &mt_ram, |
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| 45 | const soclib::common::MappingTable &mt_iox, |
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| 46 | |
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| 47 | size_t x_width, |
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| 48 | size_t y_width, |
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| 49 | size_t l_width, |
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| 50 | |
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[550] | 51 | size_t memc_int_tgtid, // local index |
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| 52 | size_t xicu_int_tgtid, // local index |
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| 53 | size_t mdma_int_tgtid, // local index |
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| 54 | size_t iobx_int_tgtid, // local index |
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[450] | 55 | |
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[550] | 56 | size_t proc_int_srcid, // local index |
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| 57 | size_t mdma_int_srcid, // local index |
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| 58 | size_t iobx_int_srcid, // local index |
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[450] | 59 | |
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[550] | 60 | size_t xram_ram_tgtid, // local index |
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[450] | 61 | |
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[550] | 62 | size_t memc_ram_srcid, // local index |
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| 63 | size_t iobx_ram_srcid, // local index |
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[450] | 64 | |
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| 65 | size_t memc_ways, |
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| 66 | size_t memc_sets, |
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| 67 | size_t l1_i_ways, |
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| 68 | size_t l1_i_sets, |
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| 69 | size_t l1_d_ways, |
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| 70 | size_t l1_d_sets, |
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| 71 | size_t xram_latency, |
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| 72 | |
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| 73 | const Loader &loader, |
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| 74 | |
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| 75 | uint32_t frozen_cycles, |
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| 76 | uint32_t debug_start_cycle, |
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| 77 | bool memc_debug_ok, |
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| 78 | bool proc_debug_ok, |
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| 79 | bool iob_debug_ok ) |
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| 80 | : soclib::caba::BaseModule(insname), |
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| 81 | p_clk("clk"), |
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| 82 | p_resetn("resetn") |
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| 83 | { |
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| 84 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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| 85 | |
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[607] | 86 | size_t cluster_id = (x_id<<4) + y_id; |
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[450] | 87 | |
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[607] | 88 | size_t cluster_iob0 = 0; // South-West cluster |
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| 89 | size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster |
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[550] | 90 | |
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[450] | 91 | // Vectors of DSPIN ports for inter-cluster communications |
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[468] | 92 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 93 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 94 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 95 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 96 | |
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| 97 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 98 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 99 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 100 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 101 | |
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[550] | 102 | // ports in cluster_iob0 and cluster_iob1 only |
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[450] | 103 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 104 | { |
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[550] | 105 | // VCI ports from IOB to IOX network |
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| 106 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 107 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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| 108 | |
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| 109 | // DSPIN ports from IOB to RAM network |
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| 110 | p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; |
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| 111 | p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; |
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[450] | 112 | } |
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| 113 | |
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| 114 | // IRQ ports in cluster_iob0 only |
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| 115 | if ( cluster_id == cluster_iob0 ) |
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| 116 | { |
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| 117 | for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>; |
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| 118 | } |
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| 119 | |
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| 120 | ///////////////////////////////////////////////////////////////////////////// |
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| 121 | // Hardware components |
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| 122 | ///////////////////////////////////////////////////////////////////////////// |
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| 123 | |
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| 124 | //////////// PROCS |
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| 125 | for (size_t p = 0; p < nb_procs; p++) |
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| 126 | { |
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| 127 | std::ostringstream s_proc; |
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| 128 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 129 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 130 | dspin_int_cmd_width, |
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| 131 | dspin_int_rsp_width, |
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| 132 | GdbServer<Mips32ElIss> >( |
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| 133 | s_proc.str().c_str(), |
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| 134 | cluster_id*nb_procs + p, // GLOBAL PROC_ID |
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| 135 | mt_int, // Mapping Table INT network |
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| 136 | IntTab(cluster_id,p), // SRCID |
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| 137 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 138 | 8, // ITLB ways |
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| 139 | 8, // ITLB sets |
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| 140 | 8, // DTLB ways |
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| 141 | 8, // DTLB sets |
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| 142 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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| 143 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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| 144 | 4, // WBUF nlines |
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| 145 | 4, // WBUF nwords |
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| 146 | x_width, |
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| 147 | y_width, |
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| 148 | frozen_cycles, // max frozen cycles |
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| 149 | debug_start_cycle, |
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| 150 | proc_debug_ok); |
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| 151 | } |
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| 152 | |
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| 153 | /////////// MEMC |
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| 154 | std::ostringstream s_memc; |
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| 155 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 156 | memc = new VciMemCache<vci_param_int, |
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| 157 | vci_param_ext, |
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| 158 | dspin_int_rsp_width, |
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| 159 | dspin_int_cmd_width>( |
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| 160 | s_memc.str().c_str(), |
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| 161 | mt_int, // Mapping Table INT network |
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| 162 | mt_ram, // Mapping Table RAM network |
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| 163 | IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network |
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| 164 | IntTab(cluster_id, memc_int_tgtid), // TGTID INT network |
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[550] | 165 | x_width, // number of bits for x coordinate |
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| 166 | y_width, // number of bits for y coordinate |
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[450] | 167 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 168 | 3, // MAX NUMBER OF COPIES |
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| 169 | 4096, // HEAP SIZE |
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| 170 | 8, // TRANSACTION TABLE DEPTH |
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| 171 | 8, // UPDATE TABLE DEPTH |
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[468] | 172 | 8, // INVALIDATE TABLE DEPTH |
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[450] | 173 | debug_start_cycle, |
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| 174 | memc_debug_ok ); |
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| 175 | |
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| 176 | std::ostringstream s_wi_memc; |
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| 177 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 178 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 179 | dspin_ram_cmd_width, |
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| 180 | dspin_ram_rsp_width>( |
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| 181 | s_wi_memc.str().c_str(), |
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| 182 | x_width + y_width + l_width); |
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| 183 | |
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| 184 | /////////// XICU |
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| 185 | std::ostringstream s_xicu; |
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| 186 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 187 | xicu = new VciXicu<vci_param_int>( |
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| 188 | s_xicu.str().c_str(), |
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| 189 | mt_int, // mapping table INT network |
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| 190 | IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space |
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[584] | 191 | 32, // number of timer IRQs |
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[450] | 192 | 32, // number of hard IRQs |
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| 193 | 32, // number of soft IRQs |
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| 194 | nb_procs); // number of output IRQs |
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| 195 | |
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| 196 | //////////// MDMA |
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| 197 | std::ostringstream s_mdma; |
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| 198 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 199 | mdma = new VciMultiDma<vci_param_int>( |
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| 200 | s_mdma.str().c_str(), |
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| 201 | mt_int, |
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| 202 | IntTab(cluster_id, nb_procs), // SRCID |
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| 203 | IntTab(cluster_id, mdma_int_tgtid), // TGTID |
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| 204 | 64, // burst size |
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| 205 | nb_dmas); // number of IRQs |
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| 206 | |
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| 207 | /////////// Direct LOCAL_XBAR(S) |
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| 208 | size_t nb_direct_initiators = nb_procs + 1; |
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| 209 | size_t nb_direct_targets = 3; |
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| 210 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 211 | { |
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| 212 | nb_direct_initiators = nb_procs + 2; |
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| 213 | nb_direct_targets = 4; |
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| 214 | } |
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| 215 | |
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[693] | 216 | std::ostringstream s_int_xbar_d; |
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| 217 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 218 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 219 | s_int_xbar_d.str().c_str(), |
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[450] | 220 | mt_int, // mapping table |
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[693] | 221 | cluster_id, // cluster id |
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| 222 | nb_direct_initiators, // number of local initiators |
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| 223 | nb_direct_targets, // number of local targets |
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| 224 | 0 ); // default target |
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[450] | 225 | |
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[693] | 226 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 227 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 228 | << x_id << "_" << y_id; |
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| 229 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 230 | dspin_int_cmd_width, |
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| 231 | dspin_int_rsp_width>( |
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| 232 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 233 | x_width + y_width + l_width); |
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[450] | 234 | |
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[693] | 235 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 236 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 237 | << x_id << "_" << y_id; |
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| 238 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 239 | dspin_int_cmd_width, |
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| 240 | dspin_int_rsp_width>( |
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| 241 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 242 | x_width + y_width + l_width); |
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| 243 | |
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| 244 | |
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[450] | 245 | //////////// Coherence LOCAL_XBAR(S) |
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| 246 | std::ostringstream s_int_xbar_m2p_c; |
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| 247 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 248 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 249 | s_int_xbar_m2p_c.str().c_str(), |
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| 250 | mt_int, // mapping table |
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| 251 | x_id, y_id, // cluster coordinates |
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| 252 | x_width, y_width, l_width, // several dests |
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| 253 | 1, // number of local sources |
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| 254 | nb_procs, // number of local dests |
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| 255 | 2, 2, // fifo depths |
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| 256 | true, // pseudo CMD |
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| 257 | false, // no routing table |
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| 258 | true ); // broacast |
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| 259 | |
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| 260 | std::ostringstream s_int_xbar_p2m_c; |
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| 261 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 262 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 263 | s_int_xbar_p2m_c.str().c_str(), |
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| 264 | mt_int, // mapping table |
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| 265 | x_id, y_id, // cluster coordinates |
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| 266 | x_width, y_width, 0, // only one dest |
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| 267 | nb_procs, // number of local sources |
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| 268 | 1, // number of local dests |
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| 269 | 2, 2, // fifo depths |
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| 270 | false, // pseudo RSP |
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| 271 | false, // no routing table |
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| 272 | false ); // no broacast |
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| 273 | |
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[468] | 274 | std::ostringstream s_int_xbar_clack_c; |
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| 275 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 276 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 277 | s_int_xbar_clack_c.str().c_str(), |
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| 278 | mt_int, // mapping table |
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| 279 | x_id, y_id, // cluster coordinates |
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| 280 | x_width, y_width, l_width, |
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| 281 | 1, // number of local sources |
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| 282 | nb_procs, // number of local targets |
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| 283 | 1, 1, // fifo depths |
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| 284 | true, // CMD |
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| 285 | false, // don't use local routing table |
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| 286 | false); // broadcast |
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| 287 | |
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[450] | 288 | ////////////// INT ROUTER(S) |
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| 289 | std::ostringstream s_int_router_cmd; |
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| 290 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 291 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 292 | s_int_router_cmd.str().c_str(), |
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| 293 | x_id,y_id, // coordinate in the mesh |
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| 294 | x_width, y_width, // x & y fields width |
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[468] | 295 | 3, // nb virtual channels |
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[450] | 296 | 4,4); // input & output fifo depths |
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| 297 | |
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| 298 | std::ostringstream s_int_router_rsp; |
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| 299 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 300 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 301 | s_int_router_rsp.str().c_str(), |
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[550] | 302 | x_id,y_id, // router coordinates in mesh |
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[450] | 303 | x_width, y_width, // x & y fields width |
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[468] | 304 | 2, // nb virtual channels |
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[450] | 305 | 4,4); // input & output fifo depths |
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| 306 | |
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| 307 | ////////////// XRAM |
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| 308 | std::ostringstream s_xram; |
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| 309 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 310 | xram = new VciSimpleRam<vci_param_ext>( |
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| 311 | s_xram.str().c_str(), |
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| 312 | IntTab(cluster_id, xram_ram_tgtid ), |
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| 313 | mt_ram, |
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| 314 | loader, |
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| 315 | xram_latency); |
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| 316 | |
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| 317 | std::ostringstream s_wt_xram; |
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| 318 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 319 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 320 | dspin_ram_cmd_width, |
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| 321 | dspin_ram_rsp_width>( |
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| 322 | s_wt_xram.str().c_str(), |
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| 323 | x_width + y_width + l_width); |
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| 324 | |
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| 325 | ///////////// RAM ROUTER(S) |
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| 326 | std::ostringstream s_ram_router_cmd; |
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| 327 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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[584] | 328 | size_t is_iob0 = (x_id == 0) and (y_id == 0); |
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| 329 | size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1)); |
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[550] | 330 | ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( |
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[450] | 331 | s_ram_router_cmd.str().c_str(), |
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[584] | 332 | x_id, y_id, // router coordinates in mesh |
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| 333 | x_width, // x field width in first flit |
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| 334 | y_width, // y field width in first flit |
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| 335 | 4, 4, // input & output fifo depths |
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| 336 | is_iob0, // cluster contains IOB0 |
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| 337 | is_iob1, // cluster contains IOB1 |
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| 338 | false, // not a response router |
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| 339 | l_width); // local field width in first flit |
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[450] | 340 | |
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| 341 | std::ostringstream s_ram_router_rsp; |
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| 342 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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[550] | 343 | ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( |
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[450] | 344 | s_ram_router_rsp.str().c_str(), |
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[584] | 345 | x_id, y_id, // coordinates in mesh |
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| 346 | x_width, // x field width in first flit |
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| 347 | y_width, // y field width in first flit |
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| 348 | 4, 4, // input & output fifo depths |
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| 349 | is_iob0, // cluster contains IOB0 |
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| 350 | is_iob1, // cluster contains IOB1 |
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| 351 | true, // response router |
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| 352 | l_width); // local field width in first flit |
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[450] | 353 | |
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[550] | 354 | |
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[450] | 355 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 356 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 357 | { |
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| 358 | /////////// IO_BRIDGE |
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| 359 | size_t iox_local_id; |
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| 360 | size_t global_id; |
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| 361 | bool has_irqs; |
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| 362 | if ( cluster_id == cluster_iob0 ) |
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| 363 | { |
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| 364 | iox_local_id = 0; |
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| 365 | global_id = cluster_iob0; |
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| 366 | has_irqs = true; |
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| 367 | } |
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| 368 | else |
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| 369 | { |
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| 370 | iox_local_id = 1; |
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| 371 | global_id = cluster_iob1; |
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| 372 | has_irqs = false; |
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| 373 | } |
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| 374 | |
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| 375 | std::ostringstream s_iob; |
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| 376 | s_iob << "iob_" << x_id << "_" << y_id; |
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| 377 | iob = new VciIoBridge<vci_param_int, |
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| 378 | vci_param_ext>( |
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| 379 | s_iob.str().c_str(), |
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| 380 | mt_ram, // EXT network maptab |
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| 381 | mt_int, // INT network maptab |
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| 382 | mt_iox, // IOX network maptab |
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| 383 | IntTab( global_id, iobx_int_tgtid ), // INT TGTID |
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| 384 | IntTab( global_id, iobx_int_srcid ), // INT SRCID |
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| 385 | IntTab( global_id, iox_local_id ), // IOX TGTID |
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| 386 | has_irqs, |
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| 387 | 16, // cache line words |
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| 388 | 8, // IOTLB ways |
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| 389 | 8, // IOTLB sets |
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| 390 | debug_start_cycle, |
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| 391 | iob_debug_ok ); |
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| 392 | |
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| 393 | std::ostringstream s_iob_ram_wi; |
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| 394 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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| 395 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 396 | dspin_ram_cmd_width, |
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| 397 | dspin_ram_rsp_width>( |
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| 398 | s_iob_ram_wi.str().c_str(), |
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| 399 | x_width + y_width + l_width); |
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[550] | 400 | } // end if IO |
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[450] | 401 | |
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| 402 | //////////////////////////////////// |
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| 403 | // Connections are defined here |
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| 404 | //////////////////////////////////// |
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| 405 | |
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| 406 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 407 | // : local srcid[memc] = nb_procs |
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[584] | 408 | // In cluster_iob0, 32 HWI interrupts from external peripherals |
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| 409 | // are connected to the XICU ports p_hwi[0:31] |
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| 410 | // In other clusters, no HWI interrupts are connected to XICU |
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| 411 | |
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[450] | 412 | //////////////////////// internal CMD & RSP routers |
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| 413 | int_router_cmd->p_clk (this->p_clk); |
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| 414 | int_router_cmd->p_resetn (this->p_resetn); |
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| 415 | int_router_rsp->p_clk (this->p_clk); |
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| 416 | int_router_rsp->p_resetn (this->p_resetn); |
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[468] | 417 | |
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| 418 | for (int i = 0; i < 4; i++) |
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[450] | 419 | { |
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[468] | 420 | for(int k = 0; k < 3; k++) |
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[450] | 421 | { |
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[468] | 422 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 423 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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[450] | 424 | } |
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[468] | 425 | |
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| 426 | for(int k = 0; k < 2; k++) |
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| 427 | { |
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| 428 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 429 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 430 | } |
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[450] | 431 | } |
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| 432 | |
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| 433 | // local ports |
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[468] | 434 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 435 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 436 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 437 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 438 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 439 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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[450] | 440 | |
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[468] | 441 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 442 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 443 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 444 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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[450] | 445 | |
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| 446 | ///////////////////// CMD DSPIN local crossbar direct |
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[693] | 447 | int_xbar_d->p_clk (this->p_clk); |
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| 448 | int_xbar_d->p_resetn (this->p_resetn); |
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| 449 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
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| 450 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
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[450] | 451 | |
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[693] | 452 | int_xbar_d->p_to_target[memc_int_tgtid] (signal_int_vci_tgt_memc); |
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| 453 | int_xbar_d->p_to_target[xicu_int_tgtid] (signal_int_vci_tgt_xicu); |
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| 454 | int_xbar_d->p_to_target[mdma_int_tgtid] (signal_int_vci_tgt_mdma); |
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| 455 | int_xbar_d->p_to_initiator[mdma_int_srcid] (signal_int_vci_ini_mdma); |
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[450] | 456 | for (size_t p = 0; p < nb_procs; p++) |
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[693] | 457 | int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]); |
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[450] | 458 | |
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| 459 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 460 | { |
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[693] | 461 | int_xbar_d->p_to_target[iobx_int_tgtid] (signal_int_vci_tgt_iobx); |
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| 462 | int_xbar_d->p_to_initiator[iobx_int_srcid] (signal_int_vci_ini_iobx); |
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[450] | 463 | } |
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| 464 | |
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[693] | 465 | int_wi_gate_d->p_clk (this->p_clk); |
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| 466 | int_wi_gate_d->p_resetn (this->p_resetn); |
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| 467 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
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| 468 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
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| 469 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
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[450] | 470 | |
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[693] | 471 | int_wt_gate_d->p_clk (this->p_clk); |
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| 472 | int_wt_gate_d->p_resetn (this->p_resetn); |
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| 473 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 474 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
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| 475 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
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| 476 | |
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[450] | 477 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 478 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 479 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
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| 480 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
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| 481 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 482 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
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| 483 | for (size_t p = 0; p < nb_procs; p++) |
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| 484 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 485 | |
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| 486 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 487 | int_xbar_p2m_c->p_clk (this->p_clk); |
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| 488 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 489 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 490 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
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| 491 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
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| 492 | for (size_t p = 0; p < nb_procs; p++) |
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| 493 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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| 494 | |
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[468] | 495 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 496 | int_xbar_clack_c->p_clk (this->p_clk); |
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| 497 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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| 498 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
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| 499 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
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| 500 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
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| 501 | for (size_t p = 0; p < nb_procs; p++) |
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| 502 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
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| 503 | |
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[450] | 504 | //////////////////////////////////// Processors |
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| 505 | for (size_t p = 0; p < nb_procs; p++) |
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| 506 | { |
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| 507 | proc[p]->p_clk (this->p_clk); |
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| 508 | proc[p]->p_resetn (this->p_resetn); |
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| 509 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
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[468] | 510 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
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| 511 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
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| 512 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
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[450] | 513 | proc[p]->p_irq[0] (signal_proc_it[p]); |
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| 514 | for ( size_t j = 1 ; j < 6 ; j++) |
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| 515 | { |
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| 516 | proc[p]->p_irq[j] (signal_false); |
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| 517 | } |
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| 518 | } |
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| 519 | |
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| 520 | ///////////////////////////////////// XICU |
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[468] | 521 | xicu->p_clk (this->p_clk); |
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| 522 | xicu->p_resetn (this->p_resetn); |
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| 523 | xicu->p_vci (signal_int_vci_tgt_xicu); |
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[450] | 524 | for ( size_t p=0 ; p<nb_procs ; p++) |
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| 525 | { |
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[468] | 526 | xicu->p_irq[p] (signal_proc_it[p]); |
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[450] | 527 | } |
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[584] | 528 | for ( size_t i=0 ; i<32 ; i++) |
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[450] | 529 | { |
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| 530 | if (cluster_id == cluster_iob0) |
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[584] | 531 | xicu->p_hwi[i] (*(this->p_irq[i])); |
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[450] | 532 | else |
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[584] | 533 | xicu->p_hwi[i] (signal_false); |
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[450] | 534 | } |
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| 535 | |
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| 536 | ///////////////////////////////////// MEMC |
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[468] | 537 | memc->p_clk (this->p_clk); |
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| 538 | memc->p_resetn (this->p_resetn); |
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| 539 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
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| 540 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
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| 541 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
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| 542 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
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| 543 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
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[607] | 544 | memc->p_irq (signal_irq_memc); |
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[450] | 545 | |
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| 546 | // wrapper to RAM network |
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| 547 | memc_ram_wi->p_clk (this->p_clk); |
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| 548 | memc_ram_wi->p_resetn (this->p_resetn); |
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| 549 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
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| 550 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
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| 551 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
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| 552 | |
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| 553 | //////////////////////////////////// XRAM |
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[468] | 554 | xram->p_clk (this->p_clk); |
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| 555 | xram->p_resetn (this->p_resetn); |
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| 556 | xram->p_vci (signal_ram_vci_tgt_xram); |
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[450] | 557 | |
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| 558 | // wrapper to RAM network |
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| 559 | xram_ram_wt->p_clk (this->p_clk); |
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| 560 | xram_ram_wt->p_resetn (this->p_resetn); |
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| 561 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
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| 562 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
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| 563 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
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| 564 | |
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| 565 | /////////////////////////////////// MDMA |
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[468] | 566 | mdma->p_clk (this->p_clk); |
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[450] | 567 | mdma->p_resetn (this->p_resetn); |
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[468] | 568 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
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| 569 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
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[450] | 570 | for (size_t i=0 ; i<nb_dmas ; i++) |
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| 571 | mdma->p_irq[i] (signal_irq_mdma[i]); |
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| 572 | |
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[550] | 573 | //////////////////////////// RAM network CMD & RSP routers |
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| 574 | ram_router_cmd->p_clk (this->p_clk); |
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| 575 | ram_router_cmd->p_resetn (this->p_resetn); |
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| 576 | ram_router_rsp->p_clk (this->p_clk); |
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| 577 | ram_router_rsp->p_resetn (this->p_resetn); |
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| 578 | for( size_t n=0 ; n<4 ; n++) |
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[450] | 579 | { |
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[550] | 580 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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| 581 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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| 582 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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| 583 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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[450] | 584 | } |
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[550] | 585 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
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| 586 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
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| 587 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
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| 588 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
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| 589 | |
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| 590 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
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| 591 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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[450] | 592 | { |
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| 593 | // IO bridge |
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| 594 | iob->p_clk (this->p_clk); |
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| 595 | iob->p_resetn (this->p_resetn); |
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[550] | 596 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
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| 597 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
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[450] | 598 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
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| 599 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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| 600 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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[550] | 601 | |
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[450] | 602 | if ( cluster_id == cluster_iob0 ) |
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[550] | 603 | for ( size_t n=0 ; n<32 ; n++ ) |
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| 604 | (*iob->p_irq[n]) (*(this->p_irq[n])); |
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[450] | 605 | |
---|
| 606 | // initiator wrapper to RAM network |
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| 607 | iob_ram_wi->p_clk (this->p_clk); |
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| 608 | iob_ram_wi->p_resetn (this->p_resetn); |
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[550] | 609 | iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); |
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| 610 | iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); |
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[450] | 611 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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[550] | 612 | } |
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[450] | 613 | |
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| 614 | } // end constructor |
---|
| 615 | |
---|
| 616 | }} |
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| 617 | |
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| 618 | |
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| 619 | // Local Variables: |
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| 620 | // tab-width: 3 |
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| 621 | // c-basic-offset: 3 |
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| 622 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 623 | // indent-tabs-mode: nil |
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| 624 | // End: |
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| 625 | |
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| 626 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 627 | |
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| 628 | |
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| 629 | |
---|