[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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[802] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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[802] | 12 | // - 2 dspin_local_crossbar for commands and responses. |
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[450] | 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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[718] | 17 | #define tmpl(x) \ |
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| 18 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 19 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 20 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 21 | x TsarIobCluster<\ |
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| 22 | vci_param_int , vci_param_ext,\ |
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| 23 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 24 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 25 | |
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[450] | 26 | namespace soclib { namespace caba { |
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| 27 | |
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| 28 | ////////////////////////////////////////////////////////////////////////// |
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| 29 | // Constructor |
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| 30 | ////////////////////////////////////////////////////////////////////////// |
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[718] | 31 | tmpl(/**/)::TsarIobCluster( |
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[450] | 32 | ////////////////////////////////////////////////////////////////////////// |
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| 33 | sc_module_name insname, |
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| 34 | size_t nb_procs, |
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| 35 | size_t nb_dmas, |
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| 36 | size_t x_id, |
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| 37 | size_t y_id, |
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| 38 | size_t xmax, |
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| 39 | size_t ymax, |
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| 40 | |
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| 41 | const soclib::common::MappingTable &mt_int, |
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[802] | 42 | const soclib::common::MappingTable &mt_ram, |
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| 43 | const soclib::common::MappingTable &mt_iox, |
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[450] | 44 | |
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| 45 | size_t x_width, |
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| 46 | size_t y_width, |
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| 47 | size_t l_width, |
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[802] | 48 | size_t p_width, |
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[450] | 49 | |
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[718] | 50 | size_t int_memc_tgt_id, // local index |
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| 51 | size_t int_xicu_tgt_id, // local index |
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| 52 | size_t int_mdma_tgt_id, // local index |
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| 53 | size_t int_iobx_tgt_id, // local index |
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[450] | 54 | |
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[718] | 55 | size_t int_proc_ini_id, // local index |
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| 56 | size_t int_mdma_ini_id, // local index |
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| 57 | size_t int_iobx_ini_id, // local index |
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[450] | 58 | |
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[718] | 59 | size_t ram_xram_tgt_id, // local index |
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| 60 | size_t ram_memc_ini_id, // local index |
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| 61 | size_t ram_iobx_ini_id, // local index |
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[450] | 62 | |
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[718] | 63 | bool is_io, // is IO cluster (IOB)? |
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| 64 | size_t iox_iobx_tgt_id, // local_index |
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| 65 | size_t iox_iobx_ini_id, // local index |
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[450] | 66 | |
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| 67 | size_t memc_ways, |
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| 68 | size_t memc_sets, |
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| 69 | size_t l1_i_ways, |
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| 70 | size_t l1_i_sets, |
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| 71 | size_t l1_d_ways, |
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| 72 | size_t l1_d_sets, |
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| 73 | size_t xram_latency, |
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[959] | 74 | size_t xcu_nb_hwi, |
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| 75 | size_t xcu_nb_pti, |
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| 76 | size_t xcu_nb_wti, |
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| 77 | size_t xcu_nb_out, |
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[450] | 78 | |
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| 79 | const Loader &loader, |
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| 80 | |
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| 81 | uint32_t frozen_cycles, |
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| 82 | uint32_t debug_start_cycle, |
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| 83 | bool memc_debug_ok, |
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| 84 | bool proc_debug_ok, |
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| 85 | bool iob_debug_ok ) |
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| 86 | : soclib::caba::BaseModule(insname), |
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| 87 | p_clk("clk"), |
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| 88 | p_resetn("resetn") |
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| 89 | { |
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| 90 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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| 91 | |
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[607] | 92 | size_t cluster_id = (x_id<<4) + y_id; |
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[450] | 93 | |
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| 94 | // Vectors of DSPIN ports for inter-cluster communications |
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[468] | 95 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 96 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 97 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 98 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 99 | |
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| 100 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 101 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 102 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 103 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 104 | |
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[718] | 105 | // VCI ports from IOB to IOX network (only in IO clusters) |
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| 106 | if ( is_io ) |
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[450] | 107 | { |
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[550] | 108 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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[802] | 109 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[450] | 110 | } |
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| 111 | |
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| 112 | ///////////////////////////////////////////////////////////////////////////// |
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| 113 | // Hardware components |
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| 114 | ///////////////////////////////////////////////////////////////////////////// |
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| 115 | |
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| 116 | //////////// PROCS |
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| 117 | for (size_t p = 0; p < nb_procs; p++) |
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[802] | 118 | { |
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[450] | 119 | std::ostringstream s_proc; |
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| 120 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 121 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 122 | dspin_int_cmd_width, |
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| 123 | dspin_int_rsp_width, |
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| 124 | GdbServer<Mips32ElIss> >( |
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| 125 | s_proc.str().c_str(), |
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[802] | 126 | (cluster_id << p_width) + p, // GLOBAL PROC_ID |
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[450] | 127 | mt_int, // Mapping Table INT network |
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| 128 | IntTab(cluster_id,p), // SRCID |
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| 129 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 130 | 8, // ITLB ways |
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| 131 | 8, // ITLB sets |
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| 132 | 8, // DTLB ways |
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| 133 | 8, // DTLB sets |
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[718] | 134 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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| 135 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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[450] | 136 | 4, // WBUF nlines |
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| 137 | 4, // WBUF nwords |
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| 138 | x_width, |
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| 139 | y_width, |
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| 140 | frozen_cycles, // max frozen cycles |
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| 141 | debug_start_cycle, |
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| 142 | proc_debug_ok); |
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| 143 | } |
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| 144 | |
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[802] | 145 | /////////// MEMC |
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[450] | 146 | std::ostringstream s_memc; |
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| 147 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 148 | memc = new VciMemCache<vci_param_int, |
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| 149 | vci_param_ext, |
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| 150 | dspin_int_rsp_width, |
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| 151 | dspin_int_cmd_width>( |
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| 152 | s_memc.str().c_str(), |
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[718] | 153 | mt_int, // Mapping Table INT network |
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| 154 | mt_ram, // Mapping Table RAM network |
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| 155 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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| 156 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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| 157 | x_width, // number of bits for x coordinate |
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| 158 | y_width, // number of bits for y coordinate |
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| 159 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 160 | 3, // MAX NUMBER OF COPIES |
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| 161 | 4096, // HEAP SIZE |
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| 162 | 8, // TRANSACTION TABLE DEPTH |
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| 163 | 8, // UPDATE TABLE DEPTH |
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| 164 | 8, // INVALIDATE TABLE DEPTH |
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[450] | 165 | debug_start_cycle, |
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| 166 | memc_debug_ok ); |
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| 167 | |
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| 168 | std::ostringstream s_wi_memc; |
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| 169 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 170 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 171 | dspin_ram_cmd_width, |
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| 172 | dspin_ram_rsp_width>( |
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| 173 | s_wi_memc.str().c_str(), |
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| 174 | x_width + y_width + l_width); |
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| 175 | |
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| 176 | /////////// XICU |
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| 177 | std::ostringstream s_xicu; |
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| 178 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 179 | xicu = new VciXicu<vci_param_int>( |
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| 180 | s_xicu.str().c_str(), |
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[718] | 181 | mt_int, // mapping table INT network |
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| 182 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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[959] | 183 | xcu_nb_pti, // number of timer IRQs |
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| 184 | xcu_nb_hwi, // number of hard IRQs |
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| 185 | xcu_nb_wti, // number of soft IRQs |
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| 186 | xcu_nb_out); // number of output IRQs |
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[450] | 187 | |
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| 188 | //////////// MDMA |
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| 189 | std::ostringstream s_mdma; |
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| 190 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 191 | mdma = new VciMultiDma<vci_param_int>( |
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| 192 | s_mdma.str().c_str(), |
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| 193 | mt_int, |
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| 194 | IntTab(cluster_id, nb_procs), // SRCID |
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[718] | 195 | IntTab(cluster_id, int_mdma_tgt_id), // TGTID |
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[450] | 196 | 64, // burst size |
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| 197 | nb_dmas); // number of IRQs |
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| 198 | |
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| 199 | /////////// Direct LOCAL_XBAR(S) |
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[718] | 200 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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| 201 | size_t nb_direct_targets = is_io ? 4 : 3; |
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[450] | 202 | |
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[693] | 203 | std::ostringstream s_int_xbar_d; |
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| 204 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 205 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 206 | s_int_xbar_d.str().c_str(), |
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[450] | 207 | mt_int, // mapping table |
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[693] | 208 | cluster_id, // cluster id |
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| 209 | nb_direct_initiators, // number of local initiators |
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[802] | 210 | nb_direct_targets, // number of local targets |
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[693] | 211 | 0 ); // default target |
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[450] | 212 | |
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[693] | 213 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 214 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 215 | << x_id << "_" << y_id; |
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| 216 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 217 | dspin_int_cmd_width, |
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| 218 | dspin_int_rsp_width>( |
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| 219 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 220 | x_width + y_width + l_width); |
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[450] | 221 | |
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[693] | 222 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 223 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 224 | << x_id << "_" << y_id; |
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| 225 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 226 | dspin_int_cmd_width, |
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| 227 | dspin_int_rsp_width>( |
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| 228 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 229 | x_width + y_width + l_width); |
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| 230 | |
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[450] | 231 | //////////// Coherence LOCAL_XBAR(S) |
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| 232 | std::ostringstream s_int_xbar_m2p_c; |
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| 233 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 234 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 235 | s_int_xbar_m2p_c.str().c_str(), |
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| 236 | mt_int, // mapping table |
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| 237 | x_id, y_id, // cluster coordinates |
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| 238 | x_width, y_width, l_width, // several dests |
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| 239 | 1, // number of local sources |
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[802] | 240 | nb_procs, // number of local dests |
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| 241 | 2, 2, // fifo depths |
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[450] | 242 | true, // pseudo CMD |
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| 243 | false, // no routing table |
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| 244 | true ); // broacast |
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| 245 | |
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| 246 | std::ostringstream s_int_xbar_p2m_c; |
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| 247 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 248 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 249 | s_int_xbar_p2m_c.str().c_str(), |
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| 250 | mt_int, // mapping table |
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| 251 | x_id, y_id, // cluster coordinates |
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| 252 | x_width, y_width, 0, // only one dest |
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| 253 | nb_procs, // number of local sources |
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| 254 | 1, // number of local dests |
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[802] | 255 | 2, 2, // fifo depths |
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[450] | 256 | false, // pseudo RSP |
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| 257 | false, // no routing table |
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[802] | 258 | false ); // no broacast |
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[450] | 259 | |
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[468] | 260 | std::ostringstream s_int_xbar_clack_c; |
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| 261 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 262 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 263 | s_int_xbar_clack_c.str().c_str(), |
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| 264 | mt_int, // mapping table |
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| 265 | x_id, y_id, // cluster coordinates |
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| 266 | x_width, y_width, l_width, |
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| 267 | 1, // number of local sources |
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[802] | 268 | nb_procs, // number of local targets |
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[468] | 269 | 1, 1, // fifo depths |
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| 270 | true, // CMD |
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[707] | 271 | false, // no routing table |
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[468] | 272 | false); // broadcast |
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| 273 | |
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[450] | 274 | ////////////// INT ROUTER(S) |
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| 275 | std::ostringstream s_int_router_cmd; |
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| 276 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 277 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 278 | s_int_router_cmd.str().c_str(), |
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| 279 | x_id,y_id, // coordinate in the mesh |
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| 280 | x_width, y_width, // x & y fields width |
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[468] | 281 | 3, // nb virtual channels |
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[450] | 282 | 4,4); // input & output fifo depths |
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| 283 | |
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| 284 | std::ostringstream s_int_router_rsp; |
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| 285 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 286 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 287 | s_int_router_rsp.str().c_str(), |
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[550] | 288 | x_id,y_id, // router coordinates in mesh |
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[450] | 289 | x_width, y_width, // x & y fields width |
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[468] | 290 | 2, // nb virtual channels |
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[450] | 291 | 4,4); // input & output fifo depths |
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| 292 | |
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| 293 | ////////////// XRAM |
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| 294 | std::ostringstream s_xram; |
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| 295 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 296 | xram = new VciSimpleRam<vci_param_ext>( |
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| 297 | s_xram.str().c_str(), |
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[718] | 298 | IntTab(cluster_id, ram_xram_tgt_id), |
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[450] | 299 | mt_ram, |
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| 300 | loader, |
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| 301 | xram_latency); |
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| 302 | |
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| 303 | std::ostringstream s_wt_xram; |
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| 304 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 305 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 306 | dspin_ram_cmd_width, |
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| 307 | dspin_ram_rsp_width>( |
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| 308 | s_wt_xram.str().c_str(), |
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| 309 | x_width + y_width + l_width); |
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| 310 | |
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| 311 | ///////////// RAM ROUTER(S) |
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| 312 | std::ostringstream s_ram_router_cmd; |
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| 313 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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[718] | 314 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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[450] | 315 | s_ram_router_cmd.str().c_str(), |
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[584] | 316 | x_id, y_id, // router coordinates in mesh |
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| 317 | x_width, // x field width in first flit |
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| 318 | y_width, // y field width in first flit |
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[718] | 319 | 4, 4); // input & output fifo depths |
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[450] | 320 | |
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| 321 | std::ostringstream s_ram_router_rsp; |
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| 322 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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[718] | 323 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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[450] | 324 | s_ram_router_rsp.str().c_str(), |
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[584] | 325 | x_id, y_id, // coordinates in mesh |
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| 326 | x_width, // x field width in first flit |
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| 327 | y_width, // y field width in first flit |
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[718] | 328 | 4, 4); // input & output fifo depths |
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[450] | 329 | |
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[550] | 330 | |
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[450] | 331 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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[718] | 332 | if ( is_io ) |
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[450] | 333 | { |
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| 334 | /////////// IO_BRIDGE |
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| 335 | std::ostringstream s_iob; |
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[802] | 336 | s_iob << "iob_" << x_id << "_" << y_id; |
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[450] | 337 | iob = new VciIoBridge<vci_param_int, |
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[802] | 338 | vci_param_ext>( |
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[450] | 339 | s_iob.str().c_str(), |
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[718] | 340 | mt_ram, // EXT network maptab |
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| 341 | mt_int, // INT network maptab |
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| 342 | mt_iox, // IOX network maptab |
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| 343 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
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| 344 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
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| 345 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
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| 346 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
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| 347 | 16, // cache line words |
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| 348 | 8, // IOTLB ways |
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| 349 | 8, // IOTLB sets |
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[450] | 350 | debug_start_cycle, |
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| 351 | iob_debug_ok ); |
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[802] | 352 | |
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[450] | 353 | std::ostringstream s_iob_ram_wi; |
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[802] | 354 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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[450] | 355 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 356 | dspin_ram_cmd_width, |
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| 357 | dspin_ram_rsp_width>( |
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| 358 | s_iob_ram_wi.str().c_str(), |
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[718] | 359 | vci_param_int::S); |
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| 360 | |
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| 361 | std::ostringstream s_ram_xbar_cmd; |
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| 362 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
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| 363 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
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| 364 | s_ram_xbar_cmd.str().c_str(), // name |
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| 365 | mt_ram, // mapping table |
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| 366 | x_id, y_id, // x, y |
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| 367 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 368 | 2, 0, // local inputs, local outputs |
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| 369 | 2, 2, // in fifo, out fifo depths |
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| 370 | true, // is cmd ? |
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| 371 | false, // use routing table ? |
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| 372 | false); // support broadcast ? |
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| 373 | |
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| 374 | std::ostringstream s_ram_xbar_rsp; |
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| 375 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
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| 376 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
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| 377 | s_ram_xbar_rsp.str().c_str(), // name |
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| 378 | mt_ram, // mapping table |
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| 379 | x_id, y_id, // x, y |
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| 380 | x_width, y_width, l_width, // x_width, y_width, l_width |
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| 381 | 0, 2, // local inputs, local outputs |
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| 382 | 2, 2, // in fifo, out fifo depths |
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| 383 | false, // is cmd ? |
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| 384 | true, // use routing table ? |
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| 385 | false); // support broadcast ? |
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[550] | 386 | } // end if IO |
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[450] | 387 | |
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| 388 | //////////////////////////////////// |
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| 389 | // Connections are defined here |
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| 390 | //////////////////////////////////// |
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| 391 | |
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| 392 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 393 | // : local srcid[memc] = nb_procs |
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[802] | 394 | |
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[450] | 395 | //////////////////////// internal CMD & RSP routers |
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| 396 | int_router_cmd->p_clk (this->p_clk); |
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| 397 | int_router_cmd->p_resetn (this->p_resetn); |
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| 398 | int_router_rsp->p_clk (this->p_clk); |
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| 399 | int_router_rsp->p_resetn (this->p_resetn); |
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[468] | 400 | |
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| 401 | for (int i = 0; i < 4; i++) |
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[450] | 402 | { |
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[468] | 403 | for(int k = 0; k < 3; k++) |
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[450] | 404 | { |
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[468] | 405 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 406 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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[450] | 407 | } |
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[468] | 408 | |
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| 409 | for(int k = 0; k < 2; k++) |
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| 410 | { |
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| 411 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 412 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 413 | } |
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[450] | 414 | } |
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| 415 | |
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| 416 | // local ports |
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[468] | 417 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 418 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 419 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 420 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 421 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 422 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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[802] | 423 | |
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[468] | 424 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 425 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 426 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 427 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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[450] | 428 | |
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| 429 | ///////////////////// CMD DSPIN local crossbar direct |
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[693] | 430 | int_xbar_d->p_clk (this->p_clk); |
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| 431 | int_xbar_d->p_resetn (this->p_resetn); |
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| 432 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
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| 433 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
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[450] | 434 | |
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[718] | 435 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
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| 436 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
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| 437 | int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); |
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| 438 | int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); |
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[450] | 439 | for (size_t p = 0; p < nb_procs; p++) |
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[718] | 440 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
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[450] | 441 | |
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[718] | 442 | if ( is_io ) |
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[450] | 443 | { |
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[718] | 444 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
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| 445 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
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[450] | 446 | } |
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| 447 | |
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[714] | 448 | int_wi_gate_d->p_clk (this->p_clk); |
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| 449 | int_wi_gate_d->p_resetn (this->p_resetn); |
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| 450 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
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| 451 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
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| 452 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
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[450] | 453 | |
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[714] | 454 | int_wt_gate_d->p_clk (this->p_clk); |
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| 455 | int_wt_gate_d->p_resetn (this->p_resetn); |
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| 456 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 457 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
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| 458 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
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[802] | 459 | |
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[450] | 460 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 461 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 462 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
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| 463 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
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| 464 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 465 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
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[802] | 466 | for (size_t p = 0; p < nb_procs; p++) |
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[450] | 467 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 468 | |
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| 469 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 470 | int_xbar_p2m_c->p_clk (this->p_clk); |
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| 471 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 472 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 473 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
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| 474 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
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[802] | 475 | for (size_t p = 0; p < nb_procs; p++) |
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[450] | 476 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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| 477 | |
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[468] | 478 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 479 | int_xbar_clack_c->p_clk (this->p_clk); |
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| 480 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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| 481 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
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| 482 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
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| 483 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
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| 484 | for (size_t p = 0; p < nb_procs; p++) |
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| 485 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
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| 486 | |
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[450] | 487 | //////////////////////////////////// Processors |
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| 488 | for (size_t p = 0; p < nb_procs; p++) |
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| 489 | { |
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| 490 | proc[p]->p_clk (this->p_clk); |
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| 491 | proc[p]->p_resetn (this->p_resetn); |
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| 492 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
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[468] | 493 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
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| 494 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
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| 495 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
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[707] | 496 | |
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| 497 | for ( size_t j = 0 ; j < 6 ; j++) |
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[450] | 498 | { |
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[707] | 499 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
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| 500 | else proc[p]->p_irq[j] (signal_false); |
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[450] | 501 | } |
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| 502 | } |
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| 503 | |
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| 504 | ///////////////////////////////////// XICU |
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[468] | 505 | xicu->p_clk (this->p_clk); |
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| 506 | xicu->p_resetn (this->p_resetn); |
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| 507 | xicu->p_vci (signal_int_vci_tgt_xicu); |
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[959] | 508 | for ( size_t i=0 ; i < xcu_nb_out ; i++) |
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[450] | 509 | { |
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[714] | 510 | xicu->p_irq[i] (signal_proc_it[i]); |
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[450] | 511 | } |
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[959] | 512 | for ( size_t i=0 ; i < xcu_nb_hwi ; i++) |
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[450] | 513 | { |
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[707] | 514 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
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| 515 | else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
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| 516 | else xicu->p_hwi[i] (signal_false); |
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[802] | 517 | } |
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[450] | 518 | |
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| 519 | ///////////////////////////////////// MEMC |
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[468] | 520 | memc->p_clk (this->p_clk); |
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| 521 | memc->p_resetn (this->p_resetn); |
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| 522 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
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| 523 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
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| 524 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
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| 525 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
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| 526 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
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[607] | 527 | memc->p_irq (signal_irq_memc); |
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[450] | 528 | |
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| 529 | // wrapper to RAM network |
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| 530 | memc_ram_wi->p_clk (this->p_clk); |
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| 531 | memc_ram_wi->p_resetn (this->p_resetn); |
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| 532 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
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| 533 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
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| 534 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
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| 535 | |
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| 536 | //////////////////////////////////// XRAM |
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[468] | 537 | xram->p_clk (this->p_clk); |
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| 538 | xram->p_resetn (this->p_resetn); |
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| 539 | xram->p_vci (signal_ram_vci_tgt_xram); |
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[450] | 540 | |
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| 541 | // wrapper to RAM network |
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| 542 | xram_ram_wt->p_clk (this->p_clk); |
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| 543 | xram_ram_wt->p_resetn (this->p_resetn); |
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| 544 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
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| 545 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
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| 546 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
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| 547 | |
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| 548 | /////////////////////////////////// MDMA |
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[468] | 549 | mdma->p_clk (this->p_clk); |
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[450] | 550 | mdma->p_resetn (this->p_resetn); |
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[468] | 551 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
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| 552 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
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[450] | 553 | for (size_t i=0 ; i<nb_dmas ; i++) |
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| 554 | mdma->p_irq[i] (signal_irq_mdma[i]); |
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| 555 | |
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[550] | 556 | //////////////////////////// RAM network CMD & RSP routers |
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[707] | 557 | ram_router_cmd->p_clk (this->p_clk); |
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| 558 | ram_router_cmd->p_resetn (this->p_resetn); |
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| 559 | ram_router_rsp->p_clk (this->p_clk); |
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| 560 | ram_router_rsp->p_resetn (this->p_resetn); |
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[550] | 561 | for( size_t n=0 ; n<4 ; n++) |
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[450] | 562 | { |
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[707] | 563 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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| 564 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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| 565 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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| 566 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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[450] | 567 | } |
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[718] | 568 | |
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[707] | 569 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
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| 570 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
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[718] | 571 | |
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| 572 | if ( is_io ) |
---|
| 573 | { |
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| 574 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
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| 575 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
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| 576 | } |
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| 577 | else |
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| 578 | { |
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| 579 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
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| 580 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
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| 581 | } |
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[802] | 582 | |
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| 583 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
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[718] | 584 | if ( is_io ) |
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[450] | 585 | { |
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| 586 | // IO bridge |
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[718] | 587 | iob->p_clk (this->p_clk); |
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| 588 | iob->p_resetn (this->p_resetn); |
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| 589 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
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| 590 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
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| 591 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
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| 592 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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| 593 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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[550] | 594 | |
---|
[450] | 595 | // initiator wrapper to RAM network |
---|
[718] | 596 | iob_ram_wi->p_clk (this->p_clk); |
---|
| 597 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
| 598 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
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| 599 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
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| 600 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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| 601 | |
---|
| 602 | // crossbar between MEMC and IOB to RAM network |
---|
| 603 | ram_xbar_cmd->p_clk (this->p_clk); |
---|
| 604 | ram_xbar_cmd->p_resetn (this->p_resetn); |
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| 605 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
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| 606 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
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| 607 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
---|
| 608 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
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| 609 | |
---|
| 610 | ram_xbar_rsp->p_clk (this->p_clk); |
---|
| 611 | ram_xbar_rsp->p_resetn (this->p_resetn); |
---|
| 612 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
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| 613 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
---|
| 614 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
---|
| 615 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
---|
[550] | 616 | } |
---|
[450] | 617 | |
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[739] | 618 | SC_METHOD(init); |
---|
| 619 | |
---|
[450] | 620 | } // end constructor |
---|
| 621 | |
---|
[718] | 622 | tmpl(void)::init() |
---|
| 623 | { |
---|
| 624 | signal_ram_dspin_cmd_false.write = false; |
---|
[739] | 625 | signal_ram_dspin_rsp_false.read = true; |
---|
[718] | 626 | } // end init |
---|
| 627 | |
---|
[450] | 628 | }} |
---|
| 629 | |
---|
| 630 | |
---|
| 631 | // Local Variables: |
---|
| 632 | // tab-width: 3 |
---|
| 633 | // c-basic-offset: 3 |
---|
| 634 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 635 | // indent-tabs-mode: nil |
---|
| 636 | // End: |
---|
| 637 | |
---|
| 638 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 639 | |
---|