1 | ////////////////////////////////////////////////////////////////////////////// |
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2 | // File: tsar_iob_cluster.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : april 2013 |
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6 | // This program is released under the GNU public license |
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7 | ////////////////////////////////////////////////////////////////////////////// |
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8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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9 | // These two clusters contain 6 extra components: |
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10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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11 | // - 3 vci_dspin_wrapper for the IOB. |
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12 | // - 2 dspin_local_crossbar for commands and responses. |
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13 | ////////////////////////////////////////////////////////////////////////////// |
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14 | |
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15 | #include "../include/tsar_iob_cluster.h" |
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16 | |
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17 | #define MWR_COPROC_CPY 0 |
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18 | #define MWR_COPROC_DCT 1 |
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19 | #define MWR_COPROC_GCD 2 |
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20 | |
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21 | #define tmpl(x) \ |
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22 | template<typename vci_param_int , typename vci_param_ext,\ |
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23 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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24 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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25 | x TsarIobCluster<\ |
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26 | vci_param_int , vci_param_ext,\ |
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27 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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28 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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29 | |
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30 | namespace soclib { namespace caba { |
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31 | |
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32 | ///////////////////////////////////////////////////////////////////////////// |
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33 | tmpl(/**/)::TsarIobCluster( |
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34 | ///////////////////////////////////////////////////////////////////////////// |
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35 | sc_module_name insname, |
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36 | size_t nb_procs, |
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37 | size_t x_id, |
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38 | size_t y_id, |
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39 | size_t xmax, |
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40 | size_t ymax, |
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41 | |
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42 | const soclib::common::MappingTable &mt_int, |
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43 | const soclib::common::MappingTable &mt_ram, |
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44 | const soclib::common::MappingTable &mt_iox, |
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45 | |
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46 | size_t x_width, |
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47 | size_t y_width, |
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48 | size_t l_width, |
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49 | size_t p_width, |
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50 | |
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51 | size_t int_memc_tgt_id, // local index |
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52 | size_t int_xicu_tgt_id, // local index |
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53 | size_t int_mwmr_tgt_id, // local index |
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54 | size_t int_iobx_tgt_id, // local index |
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55 | |
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56 | size_t int_proc_ini_id, // local index |
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57 | size_t int_mwmr_ini_id, // local index |
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58 | size_t int_iobx_ini_id, // local index |
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59 | |
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60 | size_t ram_xram_tgt_id, // local index |
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61 | size_t ram_memc_ini_id, // local index |
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62 | size_t ram_iobx_ini_id, // local index |
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63 | |
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64 | bool is_io, // is IO cluster (IOB)? |
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65 | size_t iox_iobx_tgt_id, // local_index |
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66 | size_t iox_iobx_ini_id, // local index |
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67 | |
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68 | size_t memc_ways, |
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69 | size_t memc_sets, |
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70 | size_t l1_i_ways, |
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71 | size_t l1_i_sets, |
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72 | size_t l1_d_ways, |
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73 | size_t l1_d_sets, |
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74 | size_t xram_latency, |
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75 | size_t xcu_nb_hwi, |
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76 | size_t xcu_nb_pti, |
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77 | size_t xcu_nb_wti, |
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78 | size_t xcu_nb_out, |
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79 | |
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80 | size_t coproc_type, |
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81 | |
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82 | const Loader &loader, |
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83 | |
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84 | uint32_t frozen_cycles, |
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85 | bool debug_ok, |
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86 | uint32_t debug_start_cycle, |
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87 | uint32_t debug_proc_id, |
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88 | uint32_t debug_memc_id, |
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89 | bool debug_iob ) |
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90 | : soclib::caba::BaseModule(insname), |
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91 | p_clk("clk"), |
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92 | p_resetn("resetn") |
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93 | { |
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94 | assert( (x_id < xmax) and (y_id < ymax) and |
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95 | "Error in tsar_iob_cluster : Illegal cluster coordinates"); |
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96 | |
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97 | size_t cluster_id = (x_id<<4) + y_id; |
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98 | |
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99 | // Vectors of DSPIN ports for inter-cluster communications |
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100 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4); |
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101 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4); |
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102 | |
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103 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4); |
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104 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4); |
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105 | |
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106 | p_dspin_int_m2p_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_m2p_in", 4); |
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107 | p_dspin_int_m2p_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_m2p_out", 4); |
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108 | |
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109 | p_dspin_int_p2m_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_p2m_in", 4); |
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110 | p_dspin_int_p2m_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_p2m_out", 4); |
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111 | |
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112 | p_dspin_int_cla_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cla_in", 4); |
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113 | p_dspin_int_cla_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cla_out", 4); |
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114 | |
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115 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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116 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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117 | |
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118 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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119 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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120 | |
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121 | // VCI ports from IOB to IOX network (only in IO clusters) |
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122 | if ( is_io ) |
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123 | { |
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124 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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125 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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126 | } |
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127 | |
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128 | ////////////////////////////////////////////////////////////////////////////////// |
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129 | // Hardware components |
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130 | ////////////////////////////////////////////////////////////////////////////////// |
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131 | |
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132 | size_t x_debug; |
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133 | size_t y_debug; |
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134 | size_t p_debug; |
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135 | |
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136 | //////////// PROCS ///////////////////////////////////////////////////////////// |
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137 | for (size_t p = 0; p < nb_procs; p++) |
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138 | { |
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139 | std::ostringstream s_proc; |
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140 | x_debug = (debug_proc_id >> (y_width + p_width)) & ((1<<x_width)-1); |
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141 | y_debug = (debug_proc_id >> p_width ) & ((1<<y_width)-1); |
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142 | p_debug = (debug_proc_id ) & ((1<<p_width)-1); |
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143 | |
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144 | |
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145 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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146 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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147 | dspin_int_cmd_width, |
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148 | dspin_int_rsp_width, |
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149 | GdbServer<Mips32ElIss> >( |
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150 | s_proc.str().c_str(), |
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151 | (cluster_id << p_width) + p, // GLOBAL PROC_ID |
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152 | mt_int, // Mapping Table INT network |
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153 | IntTab(cluster_id,p), // SRCID |
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154 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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155 | 8, // ITLB ways |
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156 | 8, // ITLB sets |
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157 | 8, // DTLB ways |
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158 | 8, // DTLB sets |
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159 | l1_i_ways, l1_i_sets, 16, // ICACHE size |
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160 | l1_d_ways, l1_d_sets, 16, // DCACHE size |
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161 | 4, // WBUF nlines |
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162 | 4, // WBUF nwords |
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163 | x_width, |
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164 | y_width, |
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165 | frozen_cycles, // max frozen cycles |
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166 | debug_start_cycle, |
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167 | debug_ok and (x_id == x_debug) and (y_id == y_debug) and (p_debug == p) ); |
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168 | } |
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169 | |
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170 | //////////// MEMC ///////////////////////////////////////////////////////////// |
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171 | std::ostringstream s_memc; |
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172 | s_memc << "memc_" << x_id << "_" << y_id; |
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173 | x_debug = (debug_memc_id >> y_width) & ((1<<x_width)-1); |
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174 | y_debug = (debug_memc_id ) & ((1<<y_width)-1); |
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175 | memc = new VciMemCache<vci_param_int, |
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176 | vci_param_ext, |
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177 | dspin_int_rsp_width, |
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178 | dspin_int_cmd_width>( |
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179 | s_memc.str().c_str(), |
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180 | mt_int, // Mapping Table INT network |
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181 | mt_ram, // Mapping Table RAM network |
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182 | IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network |
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183 | IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network |
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184 | x_width, // number of bits for x coordinate |
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185 | y_width, // number of bits for y coordinate |
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186 | memc_ways, memc_sets, 16, // CACHE SIZE |
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187 | 3, // MAX NUMBER OF COPIES |
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188 | 4096, // HEAP SIZE |
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189 | 8, // TRANSACTION TABLE DEPTH |
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190 | 8, // UPDATE TABLE DEPTH |
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191 | 8, // INVALIDATE TABLE DEPTH |
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192 | debug_start_cycle, |
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193 | debug_ok and (x_id == x_debug) and (y_id == y_debug) ); |
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194 | |
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195 | std::ostringstream s_wi_memc; |
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196 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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197 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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198 | dspin_ram_cmd_width, |
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199 | dspin_ram_rsp_width>( |
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200 | s_wi_memc.str().c_str(), |
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201 | x_width + y_width + l_width); |
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202 | |
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203 | /////////// XICU ////////////////////////////////////////////////////////////// |
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204 | std::ostringstream s_xicu; |
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205 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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206 | xicu = new VciXicu<vci_param_int>( |
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207 | s_xicu.str().c_str(), |
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208 | mt_int, // mapping table INT network |
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209 | IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space |
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210 | xcu_nb_pti, // number of timer IRQs |
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211 | xcu_nb_hwi, // number of hard IRQs |
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212 | xcu_nb_wti, // number of soft IRQs |
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213 | xcu_nb_out); // number of output IRQs |
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214 | |
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215 | //////////// MWMR controller and COPROC //////////////////////////////////////// |
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216 | std::ostringstream s_mwmr; |
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217 | std::ostringstream s_copro; |
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218 | s_mwmr << "mwmr_" << x_id << "_" << y_id; |
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219 | |
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220 | if ( coproc_type == MWR_COPROC_CPY) |
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221 | { |
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222 | s_copro << "cpy_" << x_id << "_" << y_id; |
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223 | cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size |
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224 | |
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225 | mwmr = new VciMwmrDma<vci_param_int>( |
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226 | s_mwmr.str().c_str(), |
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227 | mt_int, |
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228 | IntTab(cluster_id, int_mwmr_ini_id), // SRCID |
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229 | IntTab(cluster_id, int_mwmr_tgt_id), // TGTID |
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230 | 1, // nb to_coproc ports |
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231 | 1, // nb from_coproc ports |
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232 | 1, // nb config registers |
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233 | 0, // nb status registers |
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234 | 64 ); // burst size (bytes) |
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235 | } |
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236 | if ( coproc_type == MWR_COPROC_DCT ) |
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237 | { |
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238 | s_copro << "dct_" << x_id << "_" << y_id; |
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239 | dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency |
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240 | |
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241 | mwmr = new VciMwmrDma<vci_param_int>( |
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242 | s_mwmr.str().c_str(), |
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243 | mt_int, |
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244 | IntTab(cluster_id, int_mwmr_ini_id), // SRCID |
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245 | IntTab(cluster_id, int_mwmr_tgt_id), // TGTID |
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246 | 1, // nb to_coproc ports |
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247 | 1, // nb from_coproc ports |
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248 | 1, // nb config registers |
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249 | 0, // nb status registers |
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250 | 64 ); // burst size (bytes) |
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251 | } |
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252 | if ( coproc_type == MWR_COPROC_GCD ) |
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253 | { |
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254 | s_copro << "gcd_" << x_id << "_" << y_id; |
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255 | gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size |
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256 | |
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257 | mwmr = new VciMwmrDma<vci_param_int>( |
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258 | s_mwmr.str().c_str(), |
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259 | mt_int, |
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260 | IntTab(cluster_id, int_mwmr_ini_id), // SRCID |
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261 | IntTab(cluster_id, int_mwmr_tgt_id), // TGTID |
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262 | 2, // nb to_coproc ports |
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263 | 1, // nb from_coproc ports |
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264 | 1, // nb config registers |
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265 | 0, // nb status registers |
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266 | 64 ); // burst size (bytes) |
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267 | } |
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268 | |
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269 | /////////// VCI INT_CMD/RSP LOCAL_XBAR ////////////////////////////////////// |
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270 | size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; |
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271 | size_t nb_direct_targets = is_io ? 4 : 3; |
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272 | |
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273 | std::ostringstream s_int_xbar_d; |
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274 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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275 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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276 | s_int_xbar_d.str().c_str(), |
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277 | mt_int, // mapping table |
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278 | cluster_id, // cluster id |
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279 | nb_direct_initiators, // number of local initiators |
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280 | nb_direct_targets, // number of local targets |
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281 | 0 ); // default target |
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282 | |
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283 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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284 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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285 | << x_id << "_" << y_id; |
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286 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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287 | dspin_int_cmd_width, |
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288 | dspin_int_rsp_width>( |
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289 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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290 | x_width + y_width + l_width); |
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291 | |
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292 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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293 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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294 | << x_id << "_" << y_id; |
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295 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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296 | dspin_int_cmd_width, |
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297 | dspin_int_rsp_width>( |
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298 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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299 | x_width + y_width + l_width); |
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300 | |
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301 | //////////// DSPIN INT_M2P LOCAL_XBAR //////////////////////////////////////// |
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302 | std::ostringstream s_int_xbar_m2p_c; |
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303 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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304 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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305 | s_int_xbar_m2p_c.str().c_str(), |
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306 | mt_int, // mapping table |
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307 | x_id, y_id, // cluster coordinates |
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308 | x_width, y_width, l_width, // several dests |
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309 | 1, // number of local sources |
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310 | nb_procs, // number of local dests |
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311 | 2, 2, // fifo depths |
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312 | true, // pseudo CMD |
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313 | false, // no routing table |
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314 | true ); // broacast |
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315 | |
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316 | //////////// DSPIN INT_P2M LOCAL_XBAR //////////////////////////////////////// |
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317 | std::ostringstream s_int_xbar_p2m_c; |
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318 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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319 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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320 | s_int_xbar_p2m_c.str().c_str(), |
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321 | mt_int, // mapping table |
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322 | x_id, y_id, // cluster coordinates |
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323 | x_width, y_width, 0, // only one dest |
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324 | nb_procs, // number of local sources |
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325 | 1, // number of local dests |
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326 | 2, 2, // fifo depths |
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327 | false, // pseudo RSP |
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328 | false, // no routing table |
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329 | false ); // no broacast |
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330 | |
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331 | //////////// DSPIN INT_CLA LOCAL_XBAR //////////////////////////////////////// |
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332 | std::ostringstream s_int_xbar_clack_c; |
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333 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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334 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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335 | s_int_xbar_clack_c.str().c_str(), |
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336 | mt_int, // mapping table |
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337 | x_id, y_id, // cluster coordinates |
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338 | x_width, y_width, l_width, |
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339 | 1, // number of local sources |
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340 | nb_procs, // number of local targets |
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341 | 1, 1, // fifo depths |
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342 | true, // CMD |
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343 | false, // no routing table |
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344 | false); // broadcast |
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345 | |
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346 | //////////// DSPIN INT_CMD ROUTER //////////////////////////////////////////// |
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347 | std::ostringstream s_int_router_cmd; |
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348 | s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id; |
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349 | int_router_cmd = new DspinRouter<dspin_int_cmd_width>( |
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350 | s_int_router_cmd.str().c_str(), |
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351 | x_id,y_id, // coordinate in the mesh |
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352 | x_width, y_width, // x & y fields width |
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353 | 4,4); // input & output fifo depths |
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354 | |
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355 | //////////// DSPIN INT_RSP ROUTER //////////////////////////////////////////// |
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356 | std::ostringstream s_int_router_rsp; |
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357 | s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id; |
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358 | int_router_rsp = new DspinRouter<dspin_int_rsp_width>( |
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359 | s_int_router_rsp.str().c_str(), |
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360 | x_id,y_id, // coordinates in mesh |
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361 | x_width, y_width, // x & y fields width |
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362 | 4,4); // input & output fifo depths |
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363 | |
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364 | //////////// DSPIN INT_M2P ROUTER //////////////////////////////////////////// |
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365 | std::ostringstream s_int_router_m2p; |
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366 | s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id; |
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367 | int_router_m2p = new DspinRouter<dspin_int_cmd_width>( |
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368 | s_int_router_m2p.str().c_str(), |
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369 | x_id,y_id, // coordinate in the mesh |
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370 | x_width, y_width, // x & y fields width |
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371 | 4,4, // input & output fifo depths |
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372 | true); // broadcast supported |
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373 | |
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374 | //////////// DSPIN INT_P2M ROUTER //////////////////////////////////////////// |
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375 | std::ostringstream s_int_router_p2m; |
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376 | s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id; |
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377 | int_router_p2m = new DspinRouter<dspin_int_rsp_width>( |
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378 | s_int_router_p2m.str().c_str(), |
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379 | x_id,y_id, // coordinates in mesh |
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380 | x_width, y_width, // x & y fields width |
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381 | 4,4); // input & output fifo depths |
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382 | |
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383 | //////////// DSPIN INT_CLA ROUTER //////////////////////////////////////////// |
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384 | std::ostringstream s_int_router_cla; |
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385 | s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id; |
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386 | int_router_cla = new DspinRouter<dspin_int_cmd_width>( |
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387 | s_int_router_cla.str().c_str(), |
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388 | x_id,y_id, // coordinate in the mesh |
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389 | x_width, y_width, // x & y fields width |
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390 | 4,4); // input & output fifo depths |
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391 | |
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392 | ////////////// XRAM ///////////////////////////////////////////////////////// |
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393 | std::ostringstream s_xram; |
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394 | s_xram << "xram_" << x_id << "_" << y_id; |
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395 | xram = new VciSimpleRam<vci_param_ext>( |
---|
396 | s_xram.str().c_str(), |
---|
397 | IntTab(cluster_id, ram_xram_tgt_id), |
---|
398 | mt_ram, |
---|
399 | loader, |
---|
400 | xram_latency); |
---|
401 | |
---|
402 | std::ostringstream s_wt_xram; |
---|
403 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
---|
404 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
---|
405 | dspin_ram_cmd_width, |
---|
406 | dspin_ram_rsp_width>( |
---|
407 | s_wt_xram.str().c_str(), |
---|
408 | x_width + y_width + l_width); |
---|
409 | |
---|
410 | //////////// DSPIN RAM_CMD ROUTER /////////////////////////////////////////// |
---|
411 | std::ostringstream s_ram_router_cmd; |
---|
412 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
---|
413 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
---|
414 | s_ram_router_cmd.str().c_str(), |
---|
415 | x_id, y_id, // router coordinates in mesh |
---|
416 | x_width, // x field width in first flit |
---|
417 | y_width, // y field width in first flit |
---|
418 | 4, 4); // input & output fifo depths |
---|
419 | |
---|
420 | //////////// DSPIN RAM_RSP ROUTER /////////////////////////////////////////// |
---|
421 | std::ostringstream s_ram_router_rsp; |
---|
422 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
---|
423 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
---|
424 | s_ram_router_rsp.str().c_str(), |
---|
425 | x_id, y_id, // coordinates in mesh |
---|
426 | x_width, // x field width in first flit |
---|
427 | y_width, // y field width in first flit |
---|
428 | 4, 4); // input & output fifo depths |
---|
429 | |
---|
430 | |
---|
431 | ////////////////////// I/O CLUSTER ONLY /////////////////////////////////// |
---|
432 | if ( is_io ) |
---|
433 | { |
---|
434 | /////////// IO_BRIDGE //////////////////////////////////////////////////// |
---|
435 | std::ostringstream s_iob; |
---|
436 | s_iob << "iob_" << x_id << "_" << y_id; |
---|
437 | iob = new VciIoBridge<vci_param_int, |
---|
438 | vci_param_ext>( |
---|
439 | s_iob.str().c_str(), |
---|
440 | mt_ram, // EXT network maptab |
---|
441 | mt_int, // INT network maptab |
---|
442 | mt_iox, // IOX network maptab |
---|
443 | IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID |
---|
444 | IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID |
---|
445 | IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID |
---|
446 | IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID |
---|
447 | 16, // cache line words |
---|
448 | 8, // IOTLB ways |
---|
449 | 8, // IOTLB sets |
---|
450 | debug_start_cycle, |
---|
451 | debug_iob ); |
---|
452 | |
---|
453 | std::ostringstream s_iob_ram_wi; |
---|
454 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
---|
455 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
---|
456 | dspin_ram_cmd_width, |
---|
457 | dspin_ram_rsp_width>( |
---|
458 | s_iob_ram_wi.str().c_str(), |
---|
459 | vci_param_int::S); |
---|
460 | |
---|
461 | //////////// DSPIN RAM_CMD LOCAL_XBAR /////////////////////////////////// |
---|
462 | std::ostringstream s_ram_xbar_cmd; |
---|
463 | s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; |
---|
464 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
---|
465 | s_ram_xbar_cmd.str().c_str(), // name |
---|
466 | mt_ram, // mapping table |
---|
467 | x_id, y_id, // x, y |
---|
468 | x_width, y_width, l_width, // x_width, y_width, l_width |
---|
469 | 2, 0, // local inputs, local outputs |
---|
470 | 2, 2, // in fifo, out fifo depths |
---|
471 | true, // is cmd ? |
---|
472 | false, // use routing table ? |
---|
473 | false); // support broadcast ? |
---|
474 | |
---|
475 | //////////// DSPIN RAM_RSP LOCAL_XBAR /////////////////////////////////// |
---|
476 | std::ostringstream s_ram_xbar_rsp; |
---|
477 | s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; |
---|
478 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
---|
479 | s_ram_xbar_rsp.str().c_str(), // name |
---|
480 | mt_ram, // mapping table |
---|
481 | x_id, y_id, // x, y |
---|
482 | x_width, y_width, l_width, // x_width, y_width, l_width |
---|
483 | 0, 2, // local inputs, local outputs |
---|
484 | 2, 2, // in fifo, out fifo depths |
---|
485 | false, // is cmd ? |
---|
486 | true, // use routing table ? |
---|
487 | false); // support broadcast ? |
---|
488 | |
---|
489 | } // end if IO |
---|
490 | |
---|
491 | //////////////////////////////////// |
---|
492 | // Connections are defined here |
---|
493 | //////////////////////////////////// |
---|
494 | |
---|
495 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
496 | // : local srcid[memc] = nb_procs |
---|
497 | |
---|
498 | //////////////////////////////////// Processors |
---|
499 | for (size_t p = 0; p < nb_procs; p++) |
---|
500 | { |
---|
501 | proc[p]->p_clk (this->p_clk); |
---|
502 | proc[p]->p_resetn (this->p_resetn); |
---|
503 | |
---|
504 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
505 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
506 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
507 | proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]); |
---|
508 | |
---|
509 | for ( size_t j = 0 ; j < 6 ; j++) |
---|
510 | { |
---|
511 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
---|
512 | else proc[p]->p_irq[j] (signal_false); |
---|
513 | } |
---|
514 | } |
---|
515 | |
---|
516 | std::cout << " - processors connected" << std::endl; |
---|
517 | |
---|
518 | ///////////////////////////////////// XICU |
---|
519 | xicu->p_clk (this->p_clk); |
---|
520 | xicu->p_resetn (this->p_resetn); |
---|
521 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
522 | for ( size_t i=0 ; i < xcu_nb_out ; i++) |
---|
523 | { |
---|
524 | xicu->p_irq[i] (signal_proc_it[i]); |
---|
525 | } |
---|
526 | for ( size_t i=0 ; i < xcu_nb_hwi ; i++) |
---|
527 | { |
---|
528 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
---|
529 | else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr); |
---|
530 | else xicu->p_hwi[i] (signal_false); |
---|
531 | } |
---|
532 | |
---|
533 | std::cout << " - xcu connected" << std::endl; |
---|
534 | |
---|
535 | ///////////////////////////////////// MEMC |
---|
536 | memc->p_clk (this->p_clk); |
---|
537 | memc->p_resetn (this->p_resetn); |
---|
538 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
539 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
540 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
541 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
542 | memc->p_dspin_clack (signal_int_dspin_cla_memc); |
---|
543 | memc->p_irq (signal_irq_memc); |
---|
544 | |
---|
545 | // wrapper to RAM network |
---|
546 | memc_ram_wi->p_clk (this->p_clk); |
---|
547 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
548 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
549 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
550 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
551 | |
---|
552 | std::cout << " - memc connected" << std::endl; |
---|
553 | |
---|
554 | //////////////////////////////////// XRAM |
---|
555 | xram->p_clk (this->p_clk); |
---|
556 | xram->p_resetn (this->p_resetn); |
---|
557 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
558 | |
---|
559 | // wrapper to RAM network |
---|
560 | xram_ram_wt->p_clk (this->p_clk); |
---|
561 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
562 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
563 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
564 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
565 | |
---|
566 | std::cout << " - xram connected" << std::endl; |
---|
567 | |
---|
568 | /////////////////////////////////// GCD coprocessor |
---|
569 | if ( coproc_type == MWR_COPROC_GCD ) |
---|
570 | { |
---|
571 | gcd->p_clk (this->p_clk); |
---|
572 | gcd->p_resetn (this->p_resetn); |
---|
573 | gcd->p_opa (signal_to_coproc[0]); |
---|
574 | gcd->p_opb (signal_to_coproc[1]); |
---|
575 | gcd->p_res (signal_from_coproc[0]); |
---|
576 | gcd->p_config (signal_config_coproc[0]); |
---|
577 | |
---|
578 | mwmr->p_clk (this->p_clk); |
---|
579 | mwmr->p_resetn (this->p_resetn); |
---|
580 | mwmr->p_vci_target (signal_int_vci_tgt_mwmr); |
---|
581 | mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); |
---|
582 | mwmr->p_to_coproc[0] (signal_to_coproc[0]); |
---|
583 | mwmr->p_to_coproc[1] (signal_to_coproc[1]); |
---|
584 | mwmr->p_from_coproc[0] (signal_from_coproc[0]); |
---|
585 | mwmr->p_config[0] (signal_config_coproc[0]); |
---|
586 | mwmr->p_irq (signal_irq_mwmr); |
---|
587 | } |
---|
588 | |
---|
589 | /////////////////////////////////// DCT coprocessor |
---|
590 | if ( coproc_type == MWR_COPROC_DCT ) |
---|
591 | { |
---|
592 | dct->p_clk (this->p_clk); |
---|
593 | dct->p_resetn (this->p_resetn); |
---|
594 | dct->p_in (signal_to_coproc[0]); |
---|
595 | dct->p_out (signal_from_coproc[0]); |
---|
596 | dct->p_config (signal_config_coproc[0]); |
---|
597 | |
---|
598 | mwmr->p_clk (this->p_clk); |
---|
599 | mwmr->p_resetn (this->p_resetn); |
---|
600 | mwmr->p_vci_target (signal_int_vci_tgt_mwmr); |
---|
601 | mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); |
---|
602 | mwmr->p_to_coproc[0] (signal_to_coproc[0]); |
---|
603 | mwmr->p_from_coproc[0] (signal_from_coproc[0]); |
---|
604 | mwmr->p_config[0] (signal_config_coproc[0]); |
---|
605 | mwmr->p_irq (signal_irq_mwmr); |
---|
606 | } |
---|
607 | |
---|
608 | std::cout << " - coproc connected" << std::endl; |
---|
609 | |
---|
610 | /////////////////////////////////// CPY coprocessor |
---|
611 | if ( coproc_type == MWR_COPROC_CPY ) |
---|
612 | { |
---|
613 | cpy->p_clk (this->p_clk); |
---|
614 | cpy->p_resetn (this->p_resetn); |
---|
615 | cpy->p_load (signal_to_coproc[0]); |
---|
616 | cpy->p_store (signal_from_coproc[0]); |
---|
617 | cpy->p_config (signal_config_coproc[0]); |
---|
618 | |
---|
619 | mwmr->p_clk (this->p_clk); |
---|
620 | mwmr->p_resetn (this->p_resetn); |
---|
621 | mwmr->p_vci_target (signal_int_vci_tgt_mwmr); |
---|
622 | mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); |
---|
623 | mwmr->p_to_coproc[0] (signal_to_coproc[0]); |
---|
624 | mwmr->p_from_coproc[0] (signal_from_coproc[0]); |
---|
625 | mwmr->p_config[0] (signal_config_coproc[0]); |
---|
626 | mwmr->p_irq (signal_irq_mwmr); |
---|
627 | } |
---|
628 | |
---|
629 | //////////////////////////// RAM NETWORK ROUTERS |
---|
630 | ram_router_cmd->p_clk (this->p_clk); |
---|
631 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
632 | ram_router_rsp->p_clk (this->p_clk); |
---|
633 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
634 | |
---|
635 | for( size_t n=0 ; n<4 ; n++) |
---|
636 | { |
---|
637 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
638 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
639 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
640 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
641 | } |
---|
642 | |
---|
643 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
644 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
645 | |
---|
646 | if ( is_io ) |
---|
647 | { |
---|
648 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); |
---|
649 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); |
---|
650 | } |
---|
651 | else |
---|
652 | { |
---|
653 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
654 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
655 | } |
---|
656 | |
---|
657 | ///////////////////////////// INT NETWORK ROUTERS |
---|
658 | int_router_cmd->p_clk (this->p_clk); |
---|
659 | int_router_cmd->p_resetn (this->p_resetn); |
---|
660 | int_router_rsp->p_clk (this->p_clk); |
---|
661 | int_router_rsp->p_resetn (this->p_resetn); |
---|
662 | int_router_m2p->p_clk (this->p_clk); |
---|
663 | int_router_m2p->p_resetn (this->p_resetn); |
---|
664 | int_router_p2m->p_clk (this->p_clk); |
---|
665 | int_router_p2m->p_resetn (this->p_resetn); |
---|
666 | int_router_cla->p_clk (this->p_clk); |
---|
667 | int_router_cla->p_resetn (this->p_resetn); |
---|
668 | |
---|
669 | // loop on N/S/E/W ports |
---|
670 | for (size_t i = 0; i < 4; i++) |
---|
671 | { |
---|
672 | int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]); |
---|
673 | int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]); |
---|
674 | |
---|
675 | int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]); |
---|
676 | int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]); |
---|
677 | |
---|
678 | int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]); |
---|
679 | int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]); |
---|
680 | |
---|
681 | int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]); |
---|
682 | int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]); |
---|
683 | |
---|
684 | int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]); |
---|
685 | int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]); |
---|
686 | } |
---|
687 | |
---|
688 | int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d); |
---|
689 | int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d); |
---|
690 | |
---|
691 | int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d); |
---|
692 | int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d); |
---|
693 | |
---|
694 | int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c); |
---|
695 | int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c); |
---|
696 | |
---|
697 | int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c); |
---|
698 | int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c); |
---|
699 | |
---|
700 | int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c); |
---|
701 | int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c); |
---|
702 | |
---|
703 | std::cout << " - internal routers connected" << std::endl; |
---|
704 | |
---|
705 | |
---|
706 | ///////////////////// CMD DSPIN local crossbar direct |
---|
707 | int_xbar_d->p_clk (this->p_clk); |
---|
708 | int_xbar_d->p_resetn (this->p_resetn); |
---|
709 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
---|
710 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
---|
711 | |
---|
712 | int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); |
---|
713 | int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); |
---|
714 | int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr); |
---|
715 | int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr); |
---|
716 | for (size_t p = 0; p < nb_procs; p++) |
---|
717 | int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); |
---|
718 | |
---|
719 | if ( is_io ) |
---|
720 | { |
---|
721 | int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); |
---|
722 | int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); |
---|
723 | } |
---|
724 | |
---|
725 | int_wi_gate_d->p_clk (this->p_clk); |
---|
726 | int_wi_gate_d->p_resetn (this->p_resetn); |
---|
727 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
---|
728 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
---|
729 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
---|
730 | |
---|
731 | int_wt_gate_d->p_clk (this->p_clk); |
---|
732 | int_wt_gate_d->p_resetn (this->p_resetn); |
---|
733 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
---|
734 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
---|
735 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
---|
736 | |
---|
737 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
738 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
739 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
740 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
741 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
742 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
743 | for (size_t p = 0; p < nb_procs; p++) |
---|
744 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
745 | |
---|
746 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
747 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
748 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
749 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
750 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
751 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
752 | for (size_t p = 0; p < nb_procs; p++) |
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753 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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754 | |
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755 | ////////////////////// CLACK DSPIN local crossbar coherence |
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756 | int_xbar_clack_c->p_clk (this->p_clk); |
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757 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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758 | int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c); |
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759 | int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c); |
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760 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc); |
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761 | for (size_t p = 0; p < nb_procs; p++) |
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762 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]); |
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763 | |
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764 | |
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765 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
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766 | if ( is_io ) |
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767 | { |
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768 | // IO bridge |
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769 | iob->p_clk (this->p_clk); |
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770 | iob->p_resetn (this->p_resetn); |
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771 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
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772 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
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773 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
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774 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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775 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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776 | |
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777 | // initiator wrapper to RAM network |
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778 | iob_ram_wi->p_clk (this->p_clk); |
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779 | iob_ram_wi->p_resetn (this->p_resetn); |
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780 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); |
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781 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); |
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782 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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783 | |
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784 | // crossbar between MEMC and IOB to RAM network |
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785 | ram_xbar_cmd->p_clk (this->p_clk); |
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786 | ram_xbar_cmd->p_resetn (this->p_resetn); |
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787 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); |
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788 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); |
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789 | ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); |
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790 | ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); |
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791 | |
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792 | ram_xbar_rsp->p_clk (this->p_clk); |
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793 | ram_xbar_rsp->p_resetn (this->p_resetn); |
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794 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); |
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795 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); |
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796 | ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); |
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797 | ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); |
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798 | } |
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799 | |
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800 | SC_METHOD(init); |
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801 | dont_initialize(); |
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802 | |
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803 | } // end constructor |
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804 | |
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805 | tmpl(void)::init() |
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806 | { |
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807 | signal_ram_dspin_cmd_false.write = false; |
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808 | signal_ram_dspin_rsp_false.read = true; |
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809 | } |
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810 | |
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811 | }} |
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812 | |
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813 | |
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814 | // Local Variables: |
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815 | // tab-width: 3 |
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816 | // c-basic-offset: 3 |
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817 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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818 | // indent-tabs-mode: nil |
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819 | // End: |
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820 | |
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821 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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822 | |
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