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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 1002

Last change on this file since 1002 was 1002, checked in by alain, 9 years ago
Introducing the BDV / SDC / HBA switch in the tsar_generic_iob plat-form
File size: 41.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define MWR_COPROC_CPY 0
18	#define MWR_COPROC_DCT 1
19	#define MWR_COPROC_GCD 2
20
21	#define tmpl(x) \
22	template<typename vci_param_int , typename vci_param_ext,\
23	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
24	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
25	x TsarIobCluster<\
26	vci_param_int , vci_param_ext,\
27	dspin_int_cmd_width, dspin_int_rsp_width,\
28	dspin_ram_cmd_width, dspin_ram_rsp_width>
29
30	namespace soclib { namespace caba {
31
32	/////////////////////////////////////////////////////////////////////////////
33	tmpl(/**/)::TsarIobCluster(
34	/////////////////////////////////////////////////////////////////////////////
35	sc_module_name insname,
36	size_t nb_procs,
37	size_t x_id,
38	size_t y_id,
39	size_t xmax,
40	size_t ymax,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49	size_t p_width,
50
51	size_t int_memc_tgt_id, // local index
52	size_t int_xicu_tgt_id, // local index
53	size_t int_mwmr_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mwmr_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79
80	size_t coproc_type,
81
82	const Loader &loader,
83
84	uint32_t frozen_cycles,
85	uint32_t debug_start_cycle,
86	bool memc_debug_ok,
87	bool proc_debug_ok,
88	bool iob_debug_ok )
89	: soclib::caba::BaseModule(insname),
90	p_clk("clk"),
91	p_resetn("resetn")
92	{
93	assert( (x_id < xmax) and (y_id < ymax) and
94	"Error in tsar_iob_cluster : Illegal cluster coordinates");
95
96	size_t cluster_id = (x_id<<4) + y_id;
97
98	// Vectors of DSPIN ports for inter-cluster communications
99	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4);
100	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4);
101
102	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4);
103	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4);
104
105	p_dspin_int_m2p_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_m2p_in", 4);
106	p_dspin_int_m2p_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_m2p_out", 4);
107
108	p_dspin_int_p2m_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_p2m_in", 4);
109	p_dspin_int_p2m_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_p2m_out", 4);
110
111	p_dspin_int_cla_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cla_in", 4);
112	p_dspin_int_cla_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cla_out", 4);
113
114	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
115	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
116
117	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
118	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
119
120	// VCI ports from IOB to IOX network (only in IO clusters)
121	if ( is_io )
122	{
123	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
124	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
125	}
126
127	//////////////////////////////////////////////////////////////////////////////////
128	// Hardware components
129	//////////////////////////////////////////////////////////////////////////////////
130
131	//////////// PROCS /////////////////////////////////////////////////////////////
132	for (size_t p = 0; p < nb_procs; p++)
133	{
134	std::ostringstream s_proc;
135	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
136	proc[p] = new VciCcVCacheWrapper<vci_param_int,
137	dspin_int_cmd_width,
138	dspin_int_rsp_width,
139	GdbServer<Mips32ElIss> >(
140	s_proc.str().c_str(),
141	(cluster_id << p_width) + p, // GLOBAL PROC_ID
142	mt_int, // Mapping Table INT network
143	IntTab(cluster_id,p), // SRCID
144	(cluster_id << l_width) + p, // CC_GLOBAL_ID
145	8, // ITLB ways
146	8, // ITLB sets
147	8, // DTLB ways
148	8, // DTLB sets
149	l1_i_ways, l1_i_sets, 16, // ICACHE size
150	l1_d_ways, l1_d_sets, 16, // DCACHE size
151	4, // WBUF nlines
152	4, // WBUF nwords
153	x_width,
154	y_width,
155	frozen_cycles, // max frozen cycles
156	debug_start_cycle,
157	proc_debug_ok);
158	}
159
160	//////////// MEMC /////////////////////////////////////////////////////////////
161	std::ostringstream s_memc;
162	s_memc << "memc_" << x_id << "_" << y_id;
163	memc = new VciMemCache<vci_param_int,
164	vci_param_ext,
165	dspin_int_rsp_width,
166	dspin_int_cmd_width>(
167	s_memc.str().c_str(),
168	mt_int, // Mapping Table INT network
169	mt_ram, // Mapping Table RAM network
170	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
171	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
172	x_width, // number of bits for x coordinate
173	y_width, // number of bits for y coordinate
174	memc_ways, memc_sets, 16, // CACHE SIZE
175	3, // MAX NUMBER OF COPIES
176	4096, // HEAP SIZE
177	8, // TRANSACTION TABLE DEPTH
178	8, // UPDATE TABLE DEPTH
179	8, // INVALIDATE TABLE DEPTH
180	debug_start_cycle,
181	memc_debug_ok );
182
183	std::ostringstream s_wi_memc;
184	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
185	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
186	dspin_ram_cmd_width,
187	dspin_ram_rsp_width>(
188	s_wi_memc.str().c_str(),
189	x_width + y_width + l_width);
190
191	/////////// XICU //////////////////////////////////////////////////////////////
192	std::ostringstream s_xicu;
193	s_xicu << "xicu_" << x_id << "_" << y_id;
194	xicu = new VciXicu<vci_param_int>(
195	s_xicu.str().c_str(),
196	mt_int, // mapping table INT network
197	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
198	xcu_nb_pti, // number of timer IRQs
199	xcu_nb_hwi, // number of hard IRQs
200	xcu_nb_wti, // number of soft IRQs
201	xcu_nb_out); // number of output IRQs
202
203	//////////// MWMR controller and COPROC ////////////////////////////////////////
204	std::ostringstream s_mwmr;
205	std::ostringstream s_copro;
206	s_mwmr << "mwmr_" << x_id << "_" << y_id;
207
208	if ( coproc_type == MWR_COPROC_CPY)
209	{
210	s_copro << "cpy_" << x_id << "_" << y_id;
211	cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size
212
213	mwmr = new VciMwmrDma<vci_param_int>(
214	s_mwmr.str().c_str(),
215	mt_int,
216	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
217	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
218	1, // nb to_coproc ports
219	1, // nb from_coproc ports
220	1, // nb config registers
221	0, // nb status registers
222	64 ); // burst size (bytes)
223	}
224	if ( coproc_type == MWR_COPROC_DCT )
225	{
226	s_copro << "dct_" << x_id << "_" << y_id;
227	dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency
228
229	mwmr = new VciMwmrDma<vci_param_int>(
230	s_mwmr.str().c_str(),
231	mt_int,
232	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
233	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
234	1, // nb to_coproc ports
235	1, // nb from_coproc ports
236	1, // nb config registers
237	0, // nb status registers
238	64 ); // burst size (bytes)
239	}
240	if ( coproc_type == MWR_COPROC_GCD )
241	{
242	s_copro << "gcd_" << x_id << "_" << y_id;
243	gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size
244
245	mwmr = new VciMwmrDma<vci_param_int>(
246	s_mwmr.str().c_str(),
247	mt_int,
248	IntTab(cluster_id, int_mwmr_ini_id), // SRCID
249	IntTab(cluster_id, int_mwmr_tgt_id), // TGTID
250	2, // nb to_coproc ports
251	1, // nb from_coproc ports
252	1, // nb config registers
253	0, // nb status registers
254	64 ); // burst size (bytes)
255	}
256
257	/////////// VCI INT_CMD/RSP LOCAL_XBAR //////////////////////////////////////
258	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
259	size_t nb_direct_targets = is_io ? 4 : 3;
260
261	std::ostringstream s_int_xbar_d;
262	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
263	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
264	s_int_xbar_d.str().c_str(),
265	mt_int, // mapping table
266	cluster_id, // cluster id
267	nb_direct_initiators, // number of local initiators
268	nb_direct_targets, // number of local targets
269	0 ); // default target
270
271	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
272	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
273	<< x_id << "_" << y_id;
274	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
275	dspin_int_cmd_width,
276	dspin_int_rsp_width>(
277	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
278	x_width + y_width + l_width);
279
280	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
281	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
282	<< x_id << "_" << y_id;
283	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
284	dspin_int_cmd_width,
285	dspin_int_rsp_width>(
286	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
287	x_width + y_width + l_width);
288
289	//////////// DSPIN INT_M2P LOCAL_XBAR ////////////////////////////////////////
290	std::ostringstream s_int_xbar_m2p_c;
291	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
292	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
293	s_int_xbar_m2p_c.str().c_str(),
294	mt_int, // mapping table
295	x_id, y_id, // cluster coordinates
296	x_width, y_width, l_width, // several dests
297	1, // number of local sources
298	nb_procs, // number of local dests
299	2, 2, // fifo depths
300	true, // pseudo CMD
301	false, // no routing table
302	true ); // broacast
303
304	//////////// DSPIN INT_P2M LOCAL_XBAR ////////////////////////////////////////
305	std::ostringstream s_int_xbar_p2m_c;
306	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
307	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
308	s_int_xbar_p2m_c.str().c_str(),
309	mt_int, // mapping table
310	x_id, y_id, // cluster coordinates
311	x_width, y_width, 0, // only one dest
312	nb_procs, // number of local sources
313	1, // number of local dests
314	2, 2, // fifo depths
315	false, // pseudo RSP
316	false, // no routing table
317	false ); // no broacast
318
319	//////////// DSPIN INT_CLA LOCAL_XBAR ////////////////////////////////////////
320	std::ostringstream s_int_xbar_clack_c;
321	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
322	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
323	s_int_xbar_clack_c.str().c_str(),
324	mt_int, // mapping table
325	x_id, y_id, // cluster coordinates
326	x_width, y_width, l_width,
327	1, // number of local sources
328	nb_procs, // number of local targets
329	1, 1, // fifo depths
330	true, // CMD
331	false, // no routing table
332	false); // broadcast
333
334	//////////// DSPIN INT_CMD ROUTER ////////////////////////////////////////////
335	std::ostringstream s_int_router_cmd;
336	s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id;
337	int_router_cmd = new DspinRouter<dspin_int_cmd_width>(
338	s_int_router_cmd.str().c_str(),
339	x_id,y_id, // coordinate in the mesh
340	x_width, y_width, // x & y fields width
341	4,4); // input & output fifo depths
342
343	//////////// DSPIN INT_RSP ROUTER ////////////////////////////////////////////
344	std::ostringstream s_int_router_rsp;
345	s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id;
346	int_router_rsp = new DspinRouter<dspin_int_rsp_width>(
347	s_int_router_rsp.str().c_str(),
348	x_id,y_id, // coordinates in mesh
349	x_width, y_width, // x & y fields width
350	4,4); // input & output fifo depths
351
352	//////////// DSPIN INT_M2P ROUTER ////////////////////////////////////////////
353	std::ostringstream s_int_router_m2p;
354	s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id;
355	int_router_m2p = new DspinRouter<dspin_int_cmd_width>(
356	s_int_router_m2p.str().c_str(),
357	x_id,y_id, // coordinate in the mesh
358	x_width, y_width, // x & y fields width
359	4,4, // input & output fifo depths
360	true); // broadcast supported
361
362	//////////// DSPIN INT_P2M ROUTER ////////////////////////////////////////////
363	std::ostringstream s_int_router_p2m;
364	s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id;
365	int_router_p2m = new DspinRouter<dspin_int_rsp_width>(
366	s_int_router_p2m.str().c_str(),
367	x_id,y_id, // coordinates in mesh
368	x_width, y_width, // x & y fields width
369	4,4); // input & output fifo depths
370
371	//////////// DSPIN INT_CLA ROUTER ////////////////////////////////////////////
372	std::ostringstream s_int_router_cla;
373	s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id;
374	int_router_cla = new DspinRouter<dspin_int_cmd_width>(
375	s_int_router_cla.str().c_str(),
376	x_id,y_id, // coordinate in the mesh
377	x_width, y_width, // x & y fields width
378	4,4); // input & output fifo depths
379
380	////////////// XRAM /////////////////////////////////////////////////////////
381	std::ostringstream s_xram;
382	s_xram << "xram_" << x_id << "_" << y_id;
383	xram = new VciSimpleRam<vci_param_ext>(
384	s_xram.str().c_str(),
385	IntTab(cluster_id, ram_xram_tgt_id),
386	mt_ram,
387	loader,
388	xram_latency);
389
390	std::ostringstream s_wt_xram;
391	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
392	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
393	dspin_ram_cmd_width,
394	dspin_ram_rsp_width>(
395	s_wt_xram.str().c_str(),
396	x_width + y_width + l_width);
397
398	//////////// DSPIN RAM_CMD ROUTER ///////////////////////////////////////////
399	std::ostringstream s_ram_router_cmd;
400	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
401	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
402	s_ram_router_cmd.str().c_str(),
403	x_id, y_id, // router coordinates in mesh
404	x_width, // x field width in first flit
405	y_width, // y field width in first flit
406	4, 4); // input & output fifo depths
407
408	//////////// DSPIN RAM_RSP ROUTER ///////////////////////////////////////////
409	std::ostringstream s_ram_router_rsp;
410	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
411	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
412	s_ram_router_rsp.str().c_str(),
413	x_id, y_id, // coordinates in mesh
414	x_width, // x field width in first flit
415	y_width, // y field width in first flit
416	4, 4); // input & output fifo depths
417
418
419	////////////////////// I/O CLUSTER ONLY ///////////////////////////////////
420	if ( is_io )
421	{
422	/////////// IO_BRIDGE ////////////////////////////////////////////////////
423	std::ostringstream s_iob;
424	s_iob << "iob_" << x_id << "_" << y_id;
425	iob = new VciIoBridge<vci_param_int,
426	vci_param_ext>(
427	s_iob.str().c_str(),
428	mt_ram, // EXT network maptab
429	mt_int, // INT network maptab
430	mt_iox, // IOX network maptab
431	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
432	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
433	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
434	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
435	16, // cache line words
436	8, // IOTLB ways
437	8, // IOTLB sets
438	debug_start_cycle,
439	iob_debug_ok );
440
441	std::ostringstream s_iob_ram_wi;
442	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
443	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
444	dspin_ram_cmd_width,
445	dspin_ram_rsp_width>(
446	s_iob_ram_wi.str().c_str(),
447	vci_param_int::S);
448
449	//////////// DSPIN RAM_CMD LOCAL_XBAR ///////////////////////////////////
450	std::ostringstream s_ram_xbar_cmd;
451	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
452	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
453	s_ram_xbar_cmd.str().c_str(), // name
454	mt_ram, // mapping table
455	x_id, y_id, // x, y
456	x_width, y_width, l_width, // x_width, y_width, l_width
457	2, 0, // local inputs, local outputs
458	2, 2, // in fifo, out fifo depths
459	true, // is cmd ?
460	false, // use routing table ?
461	false); // support broadcast ?
462
463	//////////// DSPIN RAM_RSP LOCAL_XBAR ///////////////////////////////////
464	std::ostringstream s_ram_xbar_rsp;
465	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
466	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
467	s_ram_xbar_rsp.str().c_str(), // name
468	mt_ram, // mapping table
469	x_id, y_id, // x, y
470	x_width, y_width, l_width, // x_width, y_width, l_width
471	0, 2, // local inputs, local outputs
472	2, 2, // in fifo, out fifo depths
473	false, // is cmd ?
474	true, // use routing table ?
475	false); // support broadcast ?
476
477	} // end if IO
478
479	////////////////////////////////////
480	// Connections are defined here
481	////////////////////////////////////
482
483	// on coherence network : local srcid[proc] in [0...nb_procs-1]
484	// : local srcid[memc] = nb_procs
485
486	//////////////////////////////////// Processors
487	for (size_t p = 0; p < nb_procs; p++)
488	{
489	proc[p]->p_clk (this->p_clk);
490	proc[p]->p_resetn (this->p_resetn);
491
492	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
493	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
494	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
495	proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]);
496
497	for ( size_t j = 0 ; j < 6 ; j++)
498	{
499	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
500	else proc[p]->p_irq[j] (signal_false);
501	}
502	}
503
504	std::cout << " - processors connected" << std::endl;
505
506	///////////////////////////////////// XICU
507	xicu->p_clk (this->p_clk);
508	xicu->p_resetn (this->p_resetn);
509	xicu->p_vci (signal_int_vci_tgt_xicu);
510	for ( size_t i=0 ; i < xcu_nb_out ; i++)
511	{
512	xicu->p_irq[i] (signal_proc_it[i]);
513	}
514	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
515	{
516	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
517	else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr);
518	else xicu->p_hwi[i] (signal_false);
519	}
520
521	std::cout << " - xcu connected" << std::endl;
522
523	///////////////////////////////////// MEMC
524	memc->p_clk (this->p_clk);
525	memc->p_resetn (this->p_resetn);
526	memc->p_vci_ixr (signal_ram_vci_ini_memc);
527	memc->p_vci_tgt (signal_int_vci_tgt_memc);
528	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
529	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
530	memc->p_dspin_clack (signal_int_dspin_cla_memc);
531	memc->p_irq (signal_irq_memc);
532
533	// wrapper to RAM network
534	memc_ram_wi->p_clk (this->p_clk);
535	memc_ram_wi->p_resetn (this->p_resetn);
536	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
537	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
538	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
539
540	std::cout << " - memc connected" << std::endl;
541
542	//////////////////////////////////// XRAM
543	xram->p_clk (this->p_clk);
544	xram->p_resetn (this->p_resetn);
545	xram->p_vci (signal_ram_vci_tgt_xram);
546
547	// wrapper to RAM network
548	xram_ram_wt->p_clk (this->p_clk);
549	xram_ram_wt->p_resetn (this->p_resetn);
550	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
551	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
552	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
553
554	std::cout << " - xram connected" << std::endl;
555
556	/////////////////////////////////// GCD coprocessor
557	if ( coproc_type == MWR_COPROC_GCD )
558	{
559	gcd->p_clk (this->p_clk);
560	gcd->p_resetn (this->p_resetn);
561	gcd->p_opa (signal_to_coproc[0]);
562	gcd->p_opb (signal_to_coproc[1]);
563	gcd->p_res (signal_from_coproc[0]);
564	gcd->p_config (signal_config_coproc[0]);
565
566	mwmr->p_clk (this->p_clk);
567	mwmr->p_resetn (this->p_resetn);
568	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
569	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
570	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
571	mwmr->p_to_coproc[1] (signal_to_coproc[1]);
572	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
573	mwmr->p_config[0] (signal_config_coproc[0]);
574	mwmr->p_irq (signal_irq_mwmr);
575	}
576
577	/////////////////////////////////// DCT coprocessor
578	if ( coproc_type == MWR_COPROC_DCT )
579	{
580	dct->p_clk (this->p_clk);
581	dct->p_resetn (this->p_resetn);
582	dct->p_in (signal_to_coproc[0]);
583	dct->p_out (signal_from_coproc[0]);
584	dct->p_config (signal_config_coproc[0]);
585
586	mwmr->p_clk (this->p_clk);
587	mwmr->p_resetn (this->p_resetn);
588	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
589	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
590	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
591	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
592	mwmr->p_config[0] (signal_config_coproc[0]);
593	mwmr->p_irq (signal_irq_mwmr);
594	}
595
596	std::cout << " - coproc connected" << std::endl;
597
598	/////////////////////////////////// CPY coprocessor
599	if ( coproc_type == MWR_COPROC_CPY )
600	{
601	cpy->p_clk (this->p_clk);
602	cpy->p_resetn (this->p_resetn);
603	cpy->p_load (signal_to_coproc[0]);
604	cpy->p_store (signal_from_coproc[0]);
605	cpy->p_config (signal_config_coproc[0]);
606
607	mwmr->p_clk (this->p_clk);
608	mwmr->p_resetn (this->p_resetn);
609	mwmr->p_vci_target (signal_int_vci_tgt_mwmr);
610	mwmr->p_vci_initiator (signal_int_vci_ini_mwmr);
611	mwmr->p_to_coproc[0] (signal_to_coproc[0]);
612	mwmr->p_from_coproc[0] (signal_from_coproc[0]);
613	mwmr->p_config[0] (signal_config_coproc[0]);
614	mwmr->p_irq (signal_irq_mwmr);
615	}
616
617	//////////////////////////// RAM NETWORK ROUTERS
618	ram_router_cmd->p_clk (this->p_clk);
619	ram_router_cmd->p_resetn (this->p_resetn);
620	ram_router_rsp->p_clk (this->p_clk);
621	ram_router_rsp->p_resetn (this->p_resetn);
622
623	for( size_t n=0 ; n<4 ; n++)
624	{
625	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
626	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
627	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
628	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
629	}
630
631	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
632	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
633
634	if ( is_io )
635	{
636	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
637	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
638	}
639	else
640	{
641	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
642	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
643	}
644
645	///////////////////////////// INT NETWORK ROUTERS
646	int_router_cmd->p_clk (this->p_clk);
647	int_router_cmd->p_resetn (this->p_resetn);
648	int_router_rsp->p_clk (this->p_clk);
649	int_router_rsp->p_resetn (this->p_resetn);
650	int_router_m2p->p_clk (this->p_clk);
651	int_router_m2p->p_resetn (this->p_resetn);
652	int_router_p2m->p_clk (this->p_clk);
653	int_router_p2m->p_resetn (this->p_resetn);
654	int_router_cla->p_clk (this->p_clk);
655	int_router_cla->p_resetn (this->p_resetn);
656
657	// loop on N/S/E/W ports
658	for (size_t i = 0; i < 4; i++)
659	{
660	int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]);
661	int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]);
662
663	int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]);
664	int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]);
665
666	int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]);
667	int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]);
668
669	int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]);
670	int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]);
671
672	int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]);
673	int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]);
674	}
675
676	int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d);
677	int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d);
678
679	int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d);
680	int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d);
681
682	int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c);
683	int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c);
684
685	int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c);
686	int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c);
687
688	int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c);
689	int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c);
690
691	std::cout << " - internal routers connected" << std::endl;
692
693
694	///////////////////// CMD DSPIN local crossbar direct
695	int_xbar_d->p_clk (this->p_clk);
696	int_xbar_d->p_resetn (this->p_resetn);
697	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
698	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
699
700	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
701	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
702	int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr);
703	int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr);
704	for (size_t p = 0; p < nb_procs; p++)
705	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
706
707	if ( is_io )
708	{
709	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
710	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
711	}
712
713	int_wi_gate_d->p_clk (this->p_clk);
714	int_wi_gate_d->p_resetn (this->p_resetn);
715	int_wi_gate_d->p_vci (signal_int_vci_l2g);
716	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
717	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
718
719	int_wt_gate_d->p_clk (this->p_clk);
720	int_wt_gate_d->p_resetn (this->p_resetn);
721	int_wt_gate_d->p_vci (signal_int_vci_g2l);
722	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
723	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
724
725	////////////////////// M2P DSPIN local crossbar coherence
726	int_xbar_m2p_c->p_clk (this->p_clk);
727	int_xbar_m2p_c->p_resetn (this->p_resetn);
728	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
729	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
730	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
731	for (size_t p = 0; p < nb_procs; p++)
732	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
733
734	////////////////////////// P2M DSPIN local crossbar coherence
735	int_xbar_p2m_c->p_clk (this->p_clk);
736	int_xbar_p2m_c->p_resetn (this->p_resetn);
737	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
738	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
739	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
740	for (size_t p = 0; p < nb_procs; p++)
741	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
742
743	////////////////////// CLACK DSPIN local crossbar coherence
744	int_xbar_clack_c->p_clk (this->p_clk);
745	int_xbar_clack_c->p_resetn (this->p_resetn);
746	int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c);
747	int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c);
748	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc);
749	for (size_t p = 0; p < nb_procs; p++)
750	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]);
751
752
753	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
754	if ( is_io )
755	{
756	// IO bridge
757	iob->p_clk (this->p_clk);
758	iob->p_resetn (this->p_resetn);
759	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
760	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
761	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
762	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
763	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
764
765	// initiator wrapper to RAM network
766	iob_ram_wi->p_clk (this->p_clk);
767	iob_ram_wi->p_resetn (this->p_resetn);
768	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
769	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
770	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
771
772	// crossbar between MEMC and IOB to RAM network
773	ram_xbar_cmd->p_clk (this->p_clk);
774	ram_xbar_cmd->p_resetn (this->p_resetn);
775	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
776	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
777	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
778	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
779
780	ram_xbar_rsp->p_clk (this->p_clk);
781	ram_xbar_rsp->p_resetn (this->p_resetn);
782	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
783	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
784	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
785	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
786	}
787
788	SC_METHOD(init);
789
790	} // end constructor
791
792	tmpl(void)::init()
793	{
794	signal_ram_dspin_cmd_false.write = false;
795	signal_ram_dspin_rsp_false.read = true;
796	}
797
798	}}
799
800
801	// Local Variables:
802	// tab-width: 3
803	// c-basic-offset: 3
804	// c-file-offsets:((innamespace . 0)(inline-open . 0))
805	// indent-tabs-mode: nil
806	// End:
807
808	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
809

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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Language-Team: en_US <trac-dev@googlegroups.com>
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