1 | ////////////////////////////////////////////////////////////////////////////// |
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2 | // File: tsar_iob_cluster.cpp |
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3 | // Author: Alain Greiner |
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4 | // Copyright: UPMC/LIP6 |
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5 | // Date : april 2013 |
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6 | // This program is released under the GNU public license |
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7 | ////////////////////////////////////////////////////////////////////////////// |
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8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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9 | // These two clusters contain 6 extra components: |
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10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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11 | // - 3 vci_dspin_wrapper for the IOB. |
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12 | // - 2 dspin_local_crossbar for commands and responses. |
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13 | ////////////////////////////////////////////////////////////////////////////// |
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14 | |
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15 | #include "../include/tsar_iob_cluster.h" |
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16 | |
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17 | namespace soclib { namespace caba { |
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18 | |
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19 | ////////////////////////////////////////////////////////////////////////// |
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20 | // Constructor |
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21 | ////////////////////////////////////////////////////////////////////////// |
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22 | template<typename vci_param_int, |
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23 | typename vci_param_ext, |
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24 | size_t dspin_int_cmd_width, |
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25 | size_t dspin_int_rsp_width, |
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26 | size_t dspin_ram_cmd_width, |
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27 | size_t dspin_ram_rsp_width> |
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28 | TsarIobCluster<vci_param_int, |
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29 | vci_param_ext, |
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30 | dspin_int_cmd_width, |
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31 | dspin_int_rsp_width, |
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32 | dspin_ram_cmd_width, |
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33 | dspin_ram_rsp_width>::TsarIobCluster( |
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34 | ////////////////////////////////////////////////////////////////////////// |
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35 | sc_module_name insname, |
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36 | size_t nb_procs, |
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37 | size_t nb_dmas, |
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38 | size_t x_id, |
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39 | size_t y_id, |
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40 | size_t xmax, |
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41 | size_t ymax, |
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42 | |
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43 | const soclib::common::MappingTable &mt_int, |
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44 | const soclib::common::MappingTable &mt_ram, |
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45 | const soclib::common::MappingTable &mt_iox, |
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46 | |
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47 | size_t x_width, |
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48 | size_t y_width, |
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49 | size_t l_width, |
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50 | |
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51 | size_t memc_int_tgtid, |
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52 | size_t xicu_int_tgtid, |
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53 | size_t mdma_int_tgtid, |
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54 | size_t iobx_int_tgtid, |
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55 | |
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56 | size_t proc_int_srcid, |
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57 | size_t mdma_int_srcid, |
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58 | size_t iobx_int_srcid, |
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59 | |
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60 | size_t xram_ram_tgtid, |
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61 | |
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62 | size_t memc_ram_srcid, |
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63 | size_t iobx_ram_srcid, |
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64 | |
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65 | size_t memc_ways, |
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66 | size_t memc_sets, |
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67 | size_t l1_i_ways, |
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68 | size_t l1_i_sets, |
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69 | size_t l1_d_ways, |
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70 | size_t l1_d_sets, |
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71 | size_t xram_latency, |
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72 | |
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73 | const Loader &loader, |
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74 | |
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75 | uint32_t frozen_cycles, |
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76 | uint32_t debug_start_cycle, |
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77 | bool memc_debug_ok, |
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78 | bool proc_debug_ok, |
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79 | bool iob_debug_ok ) |
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80 | : soclib::caba::BaseModule(insname), |
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81 | p_clk("clk"), |
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82 | p_resetn("resetn") |
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83 | { |
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84 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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85 | |
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86 | size_t cluster_id = x_id * ymax + y_id; |
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87 | size_t cluster_iob0 = 0; |
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88 | size_t cluster_iob1 = xmax*ymax-1; |
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89 | |
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90 | // Vectors of DSPIN ports for inter-cluster communications |
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91 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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92 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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93 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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94 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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95 | |
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96 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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97 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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98 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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99 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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100 | |
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101 | // VCI ports to IOB0 and IOB1 in cluster_iob0 and cluster_iob1 |
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102 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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103 | { |
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104 | p_vci_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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105 | p_vci_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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106 | } |
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107 | |
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108 | // IRQ ports in cluster_iob0 only |
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109 | if ( cluster_id == cluster_iob0 ) |
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110 | { |
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111 | for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>; |
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112 | } |
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113 | |
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114 | ///////////////////////////////////////////////////////////////////////////// |
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115 | // Hardware components |
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116 | ///////////////////////////////////////////////////////////////////////////// |
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117 | |
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118 | //////////// PROCS |
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119 | for (size_t p = 0; p < nb_procs; p++) |
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120 | { |
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121 | std::ostringstream s_proc; |
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122 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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123 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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124 | dspin_int_cmd_width, |
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125 | dspin_int_rsp_width, |
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126 | GdbServer<Mips32ElIss> >( |
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127 | s_proc.str().c_str(), |
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128 | cluster_id*nb_procs + p, // GLOBAL PROC_ID |
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129 | mt_int, // Mapping Table INT network |
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130 | IntTab(cluster_id,p), // SRCID |
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131 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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132 | 8, // ITLB ways |
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133 | 8, // ITLB sets |
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134 | 8, // DTLB ways |
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135 | 8, // DTLB sets |
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136 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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137 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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138 | 4, // WBUF nlines |
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139 | 4, // WBUF nwords |
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140 | x_width, |
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141 | y_width, |
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142 | frozen_cycles, // max frozen cycles |
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143 | debug_start_cycle, |
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144 | proc_debug_ok); |
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145 | |
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146 | std::ostringstream s_wi_proc; |
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147 | s_wi_proc << "proc_wi_" << x_id << "_" << y_id << "_" << p; |
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148 | proc_wi[p] = new VciDspinInitiatorWrapper<vci_param_int, |
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149 | dspin_int_cmd_width, |
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150 | dspin_int_rsp_width>( |
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151 | s_wi_proc.str().c_str(), |
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152 | x_width + y_width + l_width); |
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153 | } |
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154 | |
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155 | /////////// MEMC |
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156 | std::ostringstream s_memc; |
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157 | s_memc << "memc_" << x_id << "_" << y_id; |
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158 | memc = new VciMemCache<vci_param_int, |
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159 | vci_param_ext, |
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160 | dspin_int_rsp_width, |
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161 | dspin_int_cmd_width>( |
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162 | s_memc.str().c_str(), |
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163 | mt_int, // Mapping Table INT network |
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164 | mt_ram, // Mapping Table RAM network |
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165 | IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network |
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166 | IntTab(cluster_id, memc_int_tgtid), // TGTID INT network |
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167 | (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID |
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168 | x_width, // Number of x bits in platform |
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169 | y_width, // Number of y bits in platform |
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170 | memc_ways, memc_sets, 16, // CACHE SIZE |
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171 | 3, // MAX NUMBER OF COPIES |
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172 | 4096, // HEAP SIZE |
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173 | 8, // TRANSACTION TABLE DEPTH |
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174 | 8, // UPDATE TABLE DEPTH |
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175 | 8, // INVALIDATE TABLE DEPTH |
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176 | debug_start_cycle, |
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177 | memc_debug_ok ); |
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178 | |
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179 | std::ostringstream s_wt_memc; |
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180 | s_wt_memc << "memc_wt_" << x_id << "_" << y_id; |
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181 | memc_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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182 | dspin_int_cmd_width, |
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183 | dspin_int_rsp_width>( |
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184 | s_wt_memc.str().c_str(), |
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185 | x_width + y_width + l_width); |
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186 | |
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187 | std::ostringstream s_wi_memc; |
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188 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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189 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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190 | dspin_ram_cmd_width, |
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191 | dspin_ram_rsp_width>( |
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192 | s_wi_memc.str().c_str(), |
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193 | x_width + y_width + l_width); |
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194 | |
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195 | /////////// XICU |
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196 | std::ostringstream s_xicu; |
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197 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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198 | xicu = new VciXicu<vci_param_int>( |
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199 | s_xicu.str().c_str(), |
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200 | mt_int, // mapping table INT network |
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201 | IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space |
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202 | nb_procs, // number of timer IRQs |
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203 | 32, // number of hard IRQs |
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204 | 32, // number of soft IRQs |
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205 | nb_procs); // number of output IRQs |
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206 | |
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207 | std::ostringstream s_wt_xicu; |
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208 | s_wt_xicu << "xicu_wt_" << x_id << "_" << y_id; |
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209 | xicu_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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210 | dspin_int_cmd_width, |
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211 | dspin_int_rsp_width>( |
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212 | s_wt_xicu.str().c_str(), |
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213 | x_width + y_width + l_width); |
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214 | |
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215 | //////////// MDMA |
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216 | std::ostringstream s_mdma; |
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217 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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218 | mdma = new VciMultiDma<vci_param_int>( |
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219 | s_mdma.str().c_str(), |
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220 | mt_int, |
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221 | IntTab(cluster_id, nb_procs), // SRCID |
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222 | IntTab(cluster_id, mdma_int_tgtid), // TGTID |
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223 | 64, // burst size |
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224 | nb_dmas); // number of IRQs |
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225 | |
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226 | std::ostringstream s_wt_mdma; |
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227 | s_wt_mdma << "mdma_wt_" << x_id << "_" << y_id; |
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228 | mdma_int_wt = new VciDspinTargetWrapper<vci_param_int, |
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229 | dspin_int_cmd_width, |
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230 | dspin_int_rsp_width>( |
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231 | s_wt_mdma.str().c_str(), |
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232 | x_width + y_width + l_width); |
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233 | |
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234 | std::ostringstream s_wi_mdma; |
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235 | s_wi_mdma << "mdma_wi_" << x_id << "_" << y_id; |
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236 | mdma_int_wi = new VciDspinInitiatorWrapper<vci_param_int, |
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237 | dspin_int_cmd_width, |
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238 | dspin_int_rsp_width>( |
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239 | s_wi_mdma.str().c_str(), |
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240 | x_width + y_width + l_width); |
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241 | |
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242 | /////////// Direct LOCAL_XBAR(S) |
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243 | size_t nb_direct_initiators = nb_procs + 1; |
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244 | size_t nb_direct_targets = 3; |
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245 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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246 | { |
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247 | nb_direct_initiators = nb_procs + 2; |
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248 | nb_direct_targets = 4; |
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249 | } |
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250 | |
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251 | std::ostringstream s_int_xbar_cmd_d; |
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252 | s_int_xbar_cmd_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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253 | int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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254 | s_int_xbar_cmd_d.str().c_str(), |
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255 | mt_int, // mapping table |
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256 | x_id, y_id, // cluster coordinates |
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257 | x_width, y_width, l_width, |
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258 | nb_direct_initiators, // number of local of sources |
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259 | nb_direct_targets, // number of local dests |
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260 | 2, 2, // fifo depths |
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261 | true, // CMD crossbar |
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262 | true, // use routing table |
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263 | false ); // no broacast |
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264 | |
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265 | std::ostringstream s_int_xbar_rsp_d; |
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266 | s_int_xbar_rsp_d << "int_xbar_rsp_d_" << x_id << "_" << y_id; |
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267 | int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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268 | s_int_xbar_rsp_d.str().c_str(), |
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269 | mt_int, // mapping table |
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270 | x_id, y_id, // cluster coordinates |
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271 | x_width, y_width, l_width, |
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272 | nb_direct_targets, // number of local sources |
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273 | nb_direct_initiators, // number of local dests |
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274 | 2, 2, // fifo depths |
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275 | false, // RSP crossbar |
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276 | false, // don't use routing table |
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277 | false ); // no broacast |
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278 | |
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279 | //////////// Coherence LOCAL_XBAR(S) |
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280 | std::ostringstream s_int_xbar_m2p_c; |
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281 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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282 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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283 | s_int_xbar_m2p_c.str().c_str(), |
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284 | mt_int, // mapping table |
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285 | x_id, y_id, // cluster coordinates |
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286 | x_width, y_width, l_width, // several dests |
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287 | 1, // number of local sources |
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288 | nb_procs, // number of local dests |
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289 | 2, 2, // fifo depths |
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290 | true, // pseudo CMD |
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291 | false, // no routing table |
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292 | true ); // broacast |
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293 | |
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294 | std::ostringstream s_int_xbar_p2m_c; |
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295 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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296 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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297 | s_int_xbar_p2m_c.str().c_str(), |
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298 | mt_int, // mapping table |
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299 | x_id, y_id, // cluster coordinates |
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300 | x_width, y_width, 0, // only one dest |
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301 | nb_procs, // number of local sources |
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302 | 1, // number of local dests |
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303 | 2, 2, // fifo depths |
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304 | false, // pseudo RSP |
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305 | false, // no routing table |
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306 | false ); // no broacast |
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307 | |
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308 | std::ostringstream s_int_xbar_clack_c; |
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309 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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310 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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311 | s_int_xbar_clack_c.str().c_str(), |
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312 | mt_int, // mapping table |
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313 | x_id, y_id, // cluster coordinates |
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314 | x_width, y_width, l_width, |
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315 | 1, // number of local sources |
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316 | nb_procs, // number of local targets |
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317 | 1, 1, // fifo depths |
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318 | true, // CMD |
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319 | false, // don't use local routing table |
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320 | false); // broadcast |
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321 | |
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322 | ////////////// INT ROUTER(S) |
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323 | std::ostringstream s_int_router_cmd; |
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324 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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325 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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326 | s_int_router_cmd.str().c_str(), |
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327 | x_id,y_id, // coordinate in the mesh |
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328 | x_width, y_width, // x & y fields width |
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329 | 3, // nb virtual channels |
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330 | 4,4); // input & output fifo depths |
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331 | |
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332 | std::ostringstream s_int_router_rsp; |
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333 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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334 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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335 | s_int_router_rsp.str().c_str(), |
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336 | x_id,y_id, // coordinates in mesh |
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337 | x_width, y_width, // x & y fields width |
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338 | 2, // nb virtual channels |
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339 | 4,4); // input & output fifo depths |
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340 | |
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341 | ////////////// XRAM |
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342 | std::ostringstream s_xram; |
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343 | s_xram << "xram_" << x_id << "_" << y_id; |
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344 | xram = new VciSimpleRam<vci_param_ext>( |
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345 | s_xram.str().c_str(), |
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346 | IntTab(cluster_id, xram_ram_tgtid ), |
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347 | mt_ram, |
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348 | loader, |
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349 | xram_latency); |
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350 | |
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351 | std::ostringstream s_wt_xram; |
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352 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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353 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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354 | dspin_ram_cmd_width, |
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355 | dspin_ram_rsp_width>( |
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356 | s_wt_xram.str().c_str(), |
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357 | x_width + y_width + l_width); |
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358 | |
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359 | ///////////// RAM ROUTER(S) |
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360 | std::ostringstream s_ram_router_cmd; |
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361 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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362 | ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( |
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363 | s_ram_router_cmd.str().c_str(), |
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364 | x_id,y_id, // coordinate in the mesh |
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365 | x_width, y_width, // x & y fields width |
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366 | 4,4); // input & output fifo depths |
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367 | |
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368 | std::ostringstream s_ram_router_rsp; |
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369 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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370 | ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( |
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371 | s_ram_router_rsp.str().c_str(), |
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372 | x_id,y_id, // coordinates in mesh |
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373 | x_width, y_width, // x & y fields width |
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374 | 4,4); // input & output fifo depths |
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375 | |
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376 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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377 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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378 | { |
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379 | /////////// IO_BRIDGE |
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380 | size_t iox_local_id; |
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381 | size_t global_id; |
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382 | bool has_irqs; |
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383 | if ( cluster_id == cluster_iob0 ) |
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384 | { |
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385 | iox_local_id = 0; |
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386 | global_id = cluster_iob0; |
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387 | has_irqs = true; |
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388 | } |
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389 | else |
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390 | { |
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391 | iox_local_id = 1; |
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392 | global_id = cluster_iob1; |
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393 | has_irqs = false; |
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394 | } |
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395 | |
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396 | std::ostringstream s_iob; |
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397 | s_iob << "iob_" << x_id << "_" << y_id; |
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398 | iob = new VciIoBridge<vci_param_int, |
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399 | vci_param_ext>( |
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400 | s_iob.str().c_str(), |
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401 | mt_ram, // EXT network maptab |
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402 | mt_int, // INT network maptab |
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403 | mt_iox, // IOX network maptab |
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404 | IntTab( global_id, iobx_int_tgtid ), // INT TGTID |
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405 | IntTab( global_id, iobx_int_srcid ), // INT SRCID |
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406 | IntTab( global_id, iox_local_id ), // IOX TGTID |
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407 | has_irqs, |
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408 | 16, // cache line words |
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409 | 8, // IOTLB ways |
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410 | 8, // IOTLB sets |
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411 | debug_start_cycle, |
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412 | iob_debug_ok ); |
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413 | |
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414 | std::ostringstream s_iob_int_wi; |
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415 | s_iob_int_wi << "iob_int_wi_" << x_id << "_" << y_id; |
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416 | iob_int_wi = new VciDspinInitiatorWrapper<vci_param_int, |
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417 | dspin_int_cmd_width, |
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418 | dspin_int_rsp_width>( |
---|
419 | s_iob_int_wi.str().c_str(), |
---|
420 | x_width + y_width + l_width); |
---|
421 | |
---|
422 | std::ostringstream s_iob_int_wt; |
---|
423 | s_iob_int_wt << "iob_int_wt_" << x_id << "_" << y_id; |
---|
424 | iob_int_wt = new VciDspinTargetWrapper<vci_param_int, |
---|
425 | dspin_int_cmd_width, |
---|
426 | dspin_int_rsp_width>( |
---|
427 | s_iob_int_wt.str().c_str(), |
---|
428 | x_width + y_width + l_width); |
---|
429 | |
---|
430 | std::ostringstream s_iob_ram_wi; |
---|
431 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
---|
432 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
---|
433 | dspin_ram_cmd_width, |
---|
434 | dspin_ram_rsp_width>( |
---|
435 | s_iob_ram_wi.str().c_str(), |
---|
436 | x_width + y_width + l_width); |
---|
437 | |
---|
438 | ///////////// RAM LOCAL_XBAR(S) |
---|
439 | std::ostringstream s_ram_xbar_cmd; |
---|
440 | s_ram_xbar_cmd << "ram_xbar_cmd_" << x_id << "_" << y_id; |
---|
441 | ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( |
---|
442 | s_ram_xbar_cmd.str().c_str(), |
---|
443 | mt_ram, // mapping table |
---|
444 | x_id, y_id, // cluster coordinates |
---|
445 | x_width, y_width, 0, // one dest on ram_cmd network |
---|
446 | 2, // number of local sources |
---|
447 | 1, // number of local dests |
---|
448 | 2, 2, // fifo depths |
---|
449 | true, // CMD crossbar |
---|
450 | false, // no routing table (one dest) |
---|
451 | false ); // no broadcast |
---|
452 | |
---|
453 | std::ostringstream s_ram_xbar_rsp; |
---|
454 | s_ram_xbar_rsp << "ram_xbar_rsp_" << x_id << "_" << y_id; |
---|
455 | ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( |
---|
456 | s_ram_xbar_rsp.str().c_str(), |
---|
457 | mt_ram, // mapping table |
---|
458 | x_id, y_id, // cluster coordinates |
---|
459 | x_width, y_width, l_width, // two sources on ram_rsp network |
---|
460 | 1, // number of local sources |
---|
461 | 2, // number of local dests |
---|
462 | 2, 2, // fifo depths |
---|
463 | false, // RSP crossbar |
---|
464 | true, // use routing table |
---|
465 | false ); // no broadcast |
---|
466 | } |
---|
467 | |
---|
468 | //////////////////////////////////// |
---|
469 | // Connections are defined here |
---|
470 | //////////////////////////////////// |
---|
471 | |
---|
472 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
473 | // : local srcid[memc] = nb_procs |
---|
474 | |
---|
475 | //////////////////////// internal CMD & RSP routers |
---|
476 | int_router_cmd->p_clk (this->p_clk); |
---|
477 | int_router_cmd->p_resetn (this->p_resetn); |
---|
478 | int_router_rsp->p_clk (this->p_clk); |
---|
479 | int_router_rsp->p_resetn (this->p_resetn); |
---|
480 | |
---|
481 | for (int i = 0; i < 4; i++) |
---|
482 | { |
---|
483 | for(int k = 0; k < 3; k++) |
---|
484 | { |
---|
485 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
---|
486 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
---|
487 | } |
---|
488 | |
---|
489 | for(int k = 0; k < 2; k++) |
---|
490 | { |
---|
491 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
---|
492 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
---|
493 | } |
---|
494 | } |
---|
495 | |
---|
496 | // local ports |
---|
497 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
---|
498 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
---|
499 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
---|
500 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
---|
501 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
---|
502 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
---|
503 | |
---|
504 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
---|
505 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
---|
506 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
---|
507 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
---|
508 | |
---|
509 | ///////////////////// CMD DSPIN local crossbar direct |
---|
510 | int_xbar_cmd_d->p_clk (this->p_clk); |
---|
511 | int_xbar_cmd_d->p_resetn (this->p_resetn); |
---|
512 | int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); |
---|
513 | int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); |
---|
514 | |
---|
515 | int_xbar_cmd_d->p_local_out[memc_int_tgtid] (signal_int_dspin_cmd_memc_t); |
---|
516 | int_xbar_cmd_d->p_local_out[xicu_int_tgtid] (signal_int_dspin_cmd_xicu_t); |
---|
517 | int_xbar_cmd_d->p_local_out[mdma_int_tgtid] (signal_int_dspin_cmd_mdma_t); |
---|
518 | |
---|
519 | int_xbar_cmd_d->p_local_in[mdma_int_srcid] (signal_int_dspin_cmd_mdma_i); |
---|
520 | |
---|
521 | for (size_t p = 0; p < nb_procs; p++) |
---|
522 | int_xbar_cmd_d->p_local_in[proc_int_srcid+p] (signal_int_dspin_cmd_proc_i[p]); |
---|
523 | |
---|
524 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
525 | { |
---|
526 | int_xbar_cmd_d->p_local_out[iobx_int_tgtid] (signal_int_dspin_cmd_iobx_t); |
---|
527 | int_xbar_cmd_d->p_local_in[iobx_int_srcid] (signal_int_dspin_cmd_iobx_i); |
---|
528 | } |
---|
529 | |
---|
530 | //////////////////////// RSP DSPIN local crossbar direct |
---|
531 | int_xbar_rsp_d->p_clk (this->p_clk); |
---|
532 | int_xbar_rsp_d->p_resetn (this->p_resetn); |
---|
533 | int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); |
---|
534 | int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); |
---|
535 | |
---|
536 | int_xbar_rsp_d->p_local_in[memc_int_tgtid] (signal_int_dspin_rsp_memc_t); |
---|
537 | int_xbar_rsp_d->p_local_in[xicu_int_tgtid] (signal_int_dspin_rsp_xicu_t); |
---|
538 | int_xbar_rsp_d->p_local_in[mdma_int_tgtid] (signal_int_dspin_rsp_mdma_t); |
---|
539 | |
---|
540 | int_xbar_rsp_d->p_local_out[mdma_int_srcid] (signal_int_dspin_rsp_mdma_i); |
---|
541 | |
---|
542 | for (size_t p = 0; p < nb_procs; p++) |
---|
543 | int_xbar_rsp_d->p_local_out[proc_int_srcid+p] (signal_int_dspin_rsp_proc_i[p]); |
---|
544 | |
---|
545 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
546 | { |
---|
547 | int_xbar_rsp_d->p_local_in[iobx_int_tgtid] (signal_int_dspin_rsp_iobx_t); |
---|
548 | int_xbar_rsp_d->p_local_out[iobx_int_srcid] (signal_int_dspin_rsp_iobx_i); |
---|
549 | } |
---|
550 | |
---|
551 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
552 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
553 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
554 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
555 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
556 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
557 | for (size_t p = 0; p < nb_procs; p++) |
---|
558 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
559 | |
---|
560 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
561 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
562 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
563 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
564 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
565 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
566 | for (size_t p = 0; p < nb_procs; p++) |
---|
567 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
568 | |
---|
569 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
570 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
571 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
572 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
573 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
574 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
575 | for (size_t p = 0; p < nb_procs; p++) |
---|
576 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
577 | |
---|
578 | //////////////////////////////////// Processors |
---|
579 | for (size_t p = 0; p < nb_procs; p++) |
---|
580 | { |
---|
581 | proc[p]->p_clk (this->p_clk); |
---|
582 | proc[p]->p_resetn (this->p_resetn); |
---|
583 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
584 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
585 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
586 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
587 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
588 | for ( size_t j = 1 ; j < 6 ; j++) |
---|
589 | { |
---|
590 | proc[p]->p_irq[j] (signal_false); |
---|
591 | } |
---|
592 | |
---|
593 | proc_wi[p]->p_clk (this->p_clk); |
---|
594 | proc_wi[p]->p_resetn (this->p_resetn); |
---|
595 | proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); |
---|
596 | proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); |
---|
597 | proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
598 | } |
---|
599 | |
---|
600 | ///////////////////////////////////// XICU |
---|
601 | xicu->p_clk (this->p_clk); |
---|
602 | xicu->p_resetn (this->p_resetn); |
---|
603 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
604 | for ( size_t p=0 ; p<nb_procs ; p++) |
---|
605 | { |
---|
606 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
607 | } |
---|
608 | for ( size_t i=0 ; i<4 ; i++) |
---|
609 | { |
---|
610 | xicu->p_hwi[i] (signal_irq_mdma[i]); |
---|
611 | } |
---|
612 | for ( size_t i=4 ; i<32 ; i++) |
---|
613 | { |
---|
614 | if (cluster_id == cluster_iob0) |
---|
615 | xicu->p_hwi[i] (*(this->p_irq[i])); |
---|
616 | else |
---|
617 | xicu->p_hwi[i] (signal_false); |
---|
618 | } |
---|
619 | |
---|
620 | // wrapper XICU |
---|
621 | xicu_int_wt->p_clk (this->p_clk); |
---|
622 | xicu_int_wt->p_resetn (this->p_resetn); |
---|
623 | xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); |
---|
624 | xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); |
---|
625 | xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); |
---|
626 | |
---|
627 | ///////////////////////////////////// MEMC |
---|
628 | memc->p_clk (this->p_clk); |
---|
629 | memc->p_resetn (this->p_resetn); |
---|
630 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
631 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
632 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
633 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
634 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
635 | |
---|
636 | // wrapper to INT network |
---|
637 | memc_int_wt->p_clk (this->p_clk); |
---|
638 | memc_int_wt->p_resetn (this->p_resetn); |
---|
639 | memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); |
---|
640 | memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); |
---|
641 | memc_int_wt->p_vci (signal_int_vci_tgt_memc); |
---|
642 | |
---|
643 | // wrapper to RAM network |
---|
644 | memc_ram_wi->p_clk (this->p_clk); |
---|
645 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
646 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
647 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
648 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
649 | |
---|
650 | //////////////////////////////////// XRAM |
---|
651 | xram->p_clk (this->p_clk); |
---|
652 | xram->p_resetn (this->p_resetn); |
---|
653 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
654 | |
---|
655 | // wrapper to RAM network |
---|
656 | xram_ram_wt->p_clk (this->p_clk); |
---|
657 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
658 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
659 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
660 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
661 | |
---|
662 | /////////////////////////////////// MDMA |
---|
663 | mdma->p_clk (this->p_clk); |
---|
664 | mdma->p_resetn (this->p_resetn); |
---|
665 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
666 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
667 | for (size_t i=0 ; i<nb_dmas ; i++) |
---|
668 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
669 | |
---|
670 | // target wrapper |
---|
671 | mdma_int_wt->p_clk (this->p_clk); |
---|
672 | mdma_int_wt->p_resetn (this->p_resetn); |
---|
673 | mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); |
---|
674 | mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); |
---|
675 | mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); |
---|
676 | |
---|
677 | // initiator wrapper |
---|
678 | mdma_int_wi->p_clk (this->p_clk); |
---|
679 | mdma_int_wi->p_resetn (this->p_resetn); |
---|
680 | mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); |
---|
681 | mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); |
---|
682 | mdma_int_wi->p_vci (signal_int_vci_ini_mdma); |
---|
683 | |
---|
684 | // For the IO bridge and the RAM network components, the connexions |
---|
685 | // depend on cluster type: The vci_io_bridge and dspin_local_crossbar |
---|
686 | // components are only in cluster_iob0 & cluster_iob1 |
---|
687 | |
---|
688 | if ( (cluster_id != cluster_iob0) and (cluster_id != cluster_iob1) ) |
---|
689 | { |
---|
690 | // RAM network CMD & RSP routers |
---|
691 | ram_router_cmd->p_clk (this->p_clk); |
---|
692 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
693 | ram_router_rsp->p_clk (this->p_clk); |
---|
694 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
695 | for( size_t n=0 ; n<4 ; n++) |
---|
696 | { |
---|
697 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
698 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
699 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
700 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
701 | } |
---|
702 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
703 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
704 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
705 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
706 | } |
---|
707 | else // IO cluster |
---|
708 | { |
---|
709 | // IO bridge |
---|
710 | iob->p_clk (this->p_clk); |
---|
711 | iob->p_resetn (this->p_resetn); |
---|
712 | iob->p_vci_ini_iox (*(this->p_vci_iox_ini)); |
---|
713 | iob->p_vci_tgt_iox (*(this->p_vci_iox_tgt)); |
---|
714 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
715 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
716 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
717 | if ( cluster_id == cluster_iob0 ) |
---|
718 | for ( size_t n=0 ; n<32 ; n++ ) |
---|
719 | (*iob->p_irq[n]) (*(this->p_irq[n])); |
---|
720 | |
---|
721 | // initiator wrapper to RAM network |
---|
722 | iob_ram_wi->p_clk (this->p_clk); |
---|
723 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
724 | iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iobx_i); |
---|
725 | iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iobx_i); |
---|
726 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
---|
727 | |
---|
728 | // initiator wrapper to INT network |
---|
729 | iob_int_wi->p_clk (this->p_clk); |
---|
730 | iob_int_wi->p_resetn (this->p_resetn); |
---|
731 | iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); |
---|
732 | iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); |
---|
733 | iob_int_wi->p_vci (signal_int_vci_ini_iobx); |
---|
734 | |
---|
735 | // target wrapper to INT network |
---|
736 | iob_int_wt->p_clk (this->p_clk); |
---|
737 | iob_int_wt->p_resetn (this->p_resetn); |
---|
738 | iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); |
---|
739 | iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); |
---|
740 | iob_int_wt->p_vci (signal_int_vci_tgt_iobx); |
---|
741 | |
---|
742 | // RAM network CMD local crossbar |
---|
743 | ram_xbar_cmd->p_clk (this->p_clk); |
---|
744 | ram_xbar_cmd->p_resetn (this->p_resetn); |
---|
745 | ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_l2g); |
---|
746 | ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_g2l); |
---|
747 | ram_xbar_cmd->p_local_in[0] (signal_ram_dspin_cmd_memc_i); |
---|
748 | ram_xbar_cmd->p_local_in[1] (signal_ram_dspin_cmd_iobx_i); |
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749 | ram_xbar_cmd->p_local_out[0] (signal_ram_dspin_cmd_xram_t); |
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750 | |
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751 | // RAM network RSP local crossbar |
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752 | ram_xbar_rsp->p_clk (this->p_clk); |
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753 | ram_xbar_rsp->p_resetn (this->p_resetn); |
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754 | ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_l2g); |
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755 | ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_g2l); |
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756 | ram_xbar_rsp->p_local_in[0] (signal_ram_dspin_rsp_xram_t); |
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757 | ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i); |
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758 | ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iobx_i); |
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759 | |
---|
760 | // RAM network CMD & RSP routers |
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761 | ram_router_cmd->p_clk (this->p_clk); |
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762 | ram_router_cmd->p_resetn (this->p_resetn); |
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763 | ram_router_rsp->p_clk (this->p_clk); |
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764 | ram_router_rsp->p_resetn (this->p_resetn); |
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765 | for( size_t n=0 ; n<4 ; n++) |
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766 | { |
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767 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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768 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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769 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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770 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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771 | } |
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772 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_g2l); |
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773 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_l2g); |
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774 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_g2l); |
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775 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_l2g); |
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776 | } |
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777 | |
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778 | } // end constructor |
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779 | |
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780 | }} |
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781 | |
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782 | |
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783 | // Local Variables: |
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784 | // tab-width: 3 |
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785 | // c-basic-offset: 3 |
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786 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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787 | // indent-tabs-mode: nil |
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788 | // End: |
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789 | |
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790 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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791 | |
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792 | |
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793 | |
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