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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 953

Last change on this file since 953 was 802, checked in by cfuguet, 10 years ago

tsar_generic_iob: Using the new P_WIDTH constant from hard_config.h

This constant is used in the clusters to compute the procesor id which now is: (((x << Y_WIDTH) + y) << P_WIDTH) + lpid

Introducing the p_width constant in the arch.py and non_distributed_arch.py files

File size: 32.4 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	//////////////////////////////////////////////////////////////////////////
33	sc_module_name insname,
34	size_t nb_procs,
35	size_t nb_dmas,
36	size_t x_id,
37	size_t y_id,
38	size_t xmax,
39	size_t ymax,
40
41	const soclib::common::MappingTable &mt_int,
42	const soclib::common::MappingTable &mt_ram,
43	const soclib::common::MappingTable &mt_iox,
44
45	size_t x_width,
46	size_t y_width,
47	size_t l_width,
48	size_t p_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_iobx_tgt_id, // local index
54
55	size_t int_proc_ini_id, // local index
56	size_t int_mdma_ini_id, // local index
57	size_t int_iobx_ini_id, // local index
58
59	size_t ram_xram_tgt_id, // local index
60	size_t ram_memc_ini_id, // local index
61	size_t ram_iobx_ini_id, // local index
62
63	bool is_io, // is IO cluster (IOB)?
64	size_t iox_iobx_tgt_id, // local_index
65	size_t iox_iobx_ini_id, // local index
66
67	size_t memc_ways,
68	size_t memc_sets,
69	size_t l1_i_ways,
70	size_t l1_i_sets,
71	size_t l1_d_ways,
72	size_t l1_d_sets,
73	size_t xram_latency,
74	size_t xcu_nb_inputs,
75
76	const Loader &loader,
77
78	uint32_t frozen_cycles,
79	uint32_t debug_start_cycle,
80	bool memc_debug_ok,
81	bool proc_debug_ok,
82	bool iob_debug_ok )
83	: soclib::caba::BaseModule(insname),
84	p_clk("clk"),
85	p_resetn("resetn")
86	{
87	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
88
89	size_t cluster_id = (x_id<<4) + y_id;
90
91	// Vectors of DSPIN ports for inter-cluster communications
92	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
93	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
94	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
95	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
96
97	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
98	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
99	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
100	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
101
102	// VCI ports from IOB to IOX network (only in IO clusters)
103	if ( is_io )
104	{
105	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
106	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
107	}
108
109	/////////////////////////////////////////////////////////////////////////////
110	// Hardware components
111	/////////////////////////////////////////////////////////////////////////////
112
113	//////////// PROCS
114	for (size_t p = 0; p < nb_procs; p++)
115	{
116	std::ostringstream s_proc;
117	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
118	proc[p] = new VciCcVCacheWrapper<vci_param_int,
119	dspin_int_cmd_width,
120	dspin_int_rsp_width,
121	GdbServer<Mips32ElIss> >(
122	s_proc.str().c_str(),
123	(cluster_id << p_width) + p, // GLOBAL PROC_ID
124	mt_int, // Mapping Table INT network
125	IntTab(cluster_id,p), // SRCID
126	(cluster_id << l_width) + p, // CC_GLOBAL_ID
127	8, // ITLB ways
128	8, // ITLB sets
129	8, // DTLB ways
130	8, // DTLB sets
131	l1_i_ways, l1_i_sets, 16, // ICACHE size
132	l1_d_ways, l1_d_sets, 16, // DCACHE size
133	4, // WBUF nlines
134	4, // WBUF nwords
135	x_width,
136	y_width,
137	frozen_cycles, // max frozen cycles
138	debug_start_cycle,
139	proc_debug_ok);
140	}
141
142	/////////// MEMC
143	std::ostringstream s_memc;
144	s_memc << "memc_" << x_id << "_" << y_id;
145	memc = new VciMemCache<vci_param_int,
146	vci_param_ext,
147	dspin_int_rsp_width,
148	dspin_int_cmd_width>(
149	s_memc.str().c_str(),
150	mt_int, // Mapping Table INT network
151	mt_ram, // Mapping Table RAM network
152	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
153	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
154	x_width, // number of bits for x coordinate
155	y_width, // number of bits for y coordinate
156	memc_ways, memc_sets, 16, // CACHE SIZE
157	3, // MAX NUMBER OF COPIES
158	4096, // HEAP SIZE
159	8, // TRANSACTION TABLE DEPTH
160	8, // UPDATE TABLE DEPTH
161	8, // INVALIDATE TABLE DEPTH
162	debug_start_cycle,
163	memc_debug_ok );
164
165	std::ostringstream s_wi_memc;
166	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
167	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
168	dspin_ram_cmd_width,
169	dspin_ram_rsp_width>(
170	s_wi_memc.str().c_str(),
171	x_width + y_width + l_width);
172
173	/////////// XICU
174	std::ostringstream s_xicu;
175	s_xicu << "xicu_" << x_id << "_" << y_id;
176	xicu = new VciXicu<vci_param_int>(
177	s_xicu.str().c_str(),
178	mt_int, // mapping table INT network
179	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
180	xcu_nb_inputs, // number of timer IRQs
181	xcu_nb_inputs, // number of hard IRQs
182	xcu_nb_inputs, // number of soft IRQs
183	16); // number of output IRQs
184
185	//////////// MDMA
186	std::ostringstream s_mdma;
187	s_mdma << "mdma_" << x_id << "_" << y_id;
188	mdma = new VciMultiDma<vci_param_int>(
189	s_mdma.str().c_str(),
190	mt_int,
191	IntTab(cluster_id, nb_procs), // SRCID
192	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
193	64, // burst size
194	nb_dmas); // number of IRQs
195
196	/////////// Direct LOCAL_XBAR(S)
197	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
198	size_t nb_direct_targets = is_io ? 4 : 3;
199
200	std::ostringstream s_int_xbar_d;
201	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
202	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
203	s_int_xbar_d.str().c_str(),
204	mt_int, // mapping table
205	cluster_id, // cluster id
206	nb_direct_initiators, // number of local initiators
207	nb_direct_targets, // number of local targets
208	0 ); // default target
209
210	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
211	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
212	<< x_id << "_" << y_id;
213	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
214	dspin_int_cmd_width,
215	dspin_int_rsp_width>(
216	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
217	x_width + y_width + l_width);
218
219	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
220	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
221	<< x_id << "_" << y_id;
222	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
223	dspin_int_cmd_width,
224	dspin_int_rsp_width>(
225	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
226	x_width + y_width + l_width);
227
228	//////////// Coherence LOCAL_XBAR(S)
229	std::ostringstream s_int_xbar_m2p_c;
230	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
231	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
232	s_int_xbar_m2p_c.str().c_str(),
233	mt_int, // mapping table
234	x_id, y_id, // cluster coordinates
235	x_width, y_width, l_width, // several dests
236	1, // number of local sources
237	nb_procs, // number of local dests
238	2, 2, // fifo depths
239	true, // pseudo CMD
240	false, // no routing table
241	true ); // broacast
242
243	std::ostringstream s_int_xbar_p2m_c;
244	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
245	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
246	s_int_xbar_p2m_c.str().c_str(),
247	mt_int, // mapping table
248	x_id, y_id, // cluster coordinates
249	x_width, y_width, 0, // only one dest
250	nb_procs, // number of local sources
251	1, // number of local dests
252	2, 2, // fifo depths
253	false, // pseudo RSP
254	false, // no routing table
255	false ); // no broacast
256
257	std::ostringstream s_int_xbar_clack_c;
258	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
259	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
260	s_int_xbar_clack_c.str().c_str(),
261	mt_int, // mapping table
262	x_id, y_id, // cluster coordinates
263	x_width, y_width, l_width,
264	1, // number of local sources
265	nb_procs, // number of local targets
266	1, 1, // fifo depths
267	true, // CMD
268	false, // no routing table
269	false); // broadcast
270
271	////////////// INT ROUTER(S)
272	std::ostringstream s_int_router_cmd;
273	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
274	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
275	s_int_router_cmd.str().c_str(),
276	x_id,y_id, // coordinate in the mesh
277	x_width, y_width, // x & y fields width
278	3, // nb virtual channels
279	4,4); // input & output fifo depths
280
281	std::ostringstream s_int_router_rsp;
282	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
283	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
284	s_int_router_rsp.str().c_str(),
285	x_id,y_id, // router coordinates in mesh
286	x_width, y_width, // x & y fields width
287	2, // nb virtual channels
288	4,4); // input & output fifo depths
289
290	////////////// XRAM
291	std::ostringstream s_xram;
292	s_xram << "xram_" << x_id << "_" << y_id;
293	xram = new VciSimpleRam<vci_param_ext>(
294	s_xram.str().c_str(),
295	IntTab(cluster_id, ram_xram_tgt_id),
296	mt_ram,
297	loader,
298	xram_latency);
299
300	std::ostringstream s_wt_xram;
301	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
302	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
303	dspin_ram_cmd_width,
304	dspin_ram_rsp_width>(
305	s_wt_xram.str().c_str(),
306	x_width + y_width + l_width);
307
308	///////////// RAM ROUTER(S)
309	std::ostringstream s_ram_router_cmd;
310	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
311	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
312	s_ram_router_cmd.str().c_str(),
313	x_id, y_id, // router coordinates in mesh
314	x_width, // x field width in first flit
315	y_width, // y field width in first flit
316	4, 4); // input & output fifo depths
317
318	std::ostringstream s_ram_router_rsp;
319	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
320	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
321	s_ram_router_rsp.str().c_str(),
322	x_id, y_id, // coordinates in mesh
323	x_width, // x field width in first flit
324	y_width, // y field width in first flit
325	4, 4); // input & output fifo depths
326
327
328	////////////////////// I/O CLUSTER ONLY ///////////////////////
329	if ( is_io )
330	{
331	/////////// IO_BRIDGE
332	std::ostringstream s_iob;
333	s_iob << "iob_" << x_id << "_" << y_id;
334	iob = new VciIoBridge<vci_param_int,
335	vci_param_ext>(
336	s_iob.str().c_str(),
337	mt_ram, // EXT network maptab
338	mt_int, // INT network maptab
339	mt_iox, // IOX network maptab
340	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
341	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
342	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
343	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
344	16, // cache line words
345	8, // IOTLB ways
346	8, // IOTLB sets
347	debug_start_cycle,
348	iob_debug_ok );
349
350	std::ostringstream s_iob_ram_wi;
351	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
352	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
353	dspin_ram_cmd_width,
354	dspin_ram_rsp_width>(
355	s_iob_ram_wi.str().c_str(),
356	vci_param_int::S);
357
358	std::ostringstream s_ram_xbar_cmd;
359	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
360	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
361	s_ram_xbar_cmd.str().c_str(), // name
362	mt_ram, // mapping table
363	x_id, y_id, // x, y
364	x_width, y_width, l_width, // x_width, y_width, l_width
365	2, 0, // local inputs, local outputs
366	2, 2, // in fifo, out fifo depths
367	true, // is cmd ?
368	false, // use routing table ?
369	false); // support broadcast ?
370
371	std::ostringstream s_ram_xbar_rsp;
372	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
373	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
374	s_ram_xbar_rsp.str().c_str(), // name
375	mt_ram, // mapping table
376	x_id, y_id, // x, y
377	x_width, y_width, l_width, // x_width, y_width, l_width
378	0, 2, // local inputs, local outputs
379	2, 2, // in fifo, out fifo depths
380	false, // is cmd ?
381	true, // use routing table ?
382	false); // support broadcast ?
383	} // end if IO
384
385	////////////////////////////////////
386	// Connections are defined here
387	////////////////////////////////////
388
389	// on coherence network : local srcid[proc] in [0...nb_procs-1]
390	// : local srcid[memc] = nb_procs
391
392	//////////////////////// internal CMD & RSP routers
393	int_router_cmd->p_clk (this->p_clk);
394	int_router_cmd->p_resetn (this->p_resetn);
395	int_router_rsp->p_clk (this->p_clk);
396	int_router_rsp->p_resetn (this->p_resetn);
397
398	for (int i = 0; i < 4; i++)
399	{
400	for(int k = 0; k < 3; k++)
401	{
402	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
403	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
404	}
405
406	for(int k = 0; k < 2; k++)
407	{
408	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
409	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
410	}
411	}
412
413	// local ports
414	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
415	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
416	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
417	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
418	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
419	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
420
421	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
422	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
423	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
424	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
425
426	///////////////////// CMD DSPIN local crossbar direct
427	int_xbar_d->p_clk (this->p_clk);
428	int_xbar_d->p_resetn (this->p_resetn);
429	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
430	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
431
432	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
433	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
434	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
435	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
436	for (size_t p = 0; p < nb_procs; p++)
437	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
438
439	if ( is_io )
440	{
441	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
442	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
443	}
444
445	int_wi_gate_d->p_clk (this->p_clk);
446	int_wi_gate_d->p_resetn (this->p_resetn);
447	int_wi_gate_d->p_vci (signal_int_vci_l2g);
448	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
449	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
450
451	int_wt_gate_d->p_clk (this->p_clk);
452	int_wt_gate_d->p_resetn (this->p_resetn);
453	int_wt_gate_d->p_vci (signal_int_vci_g2l);
454	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
455	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
456
457	////////////////////// M2P DSPIN local crossbar coherence
458	int_xbar_m2p_c->p_clk (this->p_clk);
459	int_xbar_m2p_c->p_resetn (this->p_resetn);
460	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
461	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
462	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
463	for (size_t p = 0; p < nb_procs; p++)
464	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
465
466	////////////////////////// P2M DSPIN local crossbar coherence
467	int_xbar_p2m_c->p_clk (this->p_clk);
468	int_xbar_p2m_c->p_resetn (this->p_resetn);
469	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
470	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
471	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
472	for (size_t p = 0; p < nb_procs; p++)
473	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
474
475	////////////////////// CLACK DSPIN local crossbar coherence
476	int_xbar_clack_c->p_clk (this->p_clk);
477	int_xbar_clack_c->p_resetn (this->p_resetn);
478	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
479	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
480	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
481	for (size_t p = 0; p < nb_procs; p++)
482	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
483
484	//////////////////////////////////// Processors
485	for (size_t p = 0; p < nb_procs; p++)
486	{
487	proc[p]->p_clk (this->p_clk);
488	proc[p]->p_resetn (this->p_resetn);
489	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
490	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
491	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
492	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
493
494	for ( size_t j = 0 ; j < 6 ; j++)
495	{
496	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
497	else proc[p]->p_irq[j] (signal_false);
498	}
499	}
500
501	///////////////////////////////////// XICU
502	xicu->p_clk (this->p_clk);
503	xicu->p_resetn (this->p_resetn);
504	xicu->p_vci (signal_int_vci_tgt_xicu);
505	for ( size_t i=0 ; i < 16 ; i++)
506	{
507	xicu->p_irq[i] (signal_proc_it[i]);
508	}
509	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
510	{
511	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
512	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
513	else xicu->p_hwi[i] (signal_false);
514	}
515
516	///////////////////////////////////// MEMC
517	memc->p_clk (this->p_clk);
518	memc->p_resetn (this->p_resetn);
519	memc->p_vci_ixr (signal_ram_vci_ini_memc);
520	memc->p_vci_tgt (signal_int_vci_tgt_memc);
521	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
522	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
523	memc->p_dspin_clack (signal_int_dspin_clack_memc);
524	memc->p_irq (signal_irq_memc);
525
526	// wrapper to RAM network
527	memc_ram_wi->p_clk (this->p_clk);
528	memc_ram_wi->p_resetn (this->p_resetn);
529	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
530	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
531	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
532
533	//////////////////////////////////// XRAM
534	xram->p_clk (this->p_clk);
535	xram->p_resetn (this->p_resetn);
536	xram->p_vci (signal_ram_vci_tgt_xram);
537
538	// wrapper to RAM network
539	xram_ram_wt->p_clk (this->p_clk);
540	xram_ram_wt->p_resetn (this->p_resetn);
541	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
542	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
543	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
544
545	/////////////////////////////////// MDMA
546	mdma->p_clk (this->p_clk);
547	mdma->p_resetn (this->p_resetn);
548	mdma->p_vci_target (signal_int_vci_tgt_mdma);
549	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
550	for (size_t i=0 ; i<nb_dmas ; i++)
551	mdma->p_irq[i] (signal_irq_mdma[i]);
552
553	//////////////////////////// RAM network CMD & RSP routers
554	ram_router_cmd->p_clk (this->p_clk);
555	ram_router_cmd->p_resetn (this->p_resetn);
556	ram_router_rsp->p_clk (this->p_clk);
557	ram_router_rsp->p_resetn (this->p_resetn);
558	for( size_t n=0 ; n<4 ; n++)
559	{
560	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
561	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
562	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
563	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
564	}
565
566	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
567	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
568
569	if ( is_io )
570	{
571	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
572	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
573	}
574	else
575	{
576	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
577	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
578	}
579
580	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
581	if ( is_io )
582	{
583	// IO bridge
584	iob->p_clk (this->p_clk);
585	iob->p_resetn (this->p_resetn);
586	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
587	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
588	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
589	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
590	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
591
592	// initiator wrapper to RAM network
593	iob_ram_wi->p_clk (this->p_clk);
594	iob_ram_wi->p_resetn (this->p_resetn);
595	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
596	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
597	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
598
599	// crossbar between MEMC and IOB to RAM network
600	ram_xbar_cmd->p_clk (this->p_clk);
601	ram_xbar_cmd->p_resetn (this->p_resetn);
602	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
603	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
604	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
605	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
606
607	ram_xbar_rsp->p_clk (this->p_clk);
608	ram_xbar_rsp->p_resetn (this->p_resetn);
609	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
610	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
611	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
612	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
613	}
614
615	SC_METHOD(init);
616
617	} // end constructor
618
619	tmpl(void)::init()
620	{
621	signal_ram_dspin_cmd_false.write = false;
622	signal_ram_dspin_rsp_false.read = true;
623	} // end init
624
625	}}
626
627
628	// Local Variables:
629	// tab-width: 3
630	// c-basic-offset: 3
631	// c-file-offsets:((innamespace . 0)(inline-open . 0))
632	// indent-tabs-mode: nil
633	// End:
634
635	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
636

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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