| 1 | #!/usr/bin/env python |
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| 2 | |
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| 3 | from math import log, ceil |
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| 4 | from mapping import * |
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| 5 | |
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| 6 | ############################################################################### |
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| 7 | # file : arch.py (for the tsar_generic_leti architecture) |
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| 8 | # date : may 2014 |
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| 9 | # author : Alain Greiner |
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| 10 | ############################################################################### |
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| 11 | # This file contains a mapping generator for the "tsar_generic_leti" platform. |
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| 12 | # This includes both the hardware architecture (clusters, processors, |
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| 13 | # peripherals, physical space segmentation) and the mapping of all boot |
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| 14 | # and kernel objects (global vsegs). |
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| 15 | # |
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| 16 | # The x_size & y_size parameters define the total number of clusters. |
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| 17 | # The upper row (y = y_size-1) does not contain processors or memory. |
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| 18 | # |
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| 19 | # It does not use the IOB component: |
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| 20 | # The external peripherals are located in cluster[x_size-1][y_size-1]. |
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| 21 | # |
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| 22 | # It does not use an external ROM, as the preloader code is (pre)loaded |
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| 23 | # at address 0x0, in the physical memory of cluster[0][0]. |
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| 24 | # |
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| 25 | # It can use an - optional - RAMDISK located in cluster[0][0]. |
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| 26 | # |
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| 27 | # The others hardware parameters are: |
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| 28 | # - fbf_width : frame_buffer width = frame_buffer heigth |
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| 29 | # - nb_ttys : number of TTY channels |
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| 30 | # - nb_nics : number of NIC channels |
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| 31 | # - nb_cmas : number of CMA channels |
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| 32 | # - irq_per_proc : number of input IRQs per processor |
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| 33 | # - use_ramdisk : use a RAMDISK when True |
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| 34 | # - peri_increment : address increment for replicated peripherals |
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| 35 | # |
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| 36 | # Regarding the boot and kernel vsegs mapping : |
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| 37 | # - We use one big physical page (2 Mbytes) for the preloader and the four |
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| 38 | # boot vsegs, all allocated in cluster[0,0]. |
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| 39 | # - We use the 16 next big pages in cluster[0][0] to implement the RAMDISK. |
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| 40 | # - We use one big page per cluster for the replicated kernel code vsegs. |
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| 41 | # - We use one big page in cluster[0][0] for the kernel data vseg. |
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| 42 | # - We use one big page per cluster for the distributed kernel heap vsegs. |
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| 43 | # - We use one big page per cluster for the distributed ptab vsegs. |
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| 44 | # - We use small physical pages (4 Kbytes) per cluster for the schedulers. |
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| 45 | # - We use one big page for each external peripheral in IO cluster, |
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| 46 | # - We use one small page per cluster for each internal peripheral. |
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| 47 | ############################################################################### |
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| 48 | |
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| 49 | ######################## |
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| 50 | def arch( x_size = 2, |
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| 51 | y_size = 2, |
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| 52 | nb_procs = 4, |
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| 53 | nb_ttys = 1, |
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| 54 | fbf_width = 128 ): |
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| 55 | |
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| 56 | ### define architecture constants |
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| 57 | |
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| 58 | nb_nics = 1 |
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| 59 | nb_cmas = 2 |
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| 60 | x_io = x_size - 1 |
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| 61 | y_io = y_size - 1 |
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| 62 | x_width = 4 |
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| 63 | y_width = 4 |
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| 64 | p_width = 2 |
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| 65 | paddr_width = 40 |
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| 66 | irq_per_proc = 4 |
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| 67 | use_ramdisk = False |
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| 68 | peri_increment = 0x10000 # distributed peripherals vbase increment |
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| 69 | reset_address = 0x00000000 # wired preloader pbase address |
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| 70 | |
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| 71 | ### parameters checking |
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| 72 | |
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| 73 | assert( nb_procs <= 4 ) |
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| 74 | |
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| 75 | assert( x_size <= (1 << x_width) ) |
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| 76 | |
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| 77 | assert( y_size <= (1 << y_width) ) |
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| 78 | |
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| 79 | ### define type and name |
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| 80 | |
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| 81 | platform_type = 'tsar_leti' |
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| 82 | platform_name = '%s_%d_%d_%d' % (platform_type, x_size, y_size, nb_procs ) |
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| 83 | |
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| 84 | ### define physical segments replicated in all clusters |
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| 85 | ### the base address is extended by the cluster_xy (8 bits) |
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| 86 | |
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| 87 | ram_base = 0x00000000 |
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| 88 | ram_size = 0x4000000 # 64 Mbytes |
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| 89 | |
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| 90 | xcu_base = 0xF0000000 |
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| 91 | xcu_size = 0x1000 # 4 Kbytes |
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| 92 | |
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| 93 | mmc_base = 0xF1000000 |
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| 94 | mmc_size = 0x1000 # 4 Kbytes |
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| 95 | |
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| 96 | ### define physical segments for external peripherals |
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| 97 | ## These segments are only defined in cluster_io |
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| 98 | |
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| 99 | bdv_base = 0xF2000000 |
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| 100 | bdv_size = 0x1000 # 4kbytes |
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| 101 | |
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| 102 | tty_base = 0xF4000000 |
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| 103 | tty_size = 0x4000 # 16 Kbytes |
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| 104 | |
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| 105 | nic_base = 0xF7000000 |
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| 106 | nic_size = 0x80000 # 512 kbytes |
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| 107 | |
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| 108 | cma_base = 0xF8000000 |
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| 109 | cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics |
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| 110 | |
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| 111 | pic_base = 0xF9000000 |
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| 112 | pic_size = 0x1000 # 4 Kbytes |
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| 113 | |
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| 114 | fbf_base = 0xF3000000 |
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| 115 | fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes |
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| 116 | |
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| 117 | |
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| 118 | ### define preloader & bootloader vsegs base addresses and sizes |
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| 119 | ### We want to pack these 5 vsegs in the same big page |
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| 120 | ### => boot cost is one BPP in cluster[0][0] |
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| 121 | |
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| 122 | preloader_vbase = 0x00000000 # ident |
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| 123 | preloader_size = 0x00010000 # 64 Kbytes |
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| 124 | |
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| 125 | boot_mapping_vbase = 0x00010000 # ident |
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| 126 | boot_mapping_size = 0x00080000 # 512 Kbytes |
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| 127 | |
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| 128 | boot_code_vbase = 0x00090000 # ident |
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| 129 | boot_code_size = 0x00040000 # 256 Kbytes |
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| 130 | |
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| 131 | boot_data_vbase = 0x000D0000 # ident |
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| 132 | boot_data_size = 0x000B0000 # 704 Kbytes |
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| 133 | |
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| 134 | boot_stack_vbase = 0x00180000 # ident |
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| 135 | boot_stack_size = 0x00080000 # 512 Kbytes |
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| 136 | |
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| 137 | ### define ramdisk vseg / must be identity mapping in cluster[0][0] |
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| 138 | ### occupies 15 BPP after the boot |
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| 139 | ramdisk_vbase = 0x00200000 |
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| 140 | ramdisk_size = 0x02000000 # 32 Mbytes |
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| 141 | |
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| 142 | ### define kernel vsegs base addresses and sizes |
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| 143 | ### code, init, ptab, heap & sched vsegs are replicated in all clusters. |
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| 144 | ### data & uncdata vsegs are only mapped in cluster[0][0]. |
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| 145 | |
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| 146 | kernel_code_vbase = 0x80000000 |
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| 147 | kernel_code_size = 0x00100000 # 1 Mbytes per cluster |
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| 148 | |
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| 149 | kernel_init_vbase = 0x80100000 |
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| 150 | kernel_init_size = 0x00100000 # 1 Mbytes per cluster |
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| 151 | |
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| 152 | kernel_data_vbase = 0x90000000 |
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| 153 | kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0] |
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| 154 | |
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| 155 | kernel_ptab_vbase = 0xE0000000 |
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| 156 | kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster |
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| 157 | |
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| 158 | kernel_heap_vbase = 0xD0000000 |
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| 159 | kernel_heap_size = 0x00200000 # 2 Mbytes per cluster |
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| 160 | |
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| 161 | kernel_sched_vbase = 0xA0000000 |
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| 162 | kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster |
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| 163 | |
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| 164 | ##################### |
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| 165 | ### create mapping |
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| 166 | ##################### |
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| 167 | |
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| 168 | mapping = Mapping( name = platform_name, |
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| 169 | x_size = x_size, |
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| 170 | y_size = y_size, |
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| 171 | nprocs = nb_procs, |
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| 172 | x_width = x_width, |
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| 173 | y_width = y_width, |
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| 174 | p_width = p_width, |
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| 175 | paddr_width = paddr_width, |
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| 176 | coherence = True, |
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| 177 | irq_per_proc = irq_per_proc, |
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| 178 | use_ramdisk = use_ramdisk, |
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| 179 | x_io = x_io, |
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| 180 | y_io = y_io, |
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| 181 | peri_increment = peri_increment, |
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| 182 | reset_address = reset_address, |
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| 183 | ram_base = ram_base, |
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| 184 | ram_size = ram_size ) |
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| 185 | |
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| 186 | ########################### |
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| 187 | ### Hardware Description |
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| 188 | ########################### |
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| 189 | |
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| 190 | for x in xrange( x_size ): |
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| 191 | for y in xrange( y_size ): |
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| 192 | cluster_xy = (x << y_width) + y; |
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| 193 | offset = cluster_xy << (paddr_width - x_width - y_width) |
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| 194 | |
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| 195 | ### components replicated in all clusters but the upper row |
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| 196 | if ( y < (y_size - 1) ): |
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| 197 | |
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| 198 | ram = mapping.addRam( 'RAM', base = ram_base + offset, |
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| 199 | size = ram_size ) |
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| 200 | |
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| 201 | mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, |
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| 202 | size = mmc_size, ptype = 'MMC' ) |
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| 203 | |
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| 204 | xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, |
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| 205 | size = xcu_size, ptype = 'XCU', |
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| 206 | channels = nb_procs * irq_per_proc, |
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| 207 | arg0 = 16, arg1 = 16, arg2 = 16 ) |
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| 208 | |
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| 209 | mapping.addIrq( xcu, index = 8, isrtype = 'ISR_MMC' ) |
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| 210 | |
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| 211 | for p in xrange ( nb_procs ): |
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| 212 | mapping.addProc( x, y, p ) |
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| 213 | |
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| 214 | ### external peripherals in cluster_io |
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| 215 | if ( (x==x_io) and (y==y_io) ): |
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| 216 | |
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| 217 | bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size, |
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| 218 | ptype = 'IOC', subtype = 'BDV' ) |
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| 219 | |
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| 220 | tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size, |
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| 221 | ptype = 'TTY', channels = nb_ttys ) |
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| 222 | |
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| 223 | nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size, |
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| 224 | ptype = 'NIC', channels = nb_nics ) |
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| 225 | |
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| 226 | cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size, |
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| 227 | ptype = 'CMA', channels = nb_cmas ) |
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| 228 | |
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| 229 | fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size, |
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| 230 | ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width ) |
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| 231 | |
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| 232 | pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size, |
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| 233 | ptype = 'PIC', channels = 32 ) |
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| 234 | |
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| 235 | mapping.addIrq( pic, index = 0 , isrtype = 'ISR_NIC_RX', channel = 0 ) |
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| 236 | mapping.addIrq( pic, index = 1 , isrtype = 'ISR_NIC_RX', channel = 1 ) |
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| 237 | |
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| 238 | mapping.addIrq( pic, index = 2 , isrtype = 'ISR_NIC_TX', channel = 0 ) |
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| 239 | mapping.addIrq( pic, index = 3 , isrtype = 'ISR_NIC_TX', channel = 1 ) |
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| 240 | |
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| 241 | mapping.addIrq( pic, index = 4 , isrtype = 'ISR_CMA' , channel = 0 ) |
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| 242 | mapping.addIrq( pic, index = 5 , isrtype = 'ISR_CMA' , channel = 1 ) |
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| 243 | mapping.addIrq( pic, index = 6 , isrtype = 'ISR_CMA' , channel = 2 ) |
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| 244 | mapping.addIrq( pic, index = 7 , isrtype = 'ISR_CMA' , channel = 3 ) |
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| 245 | |
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| 246 | mapping.addIrq( pic, index = 8 , isrtype = 'ISR_BDV' , channel = 0 ) |
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| 247 | |
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| 248 | mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) |
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| 249 | mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 ) |
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| 250 | mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 ) |
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| 251 | mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 ) |
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| 252 | mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 ) |
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| 253 | mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 ) |
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| 254 | mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 ) |
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| 255 | mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 ) |
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| 256 | |
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| 257 | ################################### |
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| 258 | ### boot & kernel vsegs mapping |
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| 259 | ################################### |
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| 260 | |
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| 261 | ### global vsegs for preloader & boot_loader are mapped in cluster[0][0] |
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| 262 | ### => same flags CXW_ / identity mapping / non local / big page |
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| 263 | |
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| 264 | mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size, |
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| 265 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 266 | identity = True, local = False, big = True ) |
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| 267 | |
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| 268 | mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, |
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| 269 | 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', |
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| 270 | identity = True, local = False, big = True ) |
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| 271 | |
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| 272 | mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, |
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| 273 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 274 | identity = True, local = False, big = True ) |
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| 275 | |
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| 276 | mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, |
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| 277 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 278 | identity = True, local = False, big = True ) |
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| 279 | |
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| 280 | mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, |
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| 281 | 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 282 | identity = True, local = False, big = True ) |
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| 283 | |
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| 284 | ### global vseg for RAM-DISK in cluster[0][0] |
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| 285 | ### identity mapping / non local / big pages |
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| 286 | if use_ramdisk: |
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| 287 | |
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| 288 | mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size, |
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| 289 | 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', |
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| 290 | identity = True, local = True, big = True ) |
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| 291 | |
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| 292 | ### global vsegs kernel_code, kernel_init : local / big page |
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| 293 | ### replicated in all clusters containing processors |
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| 294 | ### same content => same name / same vbase |
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| 295 | for x in xrange( x_size ): |
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| 296 | for y in xrange( y_size - 1 ): |
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| 297 | |
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| 298 | mapping.addGlobal( 'seg_kernel_code', |
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| 299 | kernel_code_vbase, kernel_code_size, |
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| 300 | 'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM', |
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| 301 | binpath = 'build/kernel/kernel.elf', |
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| 302 | local = True, big = True ) |
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| 303 | |
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| 304 | mapping.addGlobal( 'seg_kernel_init', |
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| 305 | kernel_init_vbase, kernel_init_size, |
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| 306 | 'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM', |
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| 307 | binpath = 'build/kernel/kernel.elf', |
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| 308 | local = True, big = True ) |
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| 309 | |
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| 310 | ### global vseg kernel_data: non local / big page |
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| 311 | ### Only mapped in cluster[0][0] |
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| 312 | mapping.addGlobal( 'seg_kernel_data', |
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| 313 | kernel_data_vbase, kernel_data_size, |
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| 314 | 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', |
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| 315 | binpath = 'build/kernel/kernel.elf', |
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| 316 | local = False, big = True ) |
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| 317 | |
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| 318 | ### Global vsegs kernel_ptab_x_y: non local / big page |
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| 319 | ### replicated in all clusters containing processors |
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| 320 | ### different content => name & vbase indexed by (x,y) |
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| 321 | for x in xrange( x_size ): |
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| 322 | for y in xrange( y_size - 1 ): |
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| 323 | offset = ((x << y_width) + y) * kernel_ptab_size |
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| 324 | |
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| 325 | mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), |
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| 326 | kernel_ptab_vbase + offset, kernel_ptab_size, |
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| 327 | 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', |
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| 328 | local = False, big = True ) |
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| 329 | |
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| 330 | ### global vsegs kernel_heap_x_y : non local / big pages |
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| 331 | ### distributed in all clusters containing processors |
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| 332 | ### different content => name & vbase indexed by (x,y) |
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| 333 | for x in xrange( x_size ): |
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| 334 | for y in xrange( y_size - 1 ): |
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| 335 | offset = ((x << y_width) + y) * kernel_heap_size |
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| 336 | |
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| 337 | mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), |
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| 338 | kernel_heap_vbase + offset , kernel_heap_size, |
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| 339 | 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', |
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| 340 | local = False, big = True ) |
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| 341 | |
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| 342 | ### global vsegs for external peripherals: non local / big page |
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| 343 | ### only mapped in cluster_io |
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| 344 | mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, |
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| 345 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'BDV', |
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| 346 | local = False, big = True ) |
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| 347 | |
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| 348 | mapping.addGlobal( 'seg_tty', tty_base, tty_size, |
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| 349 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'TTY', |
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| 350 | local = False, big = True ) |
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| 351 | |
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| 352 | mapping.addGlobal( 'seg_nic', nic_base, nic_size, |
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| 353 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'NIC', |
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| 354 | local = False, big = True ) |
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| 355 | |
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| 356 | mapping.addGlobal( 'seg_cma', cma_base, cma_size, |
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| 357 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'CMA', |
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| 358 | local = False, big = True ) |
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| 359 | |
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| 360 | mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, |
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| 361 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'FBF', |
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| 362 | local = False, big = True ) |
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| 363 | |
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| 364 | mapping.addGlobal( 'seg_pic', pic_base, pic_size, |
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| 365 | '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'PIC', |
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| 366 | local = False, big = True ) |
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| 367 | |
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| 368 | ### global vsegs for internal peripherals : non local / small pages |
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| 369 | ### allocated in all clusters containing processors |
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| 370 | ### name and vbase indexed by (x,y) |
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| 371 | for x in xrange( x_size ): |
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| 372 | for y in xrange( y_size - 1 ): |
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| 373 | offset = ((x << y_width) + y) * peri_increment |
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| 374 | |
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| 375 | mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), |
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| 376 | xcu_base + offset, xcu_size, |
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| 377 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', |
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| 378 | local = False, big = False ) |
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| 379 | |
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| 380 | mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), |
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| 381 | mmc_base + offset, mmc_size, |
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| 382 | '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', |
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| 383 | local = False, big = False ) |
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| 384 | |
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| 385 | ### global vsegs kernel_sched : non local / small pages |
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| 386 | ### allocated in all clusters containing processors |
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| 387 | ### different content => name & vbase indexed by (x,y) |
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| 388 | for x in xrange( x_size ): |
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| 389 | for y in xrange( y_size - 1 ): |
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| 390 | offset = ((x << y_width) + y) * kernel_ptab_size |
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| 391 | |
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| 392 | mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), |
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| 393 | kernel_sched_vbase + offset , kernel_sched_size, |
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| 394 | 'C_W_', vtype = 'SCHED', x = x, y = y, pseg = 'RAM', |
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| 395 | local = False, big = False ) |
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| 396 | |
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| 397 | return mapping |
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| 398 | |
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| 399 | ########################## platform test ############################################# |
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| 400 | |
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| 401 | if __name__ == '__main__': |
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| 402 | |
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| 403 | mapping = arch( x_size = 2, |
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| 404 | y_size = 2, |
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| 405 | nb_procs = 2 ) |
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| 406 | |
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| 407 | # print mapping.netbsd_dts() |
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| 408 | |
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| 409 | print mapping.xml() |
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| 410 | |
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| 411 | # print mapping.giet_vsegs() |
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| 412 | |
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| 413 | |
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| 414 | # Local Variables: |
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| 415 | # tab-width: 4; |
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| 416 | # c-basic-offset: 4; |
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| 417 | # c-file-offsets:((innamespace . 0)(inline-open . 0)); |
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| 418 | # indent-tabs-mode: nil; |
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| 419 | # End: |
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| 420 | # |
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| 421 | # vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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| 422 | |
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