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top.cpp @ 1060

Last change on this file since 1060 was 1057, checked in by alain, 6 years ago
Introduce an arch_info.py file for ALMOS-MKH
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1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp (for tsar_generic_leti platform)
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : february 2013 / updated january 2015
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture, fully compatible
9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
10	// in the framework of the SHARP project.
11	//
12	// The processor is a MIPS32 processor wrapped in a GDB server
13	// (this is defined in the tsar_leti_cluster).
14	//
15	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
16	// and the number of processors per cluster (NB_PROCS_MAX).
17	// The NB_PROCS_MAX parameter cannot be larger than 4.
18	// Others parameters are the frame buffer size, the disk controller type
19	// the number of TTY channels, the number of NIC channels.
20	//
21	// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
22	// and are connected to an IO bus (implemented as a vci_local_crossbar):
23	// - DISK : block device controller
24	// - MNIC : multi-channel ethernet controller
25	// - MTTY : multi-channel tty controller
26	// - FBUF : frame buffer controller
27	// - IOPI : HWI to SWI translator
28	//
29	// This IO bus is directly connected to the north ports of the CMD/RSP
30	// routers in cluster[X_SIZE-1][Y_SIZE-1] through VCI/DSPIN wrappers.
31	// All other clusters in the upper row are empty: no processors, no ram.
32	// The X_SIZE parameter must be larger than 0, but no larger than 16.
33	// The Y_SIZE parameter must be larger than 1, but no larger than 16.
34	//
35	// We don't use an external ROM, as the boot code is (pre)loaded
36	// in RAM in cluster[0][0] at address 0x0.
37	//
38	// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
39	//
40	// The physical address space is 40 bits.
41	// The 8 address MSB bits define the cluster index.
42	//
43	// Besides the processors, each cluster contains:
44	// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
45	// - 1 vci_mem_cache
46	// - 1 vci_xicu
47	// - 1 vci_simple_ram (to emulate the L3 cache).
48	//
49	// Each processor receives 4 consecutive IRQ lines from the local XICU.
50	// The number of PTI and WTI IRQs is bounded to 16.
51	//
52	// In all clusters, the MEMC IRQ line (signaling a late write error)
53	// is connected to XICU HWI[8]
54	//
55	// For all external peripherals, the hardware interrupts (HWI) are
56	// translated to write interrupts (WTI) by the iopic component:
57	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
58	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
59	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
60	// - IOPIC HWI[8] connected to IRQ_DISK
61	// - IOPIC HWI[15:9] unused (grounded)
62	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
63	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
64	//
65	// The cluster internal architecture is defined in file tsar_leti_cluster,
66	// that must be considered as an extension of this top.cpp file.
67	////////////////////////////////////////////////////////////////////////////
68	// The following parameters must be defined in the hard_config.h file :
69	// - X_WIDTH : number of bits for x coordinate (must be 4)
70	// - Y_WIDTH : number of bits for y coordinate (must be 4)
71	// - P_WIDTH : number of bits for local processor coordinate
72	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
73	// - Y_SIZE : number of clusters in a column (1,2,4,8)
74	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
75	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
76	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
77	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
78	// - FBUF_X_SIZE : number of pixels per line for frame buffer
79	// - FBUF_Y_SIZE : number of lines for frame buffer
80	// - XCU_NB_HWI : number of XCU HWIs (must be 16)
81	// - XCU_NB_PTI : number of XCU PTIs (must be 16)
82	// - XCU_NB_WTI : number of XCU WTIs (must be 16)
83	// - XCU_NB_OUT : number of XCU output (must be 16)
84	// - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC / RDK)
85	//
86	// Some other hardware parameters are not used when compiling the OS,
87	// and are only defined in this top.cpp file:
88	// - XRAM_LATENCY : external ram latency
89	// - L1_IWAYS : L1 cache instruction number of ways
90	// - L1_ISETS : L1 cache instruction number of sets
91	// - L1_DWAYS : L1 cache data number of ways
92	// - L1_DSETS : L1 cache data number of sets
93	// - DISK_IMAGE_NAME : pathname for block device disk image
94	/////////////////////////////////////////////////////////////////////////
95	// General policy for 40 bits physical address decoding:
96	// All physical segments base addresses are multiple of 1 Mbytes
97	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
98	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
99	// the cluster index, and the LADR bits define the local index:
100	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
101	// \| 4 \| 4 \| 8 \| 24 \|
102	/////////////////////////////////////////////////////////////////////////
103	// General policy for 14 bits SRCID decoding:
104	// Each component is identified by (x_id, y_id, l_id) tuple.
105	// \|X_ID\|Y_ID\| L_ID \|
106	// \| 4 \| 4 \| 6 \|
107	/////////////////////////////////////////////////////////////////////////
108
109	#include <systemc>
110	#include <sys/time.h>
111	#include <iostream>
112	#include <sstream>
113	#include <cstdlib>
114	#include <cstdarg>
115	#include <stdint.h>
116
117	#include "gdbserver.h"
118	#include "mapping_table.h"
119
120	#include "tsar_leti_cluster.h"
121	#include "vci_local_crossbar.h"
122	#include "vci_dspin_initiator_wrapper.h"
123	#include "vci_dspin_target_wrapper.h"
124	#include "vci_multi_tty.h"
125	#include "vci_multi_nic.h"
126	#include "vci_chbuf_dma.h"
127	#include "vci_block_device_tsar.h"
128	#include "vci_multi_ahci.h"
129	#include "vci_framebuffer.h"
130	#include "vci_iopic.h"
131
132	#include "alloc_elems.h"
133
134	///////////////////////////////////////////////////
135	// Main hardware parameters values
136	///////////////////////////////////////////////////
137
138	#include "hard_config.h"
139
140	///////////////////////////////////////////////////////////////////////////////////////
141	// Secondary Hardware Parameters
142	///////////////////////////////////////////////////////////////////////////////////////
143
144	#define XMAX X_SIZE // actual number of columns in 2D mesh
145	#define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh
146
147	#define XRAM_LATENCY 0
148
149	#define MEMC_WAYS 16
150	#define MEMC_SETS 256
151
152	#define L1_IWAYS 4
153	#define L1_ISETS 64
154
155	#define L1_DWAYS 4
156	#define L1_DSETS 64
157
158	#define DISK_IMAGE_NAME "virt_hdd.dmg"
159
160	#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf"
161
162	#define NORTH 0
163	#define SOUTH 1
164	#define EAST 2
165	#define WEST 3
166
167	///////////////////////////////////////////////////
168	// Parallelisation
169	///////////////////////////////////////////////////
170
171	#define USE_OPENMP _OPENMP
172
173	#if USE_OPENMP
174	#include <omp.h>
175	#endif
176
177	///////////////////////////////////////////////////
178	// cluster index (from x,y coordinates)
179	///////////////////////////////////////////////////
180
181	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
182
183	///////////////////////////////////////////////////////////
184	// DSPIN parameters
185	///////////////////////////////////////////////////////////
186
187	#define dspin_cmd_width 39
188	#define dspin_rsp_width 32
189
190	///////////////////////////////////////////////////////////
191	// VCI parameters
192	///////////////////////////////////////////////////////////
193
194	#define vci_cell_width_int 4
195	#define vci_cell_width_ext 8
196	#define vci_address_width 40
197	#define vci_plen_width 8
198	#define vci_rerror_width 1
199	#define vci_clen_width 1
200	#define vci_rflag_width 1
201	#define vci_srcid_width 14
202	#define vci_pktid_width 4
203	#define vci_trdid_width 4
204	#define vci_wrplen_width 1
205
206
207
208	///////////////////////////////////////////////////////////////////////////////////////
209	// DEBUG Parameters default values
210	///////////////////////////////////////////////////////////////////////////////////////
211
212	#define MAX_FROZEN_CYCLES 500000
213
214	///////////////////////////////////////////////////////////////////////////////////////
215	// LOCAL TGTID & SRCID definition
216	// For all components: global TGTID = global SRCID = cluster_index
217	///////////////////////////////////////////////////////////////////////////////////////
218
219	#define MEMC_TGTID 0
220	#define XICU_TGTID 1
221	#define MTTY_TGTID 2
222	#define DISK_TGTID 3
223	#define FBUF_TGTID 4
224	#define MNIC_TGTID 5
225	#define CDMA_TGTID 6
226	#define IOPI_TGTID 7
227
228	#define DISK_SRCID NB_PROCS_MAX
229	#define CDMA_SRCID NB_PROCS_MAX + 1
230	#define IOPI_SRCID NB_PROCS_MAX + 2
231
232	bool stop_called = false;
233
234	/////////////////////////////////
235	int _main(int argc, char *argv[])
236	{
237	using namespace sc_core;
238	using namespace soclib::caba;
239	using namespace soclib::common;
240
241	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
242	size_t threads = 1; // simulator's threads number
243	bool trace_ok = false; // trace activated
244	uint32_t trace_from = 0; // trace start cycle
245	bool trace_proc_ok = false; // detailed proc trace activated
246	size_t trace_memc_ok = false; // detailed memc trace activated
247	size_t trace_memc_id = 0; // index of memc to be traced
248	size_t trace_proc_id = 0; // index of proc to be traced
249	char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code
250	char disk_name[256] = DISK_IMAGE_NAME; // pathname for DISK image
251	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug
252	struct timeval t1,t2;
253	uint64_t ms1,ms2;
254
255	////////////// command line arguments //////////////////////
256	if (argc > 1)
257	{
258	for (int n = 1; n < argc; n = n + 2)
259	{
260	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
261	{
262	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
263	}
264	else if ((strcmp(argv[n],"-SOFT") == 0) && (n + 1 < argc))
265	{
266	strcpy(soft_name, argv[n + 1]);
267	}
268	else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))
269	{
270	strcpy(disk_name, argv[n + 1]);
271	}
272	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
273	{
274	trace_ok = true;
275	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
276	}
277	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
278	{
279	trace_memc_ok = true;
280	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
281	size_t x = trace_memc_id >> Y_WIDTH;
282	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
283
284	assert( (x < XMAX) and (y < (YMAX)) and
285	"MEMCID parameter doesxn't fit valid XMAX/YMAX");
286	}
287	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
288	{
289	trace_proc_ok = true;
290	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
291	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
292	size_t x = cluster_xy >> Y_WIDTH;
293	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
294	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
295
296	assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
297	"PROCID parameter refers a not valid processor");
298	}
299	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
300	{
301	threads = (size_t) strtol(argv[n + 1], NULL, 0);
302	threads = (threads < 1) ? 1 : threads;
303	}
304	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
305	{
306	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
307	}
308	else
309	{
310	std::cout << " Arguments are (key,value) couples." << std::endl;
311	std::cout << " The order is not important." << std::endl;
312	std::cout << " Accepted arguments are :" << std::endl << std::endl;
313	std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;
314	std::cout << " - DEBUG debug_start_cycle" << std::endl;
315	std::cout << " - THREADS simulator's threads number" << std::endl;
316	std::cout << " - FROZEN max_number_of_lines" << std::endl;
317	std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;
318	std::cout << " - PROCID index_proc_to_be_traced" << std::endl;
319	exit(0);
320	}
321	}
322	}
323
324	// checking hardware parameters
325	assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
326	"Illegal X_SIZE parameter" );
327
328	assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
329	"Illegal Y_SIZE parameter" );
330
331	assert( (P_WIDTH <= 2) and
332	"P_WIDTH parameter cannot be larger than 2" );
333
334	assert( (NB_PROCS_MAX <= 4) and
335	"Illegal NB_PROCS_MAX parameter" );
336
337	assert( (XCU_NB_HWI == 16) and
338	"XCU_NB_HWI must be 16" );
339
340	assert( (XCU_NB_PTI == 16) and
341	"XCU_NB_PTI must be 16" );
342
343	assert( (XCU_NB_WTI == 16) and
344	"XCU_NB_WTI must be 16" );
345
346	assert( (XCU_NB_OUT == NB_PROCS_MAX * IRQ_PER_PROCESSOR) and
347	"XCU_NB_OUT must be NB_PROCS_MAX * IRQ_PER_PROCESSOR" );
348
349	assert( (NB_CMA_CHANNELS <= 4) and
350	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
351
352	assert( (NB_TTY_CHANNELS <= 8) and
353	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
354
355	assert( (NB_NIC_CHANNELS <= 2) and
356	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
357
358	assert( (vci_address_width == 40) and
359	"VCI address width with the GIET must be 40 bits" );
360
361	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
362	"You must have X_WIDTH == Y_WIDTH == 4");
363
364	std::cout << std::endl;
365
366	std::cout << " - XMAX = " << XMAX << std::endl
367	<< " - YMAX = " << YMAX << std::endl
368	<< " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl
369	<< " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl
370	<< " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl
371	<< " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl
372	<< " - MEMC_WAYS = " << MEMC_WAYS << std::endl
373	<< " - MEMC_SETS = " << MEMC_SETS << std::endl
374	<< " - RAM_LATENCY = " << XRAM_LATENCY << std::endl
375	<< " - MAX_FROZEN = " << frozen_cycles << std::endl
376	<< " - MAX_CYCLES = " << ncycles << std::endl
377	<< " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl
378	<< " - SOFT_FILENAME = " << soft_name << std::endl
379	<< " - DISK_IMAGENAME = " << disk_name << std::endl
380	<< " - OPENMP THREADS = " << threads << std::endl
381	<< " - DEBUG_PROCID = " << trace_proc_id << std::endl
382	<< " - DEBUG_MEMCID = " << trace_memc_id << std::endl;
383
384	std::cout << std::endl;
385
386	// Internal and External VCI parameters definition
387	typedef soclib::caba::VciParams<vci_cell_width_int,
388	vci_plen_width,
389	vci_address_width,
390	vci_rerror_width,
391	vci_clen_width,
392	vci_rflag_width,
393	vci_srcid_width,
394	vci_pktid_width,
395	vci_trdid_width,
396	vci_wrplen_width> vci_param_int;
397
398	typedef soclib::caba::VciParams<vci_cell_width_ext,
399	vci_plen_width,
400	vci_address_width,
401	vci_rerror_width,
402	vci_clen_width,
403	vci_rflag_width,
404	vci_srcid_width,
405	vci_pktid_width,
406	vci_trdid_width,
407	vci_wrplen_width> vci_param_ext;
408
409	#if USE_OPENMP
410	omp_set_dynamic(false);
411	omp_set_num_threads(threads);
412	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
413	#endif
414
415
416	///////////////////////////////////////
417	// Direct Network Mapping Table
418	///////////////////////////////////////
419
420	MappingTable maptabd(vci_address_width,
421	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
422	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
423	0x00FF000000ULL);
424
425	// replicated segments
426	for (size_t x = 0; x < XMAX; x++)
427	{
428	for (size_t y = 0; y < (YMAX) ; y++)
429	{
430	sc_uint<vci_address_width> offset;
431	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
432
433	std::ostringstream si;
434	si << "seg_xicu_" << x << "_" << y;
435	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
436	IntTab(cluster(x,y),XICU_TGTID), false));
437
438	std::ostringstream sd;
439	sd << "seg_mcfg_" << x << "_" << y;
440	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
441	IntTab(cluster(x,y),MEMC_TGTID), false));
442
443	std::ostringstream sh;
444	sh << "seg_memc_" << x << "_" << y;
445	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
446	IntTab(cluster(x,y),MEMC_TGTID), true));
447	}
448	}
449
450	// segments for peripherals in cluster(0,0)
451	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
452	IntTab(cluster(0,0),MTTY_TGTID), false));
453
454	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
455	IntTab(cluster(0,0),DISK_TGTID), false));
456
457	// segments for peripherals in cluster_io (XMAX-1,YMAX)
458	sc_uint<vci_address_width> offset;
459	offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
460
461	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
462	IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
463
464	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
465	IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
466
467	maptabd.add(Segment("seg_disk", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
468	IntTab(cluster(XMAX-1, YMAX),DISK_TGTID), false));
469
470	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
471	IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
472
473	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
474	IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
475
476	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
477	IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
478
479	std::cout << maptabd << std::endl;
480
481	/////////////////////////////////////////////////
482	// Ram network mapping table
483	/////////////////////////////////////////////////
484
485	MappingTable maptabx(vci_address_width,
486	IntTab(X_WIDTH+Y_WIDTH),
487	IntTab(X_WIDTH+Y_WIDTH),
488	0x00FF000000ULL);
489
490	for (size_t x = 0; x < XMAX; x++)
491	{
492	for (size_t y = 0; y < (YMAX) ; y++)
493	{
494	sc_uint<vci_address_width> offset;
495	offset = (sc_uint<vci_address_width>)cluster(x,y)
496	<< (vci_address_width-X_WIDTH-Y_WIDTH);
497
498	std::ostringstream sh;
499	sh << "x_seg_memc_" << x << "_" << y;
500
501	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
502	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
503	}
504	}
505	std::cout << maptabx << std::endl;
506
507	////////////////////
508	// Signals
509	///////////////////
510
511	sc_clock signal_clk("clk");
512	sc_signal<bool> signal_resetn("resetn");
513
514	// IRQs from external peripherals
515	sc_signal<bool> signal_irq_disk;
516	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
517	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
518	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
519	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
520	sc_signal<bool> signal_irq_false;
521
522	// Horizontal inter-clusters DSPIN signals
523	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
524	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
525	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
526	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
527
528	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
529	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
530	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
531	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
532
533	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
534	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
535	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
536	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
537
538	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
539	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
540	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
541	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
542
543	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
544	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
545	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
546	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
547
548	// Vertical inter-clusters DSPIN signals
549	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
550	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
551	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
552	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
553
554	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
555	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
556	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
557	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
558
559	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
560	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
561	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
562	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
563
564	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
565	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
566	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
567	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
568
569	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
570	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
571	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
572	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
573
574	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
575	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
576	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
577	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
578	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
579
580	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
581	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
582	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
583	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
584
585	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
586	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
587	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
588	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
589
590	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
591	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
592	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
593	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
594
595	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
596	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
597	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
598	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
599
600	// VCI signals for iobus and peripherals
601	VciSignals<vci_param_int> signal_vci_ini_disk("signal_vci_ini_disk");
602	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
603	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
604
605	VciSignals<vci_param_int>* signal_vci_ini_proc =
606	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
607
608	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
609	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
610	VciSignals<vci_param_int> signal_vci_tgt_disk("signal_vci_tgt_disk");
611	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
612	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
613	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
614	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
615	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
616
617	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
618	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
619
620	////////////////////////////
621	// Loader
622	////////////////////////////
623
624	#if USE_IOC_RDK
625	std::ostringstream ramdisk_name;
626	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
627	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
628	#else
629	soclib::common::Loader loader( soft_name );
630	#endif
631
632	loader.memory_default(0x55);
633
634	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
635	proc_iss::set_loader( loader );
636
637	//////////////////////////////////////////////////////////////
638	// mesh construction: XMAX * YMAX clusters
639	//////////////////////////////////////////////////////////////
640
641	TsarLetiCluster<dspin_cmd_width,
642	dspin_rsp_width,
643	vci_param_int,
644	vci_param_ext>* clusters[XMAX][YMAX];
645
646	#if USE_OPENMP
647	#pragma omp parallel
648	{
649	#pragma omp for
650	#endif
651	for (size_t i = 0; i < (XMAX * YMAX); i++)
652	{
653	size_t x = i / (YMAX);
654	size_t y = i % (YMAX);
655
656	#if USE_OPENMP
657	#pragma omp critical
658	{
659	#endif
660	std::cout << std::endl;
661	std::cout << "Cluster_" << std::dec << x << "_" << y
662	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
663	std::cout << std::endl;
664
665	std::ostringstream cluster_name;
666	cluster_name << "cluster_" << std::dec << x << "_" << y;
667
668	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
669	dspin_rsp_width,
670	vci_param_int,
671	vci_param_ext>
672	(
673	cluster_name.str().c_str(),
674	NB_PROCS_MAX,
675	x,
676	y,
677	cluster(x,y),
678	maptabd,
679	maptabx,
680	RESET_ADDRESS,
681	X_WIDTH,
682	Y_WIDTH,
683	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
684	P_WIDTH,
685	MEMC_TGTID,
686	XICU_TGTID,
687	MTTY_TGTID,
688	DISK_TGTID,
689	(USE_IOC_RDK == 1),
690	disk_name,
691	MEMC_WAYS,
692	MEMC_SETS,
693	L1_IWAYS,
694	L1_ISETS,
695	L1_DWAYS,
696	L1_DSETS,
697	XRAM_LATENCY,
698	loader,
699	frozen_cycles,
700	trace_from,
701	trace_proc_ok,
702	trace_proc_id,
703	trace_memc_ok,
704	trace_memc_id
705	);
706
707	#if USE_OPENMP
708	} // end critical
709	#endif
710	} // end for
711	#if USE_OPENMP
712	}
713	#endif
714
715	#if USE_PIC
716
717	//////////////////////////////////////////////////////////////////
718	// IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
719	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
720	// - 3 local initiators : IOC, CMA, PIC
721	// There is no PROC, no MEMC and no XICU in this cluster,
722	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
723	// 8 targets, in order to use the same SRCID and TGTID space
724	// (same mapping table for the internal components,
725	// and for the external peripherals)
726	//////////////////////////////////////////////////////////////////
727
728	std::cout << std::endl;
729	std::cout << " Building IO cluster (external peripherals)" << std::endl;
730	std::cout << std::endl;
731
732	size_t cluster_io = cluster(XMAX-1, YMAX);
733
734	//////////// vci_local_crossbar
735	VciLocalCrossbar<vci_param_int>*
736	iobus = new VciLocalCrossbar<vci_param_int>(
737	"iobus",
738	maptabd, // mapping table
739	cluster_io, // cluster_xy
740	NB_PROCS_MAX + 3, // number of local initiators
741	8, // number of local targets
742	DISK_TGTID ); // default target index
743
744	//////////// vci_framebuffer
745	VciFrameBuffer<vci_param_int>*
746	fbuf = new VciFrameBuffer<vci_param_int>(
747	"fbuf",
748	IntTab(cluster_io, FBUF_TGTID),
749	maptabd,
750	FBUF_X_SIZE, FBUF_Y_SIZE );
751
752	#if ( USE_IOC_HBA )
753
754	//////////// vci_multi_ahci
755	std::vector<std::string> filenames;
756	filenames.push_back(disk_name); // one single disk
757	VciMultiAhci<vci_param_int>*
758	disk = new VciMultiAhci<vci_param_int>(
759	"disk",
760	maptabd,
761	IntTab(cluster_io, DISK_SRCID),
762	IntTab(cluster_io, DISK_TGTID),
763	filenames,
764	512, // block size
765	64, // burst size (bytes)
766	0 ); // disk latency
767
768	#elif ( USE_IOC_BDV or USE_IOC_SDC )
769
770	//////////// vci_block_device
771	VciBlockDeviceTsar<vci_param_int>*
772	disk = new VciBlockDeviceTsar<vci_param_int>(
773	"disk",
774	maptabd,
775	IntTab(cluster_io, DISK_SRCID),
776	IntTab(cluster_io, DISK_TGTID),
777	disk_name,
778	512, // block size
779	64, // burst size (bytes)
780	0 ); // disk latency
781	#endif
782
783	//////////// vci_multi_nic
784	VciMultiNic<vci_param_int>*
785	mnic = new VciMultiNic<vci_param_int>(
786	"mnic",
787	IntTab(cluster_io, MNIC_TGTID),
788	maptabd,
789	NB_NIC_CHANNELS,
790	0, // default MAC_4 address
791	0, // default MAC_2 address
792	1, // NIC_MODE_SYNTHESIS
793	12 ); // INTER_FRAME_GAP
794
795	///////////// vci_chbuf_dma
796	VciChbufDma<vci_param_int>*
797	cdma = new VciChbufDma<vci_param_int>(
798	"cdma",
799	maptabd,
800	IntTab(cluster_io, CDMA_SRCID),
801	IntTab(cluster_io, CDMA_TGTID),
802	64, // burst size
803	NB_CMA_CHANNELS,
804	4 ); // number of pipelined bursts
805
806	////////////// vci_multi_tty
807	std::vector<std::string> vect_names;
808	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
809	{
810	std::ostringstream term_name;
811	term_name << "ext_" << id;
812	vect_names.push_back(term_name.str().c_str());
813	}
814
815	VciMultiTty<vci_param_int>*
816	mtty = new VciMultiTty<vci_param_int>(
817	"mtty",
818	IntTab(cluster_io, MTTY_TGTID),
819	maptabd,
820	vect_names );
821
822	///////////// vci_iopic
823	VciIopic<vci_param_int>*
824	iopic = new VciIopic<vci_param_int>(
825	"iopic",
826	maptabd,
827	IntTab(cluster_io, IOPI_SRCID),
828	IntTab(cluster_io, IOPI_TGTID),
829	32 );
830
831	////////////// vci_dspin wrappers
832	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
833	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
834	"wt_iobus",
835	vci_srcid_width );
836
837	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
838	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
839	"wi_iobus",
840	vci_srcid_width );
841
842	///////////////////////////////////////////////////////////////
843	// IObus Net-list
844	///////////////////////////////////////////////////////////////
845
846	// iobus
847	iobus->p_clk (signal_clk);
848	iobus->p_resetn (signal_resetn);
849
850	iobus->p_target_to_up (signal_vci_cmd_from_noc);
851	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
852
853	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
854	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
855	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
856	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
857	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
858	iobus->p_to_target[DISK_TGTID] (signal_vci_tgt_disk);
859	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
860	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
861
862	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
863	{
864	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
865	}
866	iobus->p_to_initiator[DISK_SRCID] (signal_vci_ini_disk);
867	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
868	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
869
870	std::cout << " - IOBUS connected" << std::endl;
871
872	// disk
873	#if ( USE_IOC_HBA or USE_IOC_BDV or USE_IOC_SDC )
874	disk->p_clk (signal_clk);
875	disk->p_resetn (signal_resetn);
876	disk->p_vci_target (signal_vci_tgt_disk);
877	disk->p_vci_initiator (signal_vci_ini_disk);
878	#if USE_IOC_HBA
879	disk->p_channel_irq[0] (signal_irq_disk);
880	#else
881	disk->p_irq (signal_irq_disk);
882	#endif
883
884	std::cout << " - DISK connected" << std::endl;
885	#endif
886
887	// frame_buffer
888	fbuf->p_clk (signal_clk);
889	fbuf->p_resetn (signal_resetn);
890	fbuf->p_vci (signal_vci_tgt_fbuf);
891
892	std::cout << " - FBUF connected" << std::endl;
893
894	// multi_nic
895	mnic->p_clk (signal_clk);
896	mnic->p_resetn (signal_resetn);
897	mnic->p_vci (signal_vci_tgt_mnic);
898	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
899	{
900	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
901	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
902	}
903
904	std::cout << " - MNIC connected" << std::endl;
905
906	// chbuf_dma
907	cdma->p_clk (signal_clk);
908	cdma->p_resetn (signal_resetn);
909	cdma->p_vci_target (signal_vci_tgt_cdma);
910	cdma->p_vci_initiator (signal_vci_ini_cdma);
911	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
912	{
913	cdma->p_irq[i] (signal_irq_cdma[i]);
914	}
915
916	std::cout << " - CDMA connected" << std::endl;
917
918	// multi_tty
919	mtty->p_clk (signal_clk);
920	mtty->p_resetn (signal_resetn);
921	mtty->p_vci (signal_vci_tgt_mtty);
922	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
923	{
924	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
925	}
926
927	std::cout << " - MTTY connected" << std::endl;
928
929	// iopic
930	// NB_NIC_CHANNELS <= 2
931	// NB_CMA_CHANNELS <= 4
932	// NB_TTY_CHANNELS <= 16
933	iopic->p_clk (signal_clk);
934	iopic->p_resetn (signal_resetn);
935	iopic->p_vci_target (signal_vci_tgt_iopi);
936	iopic->p_vci_initiator (signal_vci_ini_iopi);
937	for ( size_t i=0 ; i<32 ; i++)
938	{
939	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
940	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
941	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
942	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
943	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
944	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
945	else if(i == 8) iopic->p_hwi[i] (signal_irq_disk);
946	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
947	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
948	else iopic->p_hwi[i] (signal_irq_false);
949	}
950
951	std::cout << " - IOPIC connected" << std::endl;
952
953	// vci/dspin wrappers
954	wi_iobus->p_clk (signal_clk);
955	wi_iobus->p_resetn (signal_resetn);
956	wi_iobus->p_vci (signal_vci_cmd_to_noc);
957	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
958	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
959
960	// vci/dspin wrappers
961	wt_iobus->p_clk (signal_clk);
962	wt_iobus->p_resetn (signal_resetn);
963	wt_iobus->p_vci (signal_vci_cmd_from_noc);
964	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
965	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
966
967	#endif // USE_PIC
968
969	// Clock & RESET for clusters
970	for (size_t x = 0; x < (XMAX); x++)
971	{
972	for (size_t y = 0; y < (YMAX); y++)
973	{
974	clusters[x][y]->p_clk (signal_clk);
975	clusters[x][y]->p_resetn (signal_resetn);
976	}
977	}
978
979	// Inter Clusters horizontal connections
980	if (XMAX > 1)
981	{
982	for (size_t x = 0; x < (XMAX-1); x++)
983	{
984	for (size_t y = 0; y < (YMAX); y++)
985	{
986	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
987	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
988	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
989	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
990
991	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
992	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
993	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
994	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
995
996	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
997	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
998	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
999	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
1000
1001	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
1002	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
1003	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
1004	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
1005
1006	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
1007	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
1008	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
1009	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
1010	}
1011	}
1012	}
1013	std::cout << std::endl << "Horizontal connections done" << std::endl;
1014
1015	// Inter Clusters vertical connections
1016	if (YMAX > 1)
1017	{
1018	for (size_t y = 0; y < (YMAX-1); y++)
1019	{
1020	for (size_t x = 0; x < XMAX; x++)
1021	{
1022	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
1023	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
1024	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
1025	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
1026
1027	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
1028	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
1029	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
1030	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
1031
1032	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
1033	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
1034	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
1035	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
1036
1037	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
1038	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
1039	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
1040	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
1041
1042	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
1043	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
1044	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
1045	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
1046	}
1047	}
1048	}
1049	std::cout << std::endl << "Vertical connections done" << std::endl;
1050
1051	// East & West boundary cluster connections
1052	for (size_t y = 0; y < (YMAX); y++)
1053	{
1054	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
1055	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
1056	clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
1057	clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
1058
1059	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
1060	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
1061	clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
1062	clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
1063
1064	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
1065	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
1066	clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
1067	clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
1068
1069	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
1070	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
1071	clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
1072	clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
1073
1074	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
1075	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
1076	clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
1077	clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
1078	}
1079
1080	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
1081
1082	// North & South boundary clusters connections
1083	for (size_t x = 0; x < XMAX; x++)
1084	{
1085	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
1086	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
1087	clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
1088	clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
1089
1090	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
1091	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
1092	clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
1093	clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
1094
1095	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
1096	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
1097	clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
1098	clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
1099
1100	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
1101	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
1102	clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
1103	clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
1104
1105	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
1106	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
1107	clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
1108	clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
1109	}
1110
1111	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
1112
1113	std::cout << std::endl;
1114
1115	////////////////////////////////////////////////////////
1116	// Simulation
1117	///////////////////////////////////////////////////////
1118
1119	sc_start(sc_core::sc_time(0, SC_NS));
1120	signal_resetn = false;
1121	signal_irq_false = false;
1122
1123	// set network boundaries signals default values
1124	// for all boundary clusters but the IO cluster
1125	for (size_t x = 0; x < XMAX ; x++)
1126	{
1127	for (size_t y = 0; y < YMAX ; y++)
1128	{
1129	for (size_t face = 0; face < 4; face++)
1130	{
1131	if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
1132	{
1133	signal_dspin_bound_cmd_in [x][y][face].write = false;
1134	signal_dspin_bound_cmd_in [x][y][face].read = true;
1135	signal_dspin_bound_cmd_out[x][y][face].write = false;
1136	signal_dspin_bound_cmd_out[x][y][face].read = true;
1137
1138	signal_dspin_bound_rsp_in [x][y][face].write = false;
1139	signal_dspin_bound_rsp_in [x][y][face].read = true;
1140	signal_dspin_bound_rsp_out[x][y][face].write = false;
1141	signal_dspin_bound_rsp_out[x][y][face].read = true;
1142	}
1143
1144	signal_dspin_bound_m2p_in [x][y][face].write = false;
1145	signal_dspin_bound_m2p_in [x][y][face].read = true;
1146	signal_dspin_bound_m2p_out[x][y][face].write = false;
1147	signal_dspin_bound_m2p_out[x][y][face].read = true;
1148
1149	signal_dspin_bound_p2m_in [x][y][face].write = false;
1150	signal_dspin_bound_p2m_in [x][y][face].read = true;
1151	signal_dspin_bound_p2m_out[x][y][face].write = false;
1152	signal_dspin_bound_p2m_out[x][y][face].read = true;
1153
1154	signal_dspin_bound_cla_in [x][y][face].write = false;
1155	signal_dspin_bound_cla_in [x][y][face].read = true;
1156	signal_dspin_bound_cla_out[x][y][face].write = false;
1157	signal_dspin_bound_cla_out[x][y][face].read = true;
1158	}
1159	}
1160	}
1161
1162	#if USE_PIC == 0
1163	signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
1164	signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
1165	signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
1166	signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
1167	#endif
1168
1169	// set default values for VCI signals connected to unused ports on iobus
1170	signal_vci_tgt_memc.rspval = false;
1171	signal_vci_tgt_xicu.rspval = false;
1172	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
1173
1174	sc_start(sc_core::sc_time(1, SC_NS));
1175	signal_resetn = true;
1176
1177	if (gettimeofday(&t1, NULL) != 0)
1178	{
1179	perror("gettimeofday");
1180	return EXIT_FAILURE;
1181	}
1182
1183	// simulation loop
1184	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
1185	{
1186	// Monitor a specific address for L1 cache
1187	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
1188
1189	// Monitor a specific address for L2 cache
1190	// clusters[0][0]->memc->cache_monitor( 0x0000201E00ULL );
1191
1192	// Monitor a specific address for one XRAM
1193	// clusters[0][0]->xram->start_monitor( 0x0000201E00ULL , 64);
1194
1195	// stats display
1196	if( (n % 5000000) == 0)
1197	{
1198
1199	if (gettimeofday(&t2, NULL) != 0)
1200	{
1201	perror("gettimeofday");
1202	return EXIT_FAILURE;
1203	}
1204
1205	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1206	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1207	std::cerr << "platform clock frequency "
1208	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
1209
1210	if (gettimeofday(&t1, NULL) != 0)
1211	{
1212	perror("gettimeofday");
1213	return EXIT_FAILURE;
1214	}
1215	}
1216
1217	// trace display
1218	if ( trace_ok and (n > trace_from) )
1219	{
1220	std::cout << "****************** cycle " << std::dec << n ;
1221	std::cout << " ********************************************" << std::endl;
1222
1223	size_t l = 0;
1224	size_t x = 0;
1225	size_t y = 0;
1226
1227	if ( trace_proc_ok )
1228	{
1229	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
1230	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
1231	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
1232
1233	std::ostringstream proc_signame;
1234	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1235	clusters[x][y]->proc[l]->print_trace(1);
1236	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
1237
1238	std::ostringstream xicu_signame;
1239	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
1240	clusters[x][y]->xicu->print_trace(0);
1241	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
1242
1243	if ( clusters[x][y]->signal_proc_irq[0] )
1244	std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
1245	if ( clusters[x][y]->signal_proc_irq[4] )
1246	std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
1247	if ( clusters[x][y]->signal_proc_irq[8] )
1248	std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
1249	if ( clusters[x][y]->signal_proc_irq[12] )
1250	std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
1251	}
1252
1253	if ( trace_memc_ok )
1254	{
1255	x = trace_memc_id >> Y_WIDTH;
1256	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
1257
1258	std::ostringstream smemc;
1259	smemc << "[SIG]MEMC_" << x << "_" << y;
1260	std::ostringstream sxram;
1261	sxram << "[SIG]XRAM_" << x << "_" << y;
1262
1263	clusters[x][y]->memc->print_trace();
1264	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1265	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1266	}
1267
1268	// trace coherence signals
1269	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
1270	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
1271	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
1272	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
1273
1274	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
1275	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
1276	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
1277	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
1278
1279	// trace xbar(s) m2p
1280	// clusters[0][0]->xbar_m2p->print_trace();
1281	// clusters[1][0]->xbar_m2p->print_trace();
1282	// clusters[0][1]->xbar_m2p->print_trace();
1283	// clusters[1][1]->xbar_m2p->print_trace();
1284
1285	// trace router(s) m2p
1286	// clusters[0][0]->router_m2p->print_trace();
1287	// clusters[1][0]->router_m2p->print_trace();
1288	// clusters[0][1]->router_m2p->print_trace();
1289	// clusters[1][1]->router_m2p->print_trace();
1290
1291	#if ( USE_IOC_HBA or USE_IOC_BDV or USE_IOC_SDC )
1292	#if USE_PIC
1293	// trace external ioc
1294	disk->print_trace();
1295	signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT");
1296	signal_vci_ini_disk.print_trace("[SIG]DISK_INI");
1297
1298	// trace external iopic
1299	iopic->print_trace();
1300	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
1301	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
1302
1303	// trace external interrupts
1304	if (signal_irq_disk) std::cout << "### IRQ_DISK" << std::endl;
1305	#else
1306	clusters[0][0]->disk->print_trace();
1307	clusters[0][0]->signal_vci_tgt_disk.print_trace("[SIG]DISK_0_0");
1308	clusters[0][0]->signal_vci_ini_disk.print_trace("[SIG]DISK_0_0");
1309	#endif
1310	#endif
1311
1312	} // end trace
1313
1314	sc_start(sc_core::sc_time(1, SC_NS));
1315	}
1316	// Free memory
1317	for (size_t i = 0 ; i < (XMAX * YMAX) ; i++)
1318	{
1319	size_t x = i / (YMAX);
1320	size_t y = i % (YMAX);
1321	delete clusters[x][y];
1322	}
1323
1324	return EXIT_SUCCESS;
1325	}
1326
1327	void handler(int dummy = 0)
1328	{
1329	stop_called = true;
1330	sc_stop();
1331	}
1332
1333	void voidhandler(int dummy = 0) {}
1334
1335	int sc_main (int argc, char *argv[])
1336	{
1337	signal(SIGINT, handler);
1338	signal(SIGPIPE, voidhandler);
1339
1340	try {
1341	return _main(argc, argv);
1342	} catch (std::exception &e) {
1343	std::cout << e.what() << std::endl;
1344	} catch (...) {
1345	std::cout << "Unknown exception occured" << std::endl;
1346	throw;
1347	}
1348	return 1;
1349	}
1350
1351
1352	// Local Variables:
1353	// tab-width: 3
1354	// c-basic-offset: 3
1355	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1356	// indent-tabs-mode: nil
1357	// End:
1358
1359	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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source: trunk/platforms/tsar_generic_leti/top.cpp @ 1060

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