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source: trunk/platforms/tsar_generic_leti/top.cpp @ 1010

Last change on this file since 1010 was 1004, checked in by bellefin, 9 years ago
Add the INTER_FRAME_GAP argument in the VciMultiNic? constructor and the “number of pipelined bursts” argument in the VciChainedBuffer? constructor.
File size: 56.0 KB

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1	/////////////////////////////////////////////////////////////////////////
2	// File: top.cpp (for tsar_generic_leti platform)
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : february 2013 / updated january 2015
6	// This program is released under the GNU public license
7	/////////////////////////////////////////////////////////////////////////
8	// This file define a generic TSAR architecture, fully compatible
9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
10	// in the framework of the SHARP project.
11	//
12	// The processor is a MIPS32 processor wrapped in a GDB server
13	// (this is defined in the tsar_leti_cluster).
14	//
15	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
16	// and the number of processors per cluster (NB_PROCS_MAX).
17	// The NB_PROCS_MAX parameter cannot be larger than 4.
18	// Others parameters are the frame buffer size, the disk controller type
19	// (BDV or HBA), the number of TTY channels, the number of NIC channels,
20	// and the number of CMA channels.
21	//
22	// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
23	// and are connected to an IO bus (implemented as a vci_local_crossbar):
24	// - DISK : block device controller (BDV / HBA)
25	// - MNIC : multi-channel ethernet controller
26	// - CDMA : multi-channel chained buffer dma controller
27	// - MTTY : multi-channel tty controller
28	// - FBUF : frame buffer controller
29	// - IOPI : HWI to SWI translator
30	//
31	// This IO bus is directly connected to the north ports of the CMD/RSP
32	// routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers.
33	// All other clusters in the upper row are empty: no processors,
34	// no ram, no routers.
35	// The X_SIZE parameter must be larger than 0, but no larger than 16.
36	// The Y_SIZE parameter must be larger than 1, but no larger than 16.
37	//
38	// We don't use an external ROM, as the boot code is (pre)loaded
39	// in RAM in cluster[0][0] at address 0x0.
40	//
41	// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
42	//
43	// The physical address space is 40 bits.
44	// The 8 address MSB bits define the cluster index.
45	//
46	// Besides the processors, each cluster contains:
47	// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
48	// - 1 vci_mem_cache
49	// - 1 vci_xicu
50	// - 1 vci_simple_ram (to emulate the L3 cache).
51	//
52	// Each processor receives 4 consecutive IRQ lines from the local XICU.
53	// The number of PTI and WTI IRQs is bounded to 16.
54	//
55	// In all clusters, the MEMC IRQ line (signaling a late write error)
56	// is connected to XICU HWI[8]
57	//
58	// For all external peripherals, the hardware interrupts (HWI) are
59	// translated to write interrupts (WTI) by the iopic component:
60	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
61	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
62	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
63	// - IOPIC HWI[8] connected to IRQ_DISK
64	// - IOPIC HWI[15:9] unused (grounded)
65	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
66	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
67	//
68	// The cluster internal architecture is defined in file tsar_leti_cluster,
69	// that must be considered as an extension of this top.cpp file.
70	////////////////////////////////////////////////////////////////////////////
71	// The following parameters must be defined in the hard_config.h file :
72	// - X_WIDTH : number of bits for x coordinate (must be 4)
73	// - Y_WIDTH : number of bits for y coordinate (must be 4)
74	// - P_WIDTH : number of bits for local processor coordinate
75	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
76	// - Y_SIZE : number of clusters in a column (1,2,4,8)
77	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
78	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
79	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
80	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
81	// - FBUF_X_SIZE : number of pixels per line for frame buffer
82	// - FBUF_Y_SIZE : number of lines for frame buffer
83	// - XCU_NB_HWI : number of XCU HWIs (must be 16)
84	// - XCU_NB_PTI : number of XCU PTIs (must be 16)
85	// - XCU_NB_WTI : number of XCU WTIs (must be 16)
86	// - XCU_NB_OUT : number of XCU output (must be 16)
87	// - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC / RDK)
88	//
89	// Some other hardware parameters are not used when compiling the OS,
90	// and are only defined in this top.cpp file:
91	// - XRAM_LATENCY : external ram latency
92	// - L1_IWAYS : L1 cache instruction number of ways
93	// - L1_ISETS : L1 cache instruction number of sets
94	// - L1_DWAYS : L1 cache data number of ways
95	// - L1_DSETS : L1 cache data number of sets
96	// - DISK_IMAGE_NAME : pathname for block device disk image
97	/////////////////////////////////////////////////////////////////////////
98	// General policy for 40 bits physical address decoding:
99	// All physical segments base addresses are multiple of 1 Mbytes
100	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
101	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
102	// the cluster index, and the LADR bits define the local index:
103	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
104	// \| 4 \| 4 \| 8 \| 24 \|
105	/////////////////////////////////////////////////////////////////////////
106	// General policy for 14 bits SRCID decoding:
107	// Each component is identified by (x_id, y_id, l_id) tuple.
108	// \|X_ID\|Y_ID\| L_ID \|
109	// \| 4 \| 4 \| 6 \|
110	/////////////////////////////////////////////////////////////////////////
111
112	#include <systemc>
113	#include <sys/time.h>
114	#include <iostream>
115	#include <sstream>
116	#include <cstdlib>
117	#include <cstdarg>
118	#include <stdint.h>
119
120	#include "gdbserver.h"
121	#include "mapping_table.h"
122
123	#include "tsar_leti_cluster.h"
124	#include "vci_local_crossbar.h"
125	#include "vci_dspin_initiator_wrapper.h"
126	#include "vci_dspin_target_wrapper.h"
127	#include "vci_multi_tty.h"
128	#include "vci_multi_nic.h"
129	#include "vci_chbuf_dma.h"
130	#include "vci_block_device_tsar.h"
131	#include "vci_multi_ahci.h"
132	#include "vci_framebuffer.h"
133	#include "vci_iopic.h"
134
135	#include "alloc_elems.h"
136
137	///////////////////////////////////////////////////
138	// Main hardware parameters values
139	///////////////////////////////////////////////////
140
141	#include "hard_config.h"
142
143	///////////////////////////////////////////////////////////////////////////////////////
144	// Secondary Hardware Parameters
145	///////////////////////////////////////////////////////////////////////////////////////
146
147	#define XMAX X_SIZE // actual number of columns in 2D mesh
148	#define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh
149
150	#define XRAM_LATENCY 0
151
152	#define MEMC_WAYS 16
153	#define MEMC_SETS 256
154
155	#define L1_IWAYS 4
156	#define L1_ISETS 64
157
158	#define L1_DWAYS 4
159	#define L1_DSETS 64
160
161	#define DISK_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg"
162
163	#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf"
164
165	#define NORTH 0
166	#define SOUTH 1
167	#define EAST 2
168	#define WEST 3
169
170	///////////////////////////////////////////////////
171	// Parallelisation
172	///////////////////////////////////////////////////
173
174	#define USE_OPENMP _OPENMP
175
176	#if USE_OPENMP
177	#include <omp.h>
178	#endif
179
180	///////////////////////////////////////////////////
181	// cluster index (from x,y coordinates)
182	///////////////////////////////////////////////////
183
184	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
185
186	///////////////////////////////////////////////////////////
187	// DSPIN parameters
188	///////////////////////////////////////////////////////////
189
190	#define dspin_cmd_width 39
191	#define dspin_rsp_width 32
192
193	///////////////////////////////////////////////////////////
194	// VCI parameters
195	///////////////////////////////////////////////////////////
196
197	#define vci_cell_width_int 4
198	#define vci_cell_width_ext 8
199	#define vci_address_width 40
200	#define vci_plen_width 8
201	#define vci_rerror_width 1
202	#define vci_clen_width 1
203	#define vci_rflag_width 1
204	#define vci_srcid_width 14
205	#define vci_pktid_width 4
206	#define vci_trdid_width 4
207	#define vci_wrplen_width 1
208
209
210
211	///////////////////////////////////////////////////////////////////////////////////////
212	// DEBUG Parameters default values
213	///////////////////////////////////////////////////////////////////////////////////////
214
215	#define MAX_FROZEN_CYCLES 500000
216
217	///////////////////////////////////////////////////////////////////////////////////////
218	// LOCAL TGTID & SRCID definition
219	// For all components: global TGTID = global SRCID = cluster_index
220	///////////////////////////////////////////////////////////////////////////////////////
221
222	#define MEMC_TGTID 0
223	#define XICU_TGTID 1
224	#define MTTY_TGTID 2
225	#define DISK_TGTID 3
226	#define FBUF_TGTID 4
227	#define MNIC_TGTID 5
228	#define CDMA_TGTID 6
229	#define IOPI_TGTID 7
230
231	#define DISK_SRCID NB_PROCS_MAX
232	#define CDMA_SRCID NB_PROCS_MAX + 1
233	#define IOPI_SRCID NB_PROCS_MAX + 2
234
235	bool stop_called = false;
236
237	/////////////////////////////////
238	int _main(int argc, char *argv[])
239	{
240	using namespace sc_core;
241	using namespace soclib::caba;
242	using namespace soclib::common;
243
244	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
245	size_t threads = 1; // simulator's threads number
246	bool trace_ok = false; // trace activated
247	uint32_t trace_from = 0; // trace start cycle
248	bool trace_proc_ok = false; // detailed proc trace activated
249	size_t trace_memc_ok = false; // detailed memc trace activated
250	size_t trace_memc_id = 0; // index of memc to be traced
251	size_t trace_proc_id = 0; // index of proc to be traced
252	char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code
253	char disk_name[256] = DISK_IMAGE_NAME; // pathname for DISK image
254	uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug
255	struct timeval t1,t2;
256	uint64_t ms1,ms2;
257
258	////////////// command line arguments //////////////////////
259	if (argc > 1)
260	{
261	for (int n = 1; n < argc; n = n + 2)
262	{
263	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
264	{
265	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
266	}
267	else if ((strcmp(argv[n],"-SOFT") == 0) && (n + 1 < argc))
268	{
269	strcpy(soft_name, argv[n + 1]);
270	}
271	else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc))
272	{
273	strcpy(disk_name, argv[n + 1]);
274	}
275	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
276	{
277	trace_ok = true;
278	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
279	}
280	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
281	{
282	trace_memc_ok = true;
283	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
284	size_t x = trace_memc_id >> Y_WIDTH;
285	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
286
287	assert( (x < XMAX) and (y < (YMAX)) and
288	"MEMCID parameter doesxn't fit valid XMAX/YMAX");
289	}
290	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
291	{
292	trace_proc_ok = true;
293	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
294	size_t cluster_xy = trace_proc_id >> P_WIDTH ;
295	size_t x = cluster_xy >> Y_WIDTH;
296	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
297	size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ;
298
299	assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
300	"PROCID parameter refers a not valid processor");
301	}
302	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
303	{
304	threads = (size_t) strtol(argv[n + 1], NULL, 0);
305	threads = (threads < 1) ? 1 : threads;
306	}
307	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
308	{
309	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
310	}
311	else
312	{
313	std::cout << " Arguments are (key,value) couples." << std::endl;
314	std::cout << " The order is not important." << std::endl;
315	std::cout << " Accepted arguments are :" << std::endl << std::endl;
316	std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;
317	std::cout << " - DEBUG debug_start_cycle" << std::endl;
318	std::cout << " - THREADS simulator's threads number" << std::endl;
319	std::cout << " - FROZEN max_number_of_lines" << std::endl;
320	std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;
321	std::cout << " - PROCID index_proc_to_be_traced" << std::endl;
322	exit(0);
323	}
324	}
325	}
326
327	// checking hardware parameters
328	assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
329	"Illegal X_SIZE parameter" );
330
331	assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
332	"Illegal Y_SIZE parameter" );
333
334	assert( (P_WIDTH <= 2) and
335	"P_WIDTH parameter cannot be larger than 2" );
336
337	assert( (NB_PROCS_MAX <= 4) and
338	"Illegal NB_PROCS_MAX parameter" );
339
340	assert( (XCU_NB_HWI == 16) and
341	"XCU_NB_HWI must be 16" );
342
343	assert( (XCU_NB_PTI == 16) and
344	"XCU_NB_PTI must be 16" );
345
346	assert( (XCU_NB_WTI == 16) and
347	"XCU_NB_WTI must be 16" );
348
349	assert( (XCU_NB_OUT == 16) and
350	"XCU_NB_OUT must be 16" );
351
352	assert( (NB_CMA_CHANNELS <= 4) and
353	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
354
355	assert( (NB_TTY_CHANNELS <= 8) and
356	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
357
358	assert( (NB_NIC_CHANNELS <= 2) and
359	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
360
361	assert( (vci_address_width == 40) and
362	"VCI address width with the GIET must be 40 bits" );
363
364	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
365	"You must have X_WIDTH == Y_WIDTH == 4");
366
367	std::cout << std::endl;
368
369	std::cout << " - XMAX = " << XMAX << std::endl
370	<< " - YMAX = " << YMAX << std::endl
371	<< " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl
372	<< " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl
373	<< " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl
374	<< " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl
375	<< " - MEMC_WAYS = " << MEMC_WAYS << std::endl
376	<< " - MEMC_SETS = " << MEMC_SETS << std::endl
377	<< " - RAM_LATENCY = " << XRAM_LATENCY << std::endl
378	<< " - MAX_FROZEN = " << frozen_cycles << std::endl
379	<< " - MAX_CYCLES = " << ncycles << std::endl
380	<< " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl
381	<< " - SOFT_FILENAME = " << soft_name << std::endl
382	<< " - DISK_IMAGENAME = " << disk_name << std::endl
383	<< " - OPENMP THREADS = " << threads << std::endl
384	<< " - DEBUG_PROCID = " << trace_proc_id << std::endl
385	<< " - DEBUG_MEMCID = " << trace_memc_id << std::endl;
386
387	std::cout << std::endl;
388
389	// Internal and External VCI parameters definition
390	typedef soclib::caba::VciParams<vci_cell_width_int,
391	vci_plen_width,
392	vci_address_width,
393	vci_rerror_width,
394	vci_clen_width,
395	vci_rflag_width,
396	vci_srcid_width,
397	vci_pktid_width,
398	vci_trdid_width,
399	vci_wrplen_width> vci_param_int;
400
401	typedef soclib::caba::VciParams<vci_cell_width_ext,
402	vci_plen_width,
403	vci_address_width,
404	vci_rerror_width,
405	vci_clen_width,
406	vci_rflag_width,
407	vci_srcid_width,
408	vci_pktid_width,
409	vci_trdid_width,
410	vci_wrplen_width> vci_param_ext;
411
412	#if USE_OPENMP
413	omp_set_dynamic(false);
414	omp_set_num_threads(threads);
415	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
416	#endif
417
418
419	///////////////////////////////////////
420	// Direct Network Mapping Table
421	///////////////////////////////////////
422
423	MappingTable maptabd(vci_address_width,
424	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
425	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
426	0x00FF000000ULL);
427
428	// replicated segments
429	for (size_t x = 0; x < XMAX; x++)
430	{
431	for (size_t y = 0; y < (YMAX) ; y++)
432	{
433	sc_uint<vci_address_width> offset;
434	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
435
436	std::ostringstream si;
437	si << "seg_xicu_" << x << "_" << y;
438	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
439	IntTab(cluster(x,y),XICU_TGTID), false));
440
441	std::ostringstream sd;
442	sd << "seg_mcfg_" << x << "_" << y;
443	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
444	IntTab(cluster(x,y),MEMC_TGTID), false));
445
446	std::ostringstream sh;
447	sh << "seg_memc_" << x << "_" << y;
448	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
449	IntTab(cluster(x,y),MEMC_TGTID), true));
450	}
451	}
452
453	// segments for peripherals in cluster(0,0)
454	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
455	IntTab(cluster(0,0),MTTY_TGTID), false));
456
457	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
458	IntTab(cluster(0,0),DISK_TGTID), false));
459
460	// segments for peripherals in cluster_io (XMAX-1,YMAX)
461	sc_uint<vci_address_width> offset;
462	offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
463
464	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
465	IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
466
467	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
468	IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
469
470	maptabd.add(Segment("seg_disk", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
471	IntTab(cluster(XMAX-1, YMAX),DISK_TGTID), false));
472
473	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
474	IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
475
476	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
477	IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
478
479	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
480	IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
481
482	std::cout << maptabd << std::endl;
483
484	/////////////////////////////////////////////////
485	// Ram network mapping table
486	/////////////////////////////////////////////////
487
488	MappingTable maptabx(vci_address_width,
489	IntTab(X_WIDTH+Y_WIDTH),
490	IntTab(X_WIDTH+Y_WIDTH),
491	0x00FF000000ULL);
492
493	for (size_t x = 0; x < XMAX; x++)
494	{
495	for (size_t y = 0; y < (YMAX) ; y++)
496	{
497	sc_uint<vci_address_width> offset;
498	offset = (sc_uint<vci_address_width>)cluster(x,y)
499	<< (vci_address_width-X_WIDTH-Y_WIDTH);
500
501	std::ostringstream sh;
502	sh << "x_seg_memc_" << x << "_" << y;
503
504	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
505	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
506	}
507	}
508	std::cout << maptabx << std::endl;
509
510	////////////////////
511	// Signals
512	///////////////////
513
514	sc_clock signal_clk("clk");
515	sc_signal<bool> signal_resetn("resetn");
516
517	// IRQs from external peripherals
518	sc_signal<bool> signal_irq_disk;
519	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
520	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
521	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
522	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
523	sc_signal<bool> signal_irq_false;
524
525	// Horizontal inter-clusters DSPIN signals
526	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
527	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
528	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
529	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
530
531	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
532	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
533	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
534	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
535
536	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
537	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
538	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
539	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
540
541	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
542	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
543	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
544	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
545
546	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
547	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
548	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
549	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
550
551	// Vertical inter-clusters DSPIN signals
552	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
553	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
554	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
555	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
556
557	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
558	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
559	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
560	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
561
562	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
563	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
564	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
565	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
566
567	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
568	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
569	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
570	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
571
572	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
573	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
574	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
575	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
576
577	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
578	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
579	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
580	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
581	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
582
583	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
584	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
585	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
586	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
587
588	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
589	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
590	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
591	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
592
593	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
594	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
595	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
596	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
597
598	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
599	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
600	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
601	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
602
603	// VCI signals for iobus and peripherals
604	VciSignals<vci_param_int> signal_vci_ini_disk("signal_vci_ini_disk");
605	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
606	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
607
608	VciSignals<vci_param_int>* signal_vci_ini_proc =
609	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
610
611	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
612	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
613	VciSignals<vci_param_int> signal_vci_tgt_disk("signal_vci_tgt_disk");
614	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
615	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
616	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
617	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
618	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
619
620	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
621	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
622
623	////////////////////////////
624	// Loader
625	////////////////////////////
626
627	#if USE_IOC_RDK
628	std::ostringstream ramdisk_name;
629	ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":";
630	soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() );
631	#else
632	soclib::common::Loader loader( soft_name );
633	#endif
634
635	loader.memory_default(0x55);
636
637	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
638	proc_iss::set_loader( loader );
639
640	//////////////////////////////////////////////////////////////
641	// mesh construction: XMAX * YMAX clusters
642	//////////////////////////////////////////////////////////////
643
644	TsarLetiCluster<dspin_cmd_width,
645	dspin_rsp_width,
646	vci_param_int,
647	vci_param_ext>* clusters[XMAX][YMAX];
648
649	#if USE_OPENMP
650	#pragma omp parallel
651	{
652	#pragma omp for
653	#endif
654	for (size_t i = 0; i < (XMAX * YMAX); i++)
655	{
656	size_t x = i / (YMAX);
657	size_t y = i % (YMAX);
658
659	#if USE_OPENMP
660	#pragma omp critical
661	{
662	#endif
663	std::cout << std::endl;
664	std::cout << "Cluster_" << std::dec << x << "_" << y
665	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
666	std::cout << std::endl;
667
668	std::ostringstream cluster_name;
669	cluster_name << "cluster_" << std::dec << x << "_" << y;
670
671	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
672	dspin_rsp_width,
673	vci_param_int,
674	vci_param_ext>
675	(
676	cluster_name.str().c_str(),
677	NB_PROCS_MAX,
678	x,
679	y,
680	cluster(x,y),
681	maptabd,
682	maptabx,
683	RESET_ADDRESS,
684	X_WIDTH,
685	Y_WIDTH,
686	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
687	P_WIDTH,
688	MEMC_TGTID,
689	XICU_TGTID,
690	MTTY_TGTID,
691	DISK_TGTID,
692	disk_name,
693	MEMC_WAYS,
694	MEMC_SETS,
695	L1_IWAYS,
696	L1_ISETS,
697	L1_DWAYS,
698	L1_DSETS,
699	XRAM_LATENCY,
700	loader,
701	frozen_cycles,
702	trace_from,
703	trace_proc_ok,
704	trace_proc_id,
705	trace_memc_ok,
706	trace_memc_id
707	);
708
709	#if USE_OPENMP
710	} // end critical
711	#endif
712	} // end for
713	#if USE_OPENMP
714	}
715	#endif
716
717	#if USE_PIC
718
719	//////////////////////////////////////////////////////////////////
720	// IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
721	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
722	// - 3 local initiators : IOC, CMA, PIC
723	// There is no PROC, no MEMC and no XICU in this cluster,
724	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
725	// 8 targets, in order to use the same SRCID and TGTID space
726	// (same mapping table for the internal components,
727	// and for the external peripherals)
728	//////////////////////////////////////////////////////////////////
729
730	std::cout << std::endl;
731	std::cout << " Building IO cluster (external peripherals)" << std::endl;
732	std::cout << std::endl;
733
734	size_t cluster_io = cluster(XMAX-1, YMAX);
735
736	//////////// vci_local_crossbar
737	VciLocalCrossbar<vci_param_int>*
738	iobus = new VciLocalCrossbar<vci_param_int>(
739	"iobus",
740	maptabd, // mapping table
741	cluster_io, // cluster_xy
742	NB_PROCS_MAX + 3, // number of local initiators
743	8, // number of local targets
744	DISK_TGTID ); // default target index
745
746	//////////// vci_framebuffer
747	VciFrameBuffer<vci_param_int>*
748	fbuf = new VciFrameBuffer<vci_param_int>(
749	"fbuf",
750	IntTab(cluster_io, FBUF_TGTID),
751	maptabd,
752	FBUF_X_SIZE, FBUF_Y_SIZE );
753
754	#if ( USE_IOC_HBA )
755
756	//////////// vci_multi_ahci
757	std::vector<std::string> filenames;
758	filenames.push_back(disk_name); // one single disk
759	VciMultiAhci<vci_param_int>*
760	disk = new VciMultiAhci<vci_param_int>(
761	"disk",
762	maptabd,
763	IntTab(cluster_io, DISK_SRCID),
764	IntTab(cluster_io, DISK_TGTID),
765	filenames,
766	512, // block size
767	64, // burst size (bytes)
768	0 ); // disk latency
769
770	#elif ( USE_IOC_BDV or USE_IOC_SDC )
771
772	//////////// vci_block_device
773	VciBlockDeviceTsar<vci_param_int>*
774	disk = new VciBlockDeviceTsar<vci_param_int>(
775	"disk",
776	maptabd,
777	IntTab(cluster_io, DISK_SRCID),
778	IntTab(cluster_io, DISK_TGTID),
779	disk_name,
780	512, // block size
781	64, // burst size (bytes)
782	0 ); // disk latency
783	#endif
784
785	//////////// vci_multi_nic
786	VciMultiNic<vci_param_int>*
787	mnic = new VciMultiNic<vci_param_int>(
788	"mnic",
789	IntTab(cluster_io, MNIC_TGTID),
790	maptabd,
791	NB_NIC_CHANNELS,
792	0, // default MAC_4 address
793	0, // default MAC_2 address
794	1, // NIC_MODE_SYNTHESIS
795	12 ); // INTER_FRAME_GAP
796
797	///////////// vci_chbuf_dma
798	VciChbufDma<vci_param_int>*
799	cdma = new VciChbufDma<vci_param_int>(
800	"cdma",
801	maptabd,
802	IntTab(cluster_io, CDMA_SRCID),
803	IntTab(cluster_io, CDMA_TGTID),
804	64, // burst size
805	NB_CMA_CHANNELS,
806	4 ); // number of pipelined bursts
807
808	////////////// vci_multi_tty
809	std::vector<std::string> vect_names;
810	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
811	{
812	std::ostringstream term_name;
813	term_name << "ext_" << id;
814	vect_names.push_back(term_name.str().c_str());
815	}
816
817	VciMultiTty<vci_param_int>*
818	mtty = new VciMultiTty<vci_param_int>(
819	"mtty",
820	IntTab(cluster_io, MTTY_TGTID),
821	maptabd,
822	vect_names );
823
824	///////////// vci_iopic
825	VciIopic<vci_param_int>*
826	iopic = new VciIopic<vci_param_int>(
827	"iopic",
828	maptabd,
829	IntTab(cluster_io, IOPI_SRCID),
830	IntTab(cluster_io, IOPI_TGTID),
831	32 );
832
833	////////////// vci_dspin wrappers
834	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
835	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
836	"wt_iobus",
837	vci_srcid_width );
838
839	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
840	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
841	"wi_iobus",
842	vci_srcid_width );
843
844	///////////////////////////////////////////////////////////////
845	// IObus Net-list
846	///////////////////////////////////////////////////////////////
847
848	// iobus
849	iobus->p_clk (signal_clk);
850	iobus->p_resetn (signal_resetn);
851
852	iobus->p_target_to_up (signal_vci_cmd_from_noc);
853	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
854
855	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
856	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
857	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
858	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
859	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
860	iobus->p_to_target[DISK_TGTID] (signal_vci_tgt_disk);
861	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
862	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
863
864	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
865	{
866	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
867	}
868	iobus->p_to_initiator[DISK_SRCID] (signal_vci_ini_disk);
869	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
870	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
871
872	std::cout << " - IOBUS connected" << std::endl;
873
874	// disk
875	disk->p_clk (signal_clk);
876	disk->p_resetn (signal_resetn);
877	disk->p_vci_target (signal_vci_tgt_disk);
878	disk->p_vci_initiator (signal_vci_ini_disk);
879	#if USE_IOC_HBA
880	disk->p_channel_irq[0] (signal_irq_disk);
881	#else
882	disk->p_irq (signal_irq_disk);
883	#endif
884
885	std::cout << " - DISK connected" << std::endl;
886
887	// frame_buffer
888	fbuf->p_clk (signal_clk);
889	fbuf->p_resetn (signal_resetn);
890	fbuf->p_vci (signal_vci_tgt_fbuf);
891
892	std::cout << " - FBUF connected" << std::endl;
893
894	// multi_nic
895	mnic->p_clk (signal_clk);
896	mnic->p_resetn (signal_resetn);
897	mnic->p_vci (signal_vci_tgt_mnic);
898	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
899	{
900	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
901	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
902	}
903
904	std::cout << " - MNIC connected" << std::endl;
905
906	// chbuf_dma
907	cdma->p_clk (signal_clk);
908	cdma->p_resetn (signal_resetn);
909	cdma->p_vci_target (signal_vci_tgt_cdma);
910	cdma->p_vci_initiator (signal_vci_ini_cdma);
911	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
912	{
913	cdma->p_irq[i] (signal_irq_cdma[i]);
914	}
915
916	std::cout << " - CDMA connected" << std::endl;
917
918	// multi_tty
919	mtty->p_clk (signal_clk);
920	mtty->p_resetn (signal_resetn);
921	mtty->p_vci (signal_vci_tgt_mtty);
922	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
923	{
924	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
925	}
926
927	std::cout << " - MTTY connected" << std::endl;
928
929	// iopic
930	// NB_NIC_CHANNELS <= 2
931	// NB_CMA_CHANNELS <= 4
932	// NB_TTY_CHANNELS <= 16
933	iopic->p_clk (signal_clk);
934	iopic->p_resetn (signal_resetn);
935	iopic->p_vci_target (signal_vci_tgt_iopi);
936	iopic->p_vci_initiator (signal_vci_ini_iopi);
937	for ( size_t i=0 ; i<32 ; i++)
938	{
939	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
940	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
941	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
942	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
943	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
944	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
945	else if(i == 8) iopic->p_hwi[i] (signal_irq_disk);
946	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
947	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
948	else iopic->p_hwi[i] (signal_irq_false);
949	}
950
951	std::cout << " - IOPIC connected" << std::endl;
952
953	// vci/dspin wrappers
954	wi_iobus->p_clk (signal_clk);
955	wi_iobus->p_resetn (signal_resetn);
956	wi_iobus->p_vci (signal_vci_cmd_to_noc);
957	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
958	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
959
960	// vci/dspin wrappers
961	wt_iobus->p_clk (signal_clk);
962	wt_iobus->p_resetn (signal_resetn);
963	wt_iobus->p_vci (signal_vci_cmd_from_noc);
964	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
965	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
966
967	#endif // USE_PIC
968
969	// Clock & RESET for clusters
970	for (size_t x = 0; x < (XMAX); x++)
971	{
972	for (size_t y = 0; y < (YMAX); y++)
973	{
974	clusters[x][y]->p_clk (signal_clk);
975	clusters[x][y]->p_resetn (signal_resetn);
976	}
977	}
978
979	// Inter Clusters horizontal connections
980	if (XMAX > 1)
981	{
982	for (size_t x = 0; x < (XMAX-1); x++)
983	{
984	for (size_t y = 0; y < (YMAX); y++)
985	{
986	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
987	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
988	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
989	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
990
991	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
992	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
993	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
994	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
995
996	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
997	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
998	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
999	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
1000
1001	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
1002	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
1003	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
1004	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
1005
1006	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
1007	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
1008	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
1009	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
1010	}
1011	}
1012	}
1013	std::cout << std::endl << "Horizontal connections done" << std::endl;
1014
1015	// Inter Clusters vertical connections
1016	if (YMAX > 1)
1017	{
1018	for (size_t y = 0; y < (YMAX-1); y++)
1019	{
1020	for (size_t x = 0; x < XMAX; x++)
1021	{
1022	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
1023	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
1024	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
1025	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
1026
1027	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
1028	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
1029	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
1030	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
1031
1032	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
1033	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
1034	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
1035	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
1036
1037	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
1038	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
1039	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
1040	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
1041
1042	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
1043	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
1044	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
1045	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
1046	}
1047	}
1048	}
1049	std::cout << std::endl << "Vertical connections done" << std::endl;
1050
1051	// East & West boundary cluster connections
1052	for (size_t y = 0; y < (YMAX); y++)
1053	{
1054	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
1055	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
1056	clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
1057	clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
1058
1059	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
1060	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
1061	clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
1062	clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
1063
1064	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
1065	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
1066	clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
1067	clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
1068
1069	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
1070	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
1071	clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
1072	clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
1073
1074	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
1075	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
1076	clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
1077	clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
1078	}
1079
1080	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
1081
1082	// North & South boundary clusters connections
1083	for (size_t x = 0; x < XMAX; x++)
1084	{
1085	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
1086	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
1087	clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
1088	clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
1089
1090	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
1091	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
1092	clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
1093	clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
1094
1095	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
1096	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
1097	clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
1098	clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
1099
1100	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
1101	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
1102	clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
1103	clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
1104
1105	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
1106	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
1107	clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
1108	clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
1109	}
1110
1111	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
1112
1113	std::cout << std::endl;
1114
1115	////////////////////////////////////////////////////////
1116	// Simulation
1117	///////////////////////////////////////////////////////
1118
1119	sc_start(sc_core::sc_time(0, SC_NS));
1120	signal_resetn = false;
1121	signal_irq_false = false;
1122
1123	// set network boundaries signals default values
1124	// for all boundary clusters but the IO cluster
1125	for (size_t x = 0; x < XMAX ; x++)
1126	{
1127	for (size_t y = 0; y < YMAX ; y++)
1128	{
1129	for (size_t face = 0; face < 4; face++)
1130	{
1131	if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
1132	{
1133	signal_dspin_bound_cmd_in [x][y][face].write = false;
1134	signal_dspin_bound_cmd_in [x][y][face].read = true;
1135	signal_dspin_bound_cmd_out[x][y][face].write = false;
1136	signal_dspin_bound_cmd_out[x][y][face].read = true;
1137
1138	signal_dspin_bound_rsp_in [x][y][face].write = false;
1139	signal_dspin_bound_rsp_in [x][y][face].read = true;
1140	signal_dspin_bound_rsp_out[x][y][face].write = false;
1141	signal_dspin_bound_rsp_out[x][y][face].read = true;
1142	}
1143
1144	signal_dspin_bound_m2p_in [x][y][face].write = false;
1145	signal_dspin_bound_m2p_in [x][y][face].read = true;
1146	signal_dspin_bound_m2p_out[x][y][face].write = false;
1147	signal_dspin_bound_m2p_out[x][y][face].read = true;
1148
1149	signal_dspin_bound_p2m_in [x][y][face].write = false;
1150	signal_dspin_bound_p2m_in [x][y][face].read = true;
1151	signal_dspin_bound_p2m_out[x][y][face].write = false;
1152	signal_dspin_bound_p2m_out[x][y][face].read = true;
1153
1154	signal_dspin_bound_cla_in [x][y][face].write = false;
1155	signal_dspin_bound_cla_in [x][y][face].read = true;
1156	signal_dspin_bound_cla_out[x][y][face].write = false;
1157	signal_dspin_bound_cla_out[x][y][face].read = true;
1158	}
1159	}
1160	}
1161
1162	#if USE_PIC == 0
1163	signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
1164	signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
1165	signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
1166	signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
1167	#endif
1168
1169	// set default values for VCI signals connected to unused ports on iobus
1170	signal_vci_tgt_memc.rspval = false;
1171	signal_vci_tgt_xicu.rspval = false;
1172	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
1173
1174	sc_start(sc_core::sc_time(1, SC_NS));
1175	signal_resetn = true;
1176
1177	if (gettimeofday(&t1, NULL) != 0)
1178	{
1179	perror("gettimeofday");
1180	return EXIT_FAILURE;
1181	}
1182
1183	// simulation loop
1184	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
1185	{
1186	// Monitor a specific address for L1 cache
1187	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
1188
1189	// Monitor a specific address for L2 cache
1190	// clusters[0][0]->memc->cache_monitor( 0x0000201E00ULL );
1191
1192	// Monitor a specific address for one XRAM
1193	// clusters[0][0]->xram->start_monitor( 0x0000201E00ULL , 64);
1194
1195	// stats display
1196	if( (n % 5000000) == 0)
1197	{
1198
1199	if (gettimeofday(&t2, NULL) != 0)
1200	{
1201	perror("gettimeofday");
1202	return EXIT_FAILURE;
1203	}
1204
1205	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1206	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1207	std::cerr << "platform clock frequency "
1208	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
1209
1210	if (gettimeofday(&t1, NULL) != 0)
1211	{
1212	perror("gettimeofday");
1213	return EXIT_FAILURE;
1214	}
1215	}
1216
1217	// trace display
1218	if ( trace_ok and (n > trace_from) )
1219	{
1220	std::cout << "****************** cycle " << std::dec << n ;
1221	std::cout << " ********************************************" << std::endl;
1222
1223	size_t l = 0;
1224	size_t x = 0;
1225	size_t y = 0;
1226
1227	if ( trace_proc_ok )
1228	{
1229	l = trace_proc_id & ((1<<P_WIDTH)-1) ;
1230	x = (trace_proc_id >> P_WIDTH) >> Y_WIDTH ;
1231	y = (trace_proc_id >> P_WIDTH) & ((1<<Y_WIDTH) - 1);
1232
1233	std::ostringstream proc_signame;
1234	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1235	clusters[x][y]->proc[l]->print_trace(1);
1236	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
1237
1238	std::ostringstream xicu_signame;
1239	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
1240	clusters[x][y]->xicu->print_trace(0);
1241	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
1242
1243	if ( clusters[x][y]->signal_proc_irq[0] )
1244	std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
1245	if ( clusters[x][y]->signal_proc_irq[4] )
1246	std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
1247	if ( clusters[x][y]->signal_proc_irq[8] )
1248	std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
1249	if ( clusters[x][y]->signal_proc_irq[12] )
1250	std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
1251	}
1252
1253	if ( trace_memc_ok )
1254	{
1255	x = trace_memc_id >> Y_WIDTH;
1256	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
1257
1258	std::ostringstream smemc;
1259	smemc << "[SIG]MEMC_" << x << "_" << y;
1260	std::ostringstream sxram;
1261	sxram << "[SIG]XRAM_" << x << "_" << y;
1262
1263	clusters[x][y]->memc->print_trace();
1264	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1265	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1266	}
1267
1268	// trace coherence signals
1269	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
1270	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
1271	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
1272	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
1273
1274	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
1275	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
1276	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
1277	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
1278
1279	// trace xbar(s) m2p
1280	// clusters[0][0]->xbar_m2p->print_trace();
1281	// clusters[1][0]->xbar_m2p->print_trace();
1282	// clusters[0][1]->xbar_m2p->print_trace();
1283	// clusters[1][1]->xbar_m2p->print_trace();
1284
1285	// trace router(s) m2p
1286	// clusters[0][0]->router_m2p->print_trace();
1287	// clusters[1][0]->router_m2p->print_trace();
1288	// clusters[0][1]->router_m2p->print_trace();
1289	// clusters[1][1]->router_m2p->print_trace();
1290
1291	#if USE_PIC
1292	// trace external ioc
1293	disk->print_trace();
1294	signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT");
1295	signal_vci_ini_disk.print_trace("[SIG]DISK_INI");
1296
1297	// trace external iopic
1298	iopic->print_trace();
1299	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
1300	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
1301
1302	// trace external interrupts
1303	if (signal_irq_disk) std::cout << "### IRQ_DISK" << std::endl;
1304	#else
1305	clusters[0][0]->disk->print_trace();
1306	clusters[0][0]->signal_vci_tgt_disk.print_trace("[SIG]DISK_0_0");
1307	clusters[0][0]->signal_vci_ini_disk.print_trace("[SIG]DISK_0_0");
1308	#endif
1309
1310	} // end trace
1311
1312	sc_start(sc_core::sc_time(1, SC_NS));
1313	}
1314	// Free memory
1315	for (size_t i = 0 ; i < (XMAX * YMAX) ; i++)
1316	{
1317	size_t x = i / (YMAX);
1318	size_t y = i % (YMAX);
1319	delete clusters[x][y];
1320	}
1321
1322	return EXIT_SUCCESS;
1323	}
1324
1325	void handler(int dummy = 0)
1326	{
1327	stop_called = true;
1328	sc_stop();
1329	}
1330
1331	void voidhandler(int dummy = 0) {}
1332
1333	int sc_main (int argc, char *argv[])
1334	{
1335	signal(SIGINT, handler);
1336	signal(SIGPIPE, voidhandler);
1337
1338	try {
1339	return _main(argc, argv);
1340	} catch (std::exception &e) {
1341	std::cout << e.what() << std::endl;
1342	} catch (...) {
1343	std::cout << "Unknown exception occured" << std::endl;
1344	throw;
1345	}
1346	return 1;
1347	}
1348
1349
1350	// Local Variables:
1351	// tab-width: 3
1352	// c-basic-offset: 3
1353	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1354	// indent-tabs-mode: nil
1355	// End:
1356
1357	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
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