source: trunk/platforms/tsar_generic_leti/top.cpp@ 720

Last change on this file since 720 was 708, checked in by cfuguet, 12 years ago

tsar_generic_leti:

  • Minor modification in platform: Initializing memory to 0xAA to emulate real behavior of memory which generally is not initialized to 0. This allows to detect problems with uninitialized structures in OSes.


File size: 58.8 KB
Line 
1/////////////////////////////////////////////////////////////////////////
2// File: top.cpp (for tsar_generic_leti)
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : february 2014
6// This program is released under the GNU public license
7/////////////////////////////////////////////////////////////////////////
8// This file define a generic TSAR architecture, fully compatible
9// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
10// in the framework of the SHARP project.
11//
12// The processor is a MIPS32 processor wrapped in a GDB server
13// (this is defined in the tsar_xbar_cluster).
14//
15// It does not use an external ROM, as the boot code is (pre)loaded
16// in cluster (0,0) memory at address 0x0.
17//
18// The physical address space is 40 bits.
19// The 8 address MSB bits define the cluster index.
20//
21// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
22// and the number of processors per cluster (NB_PROCS_MAX).
23// The number of clusters cannot be larger than 128.
24// The number of processors per cluster cannot be larger than 4.
25//
26// Each cluster contains:
27// - 5 dspin_local_crossbar (local interconnect)
28// - 5 dspin_router (global interconnect)
29// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
30// - 1 vci_mem_cache
31// - 1 vci_xicu
32// - 1 vci_simple_ram (to model the L3 cache).
33//
34// Each processor receives 4 consecutive IRQ lines from the local XICU.
35//
36// In all clusters, the MEMC IRQ line (signaling a late write error)
37// is connected to XICU HWI[8]
38// The cluster (0,0) contains two "backup" peripherals:
39// - one block device controller, whose IRQ is connected to XICU HWI[9].
40// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
41//
42// The cluster internal architecture is defined in file tsar_leti_cluster,
43// that must be considered as an extension of this top.cpp file.
44//
45// Besides the hardware components in clusters, "external" peripherals
46// are connected to an external IO bus (implemented as a vci_local_crossbar):
47// - one disk controller
48// - one multi-channel ethernet controller
49// - one multi-channel chained buffer dma controller
50// - one multi-channel tty controller
51// - one frame buffer controller
52// - one 32 channels iopic controller
53//
54// This IOBUS is connected to the north port of the DIR_CMD
55// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
56// For all external peripherals, the hardware interrupts (HWI) are
57// translated to write interrupts (WTI) by the iopic component:
58// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
59// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
60// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
61// - IOPIC HWI[8] connected to IRQ_BDEV
62// - IOPIC HWI[15:9] unused (grounded)
63// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
64// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
65////////////////////////////////////////////////////////////////////////////
66// The following parameters must be defined in the hard_config.h file :
67// - X_WIDTH : number of bits for x coordinate (must be 4)
68// - Y_WIDTH : number of bits for y coordinate (must be 4)
69// - X_SIZE : number of clusters in a row (1,2,4,8,16)
70// - Y_SIZE : number of clusters in a column (1,2,4,8)
71// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
72// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
73// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
74// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
75//
76// Some other hardware parameters are not used when compiling the OS,
77// and are only defined in this top.cpp file:
78// - XRAM_LATENCY : external ram latency
79// - MEMC_WAYS : L2 cache number of ways
80// - MEMC_SETS : L2 cache number of sets
81// - L1_IWAYS : L1 cache instruction number of ways
82// - L1_ISETS : L1 cache instruction number of sets
83// - L1_DWAYS : L1 cache data number of ways
84// - L1_DSETS : L1 cache data number of sets
85// - FBUF_X_SIZE : width of frame buffer (pixels)
86// - FBUF_Y_SIZE : heigth of frame buffer (lines)
87// - BDEV_IMAGE_NAME : file pathname for block device
88// - NIC_RX_NAME : file pathname for NIC received packets
89// - NIC_TX_NAME : file pathname for NIC transmited packets
90// - NIC_MAC4 : MAC address
91// - NIC_MAC2 : MAC address
92/////////////////////////////////////////////////////////////////////////
93// General policy for 40 bits physical address decoding:
94// All physical segments base addresses are multiple of 1 Mbytes
95// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
96// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
97// the cluster index, and the LADR bits define the local index:
98// |X_ID|Y_ID| LADR | OFFSET |
99// | 4 | 4 | 8 | 24 |
100/////////////////////////////////////////////////////////////////////////
101// General policy for 14 bits SRCID decoding:
102// Each component is identified by (x_id, y_id, l_id) tuple.
103// |X_ID|Y_ID| L_ID |
104// | 4 | 4 | 6 |
105/////////////////////////////////////////////////////////////////////////
106
107#include <systemc>
108#include <sys/time.h>
109#include <iostream>
110#include <sstream>
111#include <cstdlib>
112#include <cstdarg>
113#include <stdint.h>
114
115#include "gdbserver.h"
116#include "mapping_table.h"
117#include "tsar_leti_cluster.h"
118#include "vci_local_crossbar.h"
119#include "vci_dspin_initiator_wrapper.h"
120#include "vci_dspin_target_wrapper.h"
121#include "vci_multi_tty.h"
122#include "vci_multi_nic.h"
123#include "vci_chbuf_dma.h"
124#include "vci_block_device_tsar.h"
125#include "vci_framebuffer.h"
126#include "vci_iopic.h"
127#include "alloc_elems.h"
128
129//////////////////////////////////////////////////////////////////////////////////////////
130// Parameters depending on the OS and software application
131// - path to hard_config file
132// - path to binary code for the RAM loader
133// - path to disk image for RAMDISK loader
134// - path to disk image for IOC device
135//////////////////////////////////////////////////////////////////////////////////////////
136
137#define USE_GIET_VM 1
138#define USE_GIET_TSAR 0
139
140#if ( USE_GIET_VM and USE_GIET_TSAR )
141#error "Can't use Two different OS"
142#endif
143
144#if ( (not USE_GIET_VM) and (not USE_GIET_TSAR) )
145#error "You need to specify one OS"
146#endif
147
148#if USE_GIET_TSAR
149#include "hard_config.h"
150#define BINARY_PATH_FOR_LOADER "../../softs/soft_transpose_giet/bin.soft"
151#define DISK_IMAGE_PATH_FOR_IOC "../../softs/soft_transpose_giet/images.raw"
152#define RAMDISK_PATH_FOR_LOADER DISK_IMAGE_PATH_FOR_IOC "@0x00800000:"
153#endif
154
155#if USE_GIET_VM
156#include "hard_config.h"
157#define BINARY_PATH_FOR_LOADER "../../softs/tsar_boot/preloader.elf"
158#define DISK_IMAGE_PATH_FOR_IOC "../../../giet_vm/hdd/virt_hdd.dmg"
159#define RAMDISK_PATH_FOR_LOADER DISK_IMAGE_PATH_FOR_IOC "@0x02000000:"
160#endif
161
162///////////////////////////////////////////////////
163// Parallelisation
164///////////////////////////////////////////////////
165#define USE_OPENMP _OPENMP
166
167#if USE_OPENMP
168#include <omp.h>
169#endif
170
171///////////////////////////////////////////////////
172// cluster index (from x,y coordinates)
173///////////////////////////////////////////////////
174
175#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
176
177///////////////////////////////////////////////////////////
178// DSPIN parameters
179///////////////////////////////////////////////////////////
180
181#define dspin_cmd_width 39
182#define dspin_rsp_width 32
183
184///////////////////////////////////////////////////////////
185// VCI parameters
186///////////////////////////////////////////////////////////
187
188#define vci_cell_width_int 4
189#define vci_cell_width_ext 8
190#define vci_address_width 40
191#define vci_plen_width 8
192#define vci_rerror_width 1
193#define vci_clen_width 1
194#define vci_rflag_width 1
195#define vci_srcid_width 14
196#define vci_pktid_width 4
197#define vci_trdid_width 4
198#define vci_wrplen_width 1
199
200
201/////////////////////////////////////////////////////////////////////////////////////////
202// Secondary Hardware Parameters
203/////////////////////////////////////////////////////////////////////////////////////////
204
205#define RESET_ADDRESS 0x0
206
207#define MAX_TTY_CHANNELS 8
208#define MAX_CMA_CHANNELS 4
209#define MAX_NIC_CHANNELS 2
210
211#define XRAM_LATENCY 0
212#define XRAM_SIZE 0x04000000 // 64 Mbytes per cluster
213
214#define MEMC_WAYS 16
215#define MEMC_SETS 256
216
217#define L1_IWAYS 4
218#define L1_ISETS 64
219
220#define L1_DWAYS 4
221#define L1_DSETS 64
222
223#define FBUF_X_SIZE 128
224#define FBUF_Y_SIZE 128
225
226#define NIC_MAC4 0XBABEF00D
227#define NIC_MAC2 0xBEEF
228#define NIC_RX_NAME "/dev/null"
229#define NIC_TX_NAME "/dev/null"
230
231#define NORTH 0
232#define SOUTH 1
233#define EAST 2
234#define WEST 3
235
236///////////////////////////////////////////////////////////////////////////////////////
237// DEBUG Parameters default values
238///////////////////////////////////////////////////////////////////////////////////////
239
240#define MAX_FROZEN_CYCLES 500000
241
242///////////////////////////////////////////////////////////////////////////////////////
243// LOCAL TGTID & SRCID definition
244// For all components: global TGTID = global SRCID = cluster_index
245///////////////////////////////////////////////////////////////////////////////////////
246
247#define MEMC_TGTID 0
248#define XICU_TGTID 1
249#define MTTY_TGTID 2
250#define BDEV_TGTID 3
251#define FBUF_TGTID 4
252#define MNIC_TGTID 5
253#define CDMA_TGTID 6
254#define IOPI_TGTID 7
255
256#define BDEV_SRCID NB_PROCS_MAX
257#define CDMA_SRCID NB_PROCS_MAX + 1
258#define IOPI_SRCID NB_PROCS_MAX + 2
259
260//////////////////////////////////////////////////////////////////////////////////////
261// Physical segments definition
262//////////////////////////////////////////////////////////////////////////////////////
263// - 3 segments are replicated in all clusters
264// - 2 segments are only in cluster[0,0]
265// - 4 segments are only in cluster [X_SIZE-1,Y_SIZE]
266// The following values are for segments in cluster 0,
267// and these 32 bits values must be concatenate with the cluster
268// index (on 8 bits) to obtain the 40 bits address.
269//////////////////////////////////////////////////////////////////////////////////////
270
271// in cluster [0,0] & [X_SIZE-1,Y_SIZE]
272
273#define MTTY_BASE 0xF4000000
274#define MTTY_SIZE 0x00001000 // 4 Kbytes
275
276#define BDEV_BASE 0xF2000000
277#define BDEV_SIZE 0x00001000 // 4 Kbytes
278
279// in cluster [X_SIZE-1,Y_SIZE]
280
281#define FBUF_BASE 0xF3000000
282#define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2)
283
284#define MNIC_BASE 0xF7000000
285#define MNIC_SIZE 0x00800000 // 512 Kbytes (for 8 channels)
286
287#define CDMA_BASE 0xF8000000
288#define CDMA_SIZE 0x00004000 * NB_CMA_CHANNELS
289
290#define IOPI_BASE 0xF9000000
291#define IOPI_SIZE 0x00001000 // 4 Kbytes
292
293// replicated segments : address is extended to 40 bits by cluster_xy
294
295#define MEMC_BASE 0x00000000
296#define MEMC_SIZE XRAM_SIZE
297
298#define MCFG_BASE 0xE0000000
299#define MCFG_SIZE 0x00001000 // 4 Kbytes
300
301#define XICU_BASE 0xF0000000
302#define XICU_SIZE 0x00001000 // 4 Kbytes
303
304bool stop_called = false;
305
306/////////////////////////////////
307int _main(int argc, char *argv[])
308{
309 using namespace sc_core;
310 using namespace soclib::caba;
311 using namespace soclib::common;
312
313 uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
314 size_t threads = 1; // simulator's threads number
315 bool trace_ok = false; // trace activated
316 uint32_t trace_from = 0; // trace start cycle
317 bool trace_proc_ok = false; // detailed proc trace activated
318 size_t trace_memc_ok = false; // detailed memc trace activated
319 size_t trace_memc_id = 0; // index of memc to be traced
320 size_t trace_proc_id = 0; // index of proc to be traced
321 uint32_t frozen_cycles = MAX_FROZEN_CYCLES;
322 char soft_name[256] = BINARY_PATH_FOR_LOADER;
323 char disk_name[256] = DISK_IMAGE_PATH_FOR_IOC;
324 char ramdisk_name[256] = RAMDISK_PATH_FOR_LOADER;
325 struct timeval t1,t2;
326 uint64_t ms1,ms2;
327
328 ////////////// command line arguments //////////////////////
329 if (argc > 1)
330 {
331 for (int n = 1; n < argc; n = n + 2)
332 {
333 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
334 {
335 ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
336 }
337 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
338 {
339 trace_ok = true;
340 trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
341 }
342 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
343 {
344 trace_memc_ok = true;
345 trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
346 size_t x = trace_memc_id >> Y_WIDTH;
347 size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
348
349 assert( (x < X_SIZE) and (y < (Y_SIZE)) and
350 "MEMCID parameter refers a not valid memory cache");
351 }
352 else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
353 {
354 trace_proc_ok = true;
355 trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
356 size_t cluster_xy = trace_proc_id / NB_PROCS_MAX ;
357 size_t x = cluster_xy >> Y_WIDTH;
358 size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
359 size_t l = trace_proc_id % NB_PROCS_MAX ;
360
361 assert( (x < X_SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and
362 "PROCID parameter refers a not valid processor");
363 }
364 else if ((strcmp(argv[n], "-SOFT") == 0) && ((n + 1) < argc))
365 {
366 strcpy(soft_name, argv[n + 1]);
367 }
368 else if ((strcmp(argv[n], "-DISK") == 0) && ((n + 1) < argc))
369 {
370 strcpy(disk_name, argv[n + 1]);
371 }
372 else if ((strcmp(argv[n], "-RAMDISK") == 0) && ((n + 1) < argc))
373 {
374 strcpy(ramdisk_name, argv[n + 1]);
375 }
376 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
377 {
378 threads = (size_t) strtol(argv[n + 1], NULL, 0);
379 threads = (threads < 1) ? 1 : threads;
380 }
381 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
382 {
383 frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
384 }
385 else
386 {
387 std::cout << " Arguments are (key,value) couples." << std::endl;
388 std::cout << " The order is not important." << std::endl;
389 std::cout << " Accepted arguments are :" << std::endl << std::endl;
390 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
391 std::cout << " -DEBUG debug_start_cycle" << std::endl;
392 std::cout << " -SOFT path to soft" << std::endl;
393 std::cout << " -DISK path to disk image" << std::endl;
394 std::cout << " -RAMDISK path to ramdisk image" << std::endl;
395 std::cout << " -THREADS simulator's threads number" << std::endl;
396 std::cout << " -FROZEN max_number_of_lines" << std::endl;
397 std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
398 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
399 std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
400 exit(0);
401 }
402 }
403 }
404
405 // checking hardware parameters
406 assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or (X_SIZE==16)) and
407 "Illegal X_SIZE parameter" );
408
409 assert( ((Y_SIZE==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and
410 "Illegal Y_SIZE parameter" );
411
412 assert( (NB_PROCS_MAX <= 4) and
413 "Illegal NB_PROCS_MAX parameter" );
414
415 assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and
416 "The NB_CMA_CHANNELS parameter cannot be larger than 4" );
417
418 assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and
419 "The NB_TTY_CHANNELS parameter cannot be larger than 8" );
420
421 assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and
422 "The NB_NIC_CHANNELS parameter cannot be larger than 2" );
423
424 assert( (vci_address_width == 40) and
425 "VCI address width with the GIET must be 40 bits" );
426
427 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
428 "ERROR: you must have X_WIDTH == Y_WIDTH == 4");
429
430 std::cout << std::endl;
431
432 std::cout << " - X_SIZE = " << X_SIZE << std::endl;
433 std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
434 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
435 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
436 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
437 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
438 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
439 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
440 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
441 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
442 std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
443 std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
444 std::cout << " - SOFT_FILENAME = " << soft_name << std::endl;
445 std::cout << " - DISK_IMAGENAME = " << disk_name << std::endl;
446 std::cout << " - RAMDISK_FILENAME = " << ramdisk_name << std::endl;
447 std::cout << " - OPENMP THREADS = " << threads << std::endl;
448
449 std::cout << std::endl;
450
451 // Internal and External VCI parameters definition
452 typedef soclib::caba::VciParams<vci_cell_width_int,
453 vci_plen_width,
454 vci_address_width,
455 vci_rerror_width,
456 vci_clen_width,
457 vci_rflag_width,
458 vci_srcid_width,
459 vci_pktid_width,
460 vci_trdid_width,
461 vci_wrplen_width> vci_param_int;
462
463 typedef soclib::caba::VciParams<vci_cell_width_ext,
464 vci_plen_width,
465 vci_address_width,
466 vci_rerror_width,
467 vci_clen_width,
468 vci_rflag_width,
469 vci_srcid_width,
470 vci_pktid_width,
471 vci_trdid_width,
472 vci_wrplen_width> vci_param_ext;
473
474#if USE_OPENMP
475 omp_set_dynamic(false);
476 omp_set_num_threads(threads);
477 std::cerr << "Built with openmp version " << _OPENMP << std::endl;
478#endif
479
480
481 ///////////////////////////////////////
482 // Direct Network Mapping Table
483 ///////////////////////////////////////
484
485 MappingTable maptabd(vci_address_width,
486 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
487 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
488 0x00FF000000ULL);
489
490 // replicated segments
491 for (size_t x = 0; x < X_SIZE; x++)
492 {
493 for (size_t y = 0; y < (Y_SIZE) ; y++)
494 {
495 sc_uint<vci_address_width> offset;
496 offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
497
498 std::ostringstream si;
499 si << "seg_xicu_" << x << "_" << y;
500 maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE,
501 IntTab(cluster(x,y),XICU_TGTID), false));
502
503 std::ostringstream sd;
504 sd << "seg_mcfg_" << x << "_" << y;
505 maptabd.add(Segment(sd.str(), MCFG_BASE + offset, MCFG_SIZE,
506 IntTab(cluster(x,y),MEMC_TGTID), false));
507
508 std::ostringstream sh;
509 sh << "seg_memc_" << x << "_" << y;
510 maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE,
511 IntTab(cluster(x,y),MEMC_TGTID), true));
512 }
513 }
514
515 // segments for peripherals in cluster(0,0)
516 maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE,
517 IntTab(cluster(0,0),MTTY_TGTID), false));
518
519 maptabd.add(Segment("seg_ioc0", BDEV_BASE, BDEV_SIZE,
520 IntTab(cluster(0,0),BDEV_TGTID), false));
521
522 // segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE)
523 sc_uint<vci_address_width> offset;
524 offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
525
526 maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE,
527 IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
528
529 maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE,
530 IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
531
532 maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE,
533 IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
534
535 maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE,
536 IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
537
538 maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE,
539 IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
540
541 maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE,
542 IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
543
544 std::cout << maptabd << std::endl;
545
546 /////////////////////////////////////////////////
547 // Ram network mapping table
548 /////////////////////////////////////////////////
549
550 MappingTable maptabx(vci_address_width,
551 IntTab(X_WIDTH+Y_WIDTH),
552 IntTab(X_WIDTH+Y_WIDTH),
553 0x00FF000000ULL);
554
555 for (size_t x = 0; x < X_SIZE; x++)
556 {
557 for (size_t y = 0; y < (Y_SIZE) ; y++)
558 {
559 sc_uint<vci_address_width> offset;
560 offset = (sc_uint<vci_address_width>)cluster(x,y)
561 << (vci_address_width-X_WIDTH-Y_WIDTH);
562
563 std::ostringstream sh;
564 sh << "x_seg_memc_" << x << "_" << y;
565
566 maptabx.add(Segment(sh.str(), MEMC_BASE + offset,
567 MEMC_SIZE, IntTab(cluster(x,y)), false));
568 }
569 }
570 std::cout << maptabx << std::endl;
571
572 ////////////////////
573 // Signals
574 ///////////////////
575
576 sc_clock signal_clk("clk");
577 sc_signal<bool> signal_resetn("resetn");
578
579 // IRQs from external peripherals
580 sc_signal<bool> signal_irq_bdev;
581 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
582 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
583 sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
584// sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS];
585 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
586 sc_signal<bool> signal_irq_false;
587
588 // Horizontal inter-clusters DSPIN signals
589 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
590 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
591 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
592 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
593
594 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
595 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
596 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
597 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
598
599 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
600 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
601 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
602 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
603
604 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
605 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
606 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
607 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
608
609 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
610 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
611 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
612 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
613
614 // Vertical inter-clusters DSPIN signals
615 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
616 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
617 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
618 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
619
620 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
621 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
622 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
623 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
624
625 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
626 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
627 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
628 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
629
630 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
631 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
632 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
633 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
634
635 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
636 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
637 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
638 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
639
640 // Mesh boundaries DSPIN signals (Most of those signals are not used...)
641 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
642 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
643 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
644 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
645
646 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
647 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
648 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
649 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
650
651 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
652 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
653 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
654 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
655
656 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
657 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
658 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
659 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
660
661 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
662 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
663 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
664 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
665
666 // VCI signals for iobus and peripherals
667 VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
668 VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
669 VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
670
671 VciSignals<vci_param_int>* signal_vci_ini_proc =
672 alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
673
674 VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
675 VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
676 VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
677 VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
678 VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
679 VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
680 VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
681 VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
682
683 VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
684 VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
685
686 ////////////////////////////
687 // Loader
688 ////////////////////////////
689
690#if USE_IOC_RDK
691 soclib::common::Loader loader( soft_name, ramdisk_name );
692#else
693 soclib::common::Loader loader( soft_name );
694#endif
695 loader.memory_default(0xAA);
696
697 ///////////////////////////
698 // processor iss
699 ///////////////////////////
700
701 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
702 proc_iss::set_loader( loader );
703
704 //////////////////////////////////////////////////////////////
705 // mesh construction: only (X_SIZE) * (Y_SIZE) clusters
706 //////////////////////////////////////////////////////////////
707
708 TsarLetiCluster<dspin_cmd_width,
709 dspin_rsp_width,
710 vci_param_int,
711 vci_param_ext>* clusters[X_SIZE][Y_SIZE];
712
713#if USE_OPENMP
714#pragma omp parallel
715 {
716#pragma omp for
717#endif
718 for (size_t i = 0; i < (X_SIZE * (Y_SIZE)); i++)
719 {
720 size_t x = i / (Y_SIZE);
721 size_t y = i % (Y_SIZE);
722
723#if USE_OPENMP
724#pragma omp critical
725 {
726#endif
727 std::cout << std::endl;
728 std::cout << "Cluster_" << std::dec << x << "_" << y
729 << " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
730 std::cout << std::endl;
731
732 std::ostringstream cluster_name;
733 cluster_name << "cluster_" << std::dec << x << "_" << y;
734
735 clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
736 dspin_rsp_width,
737 vci_param_int,
738 vci_param_ext>
739 (
740 cluster_name.str().c_str(),
741 NB_PROCS_MAX,
742 x,
743 y,
744 cluster(x,y),
745 maptabd,
746 maptabx,
747 RESET_ADDRESS,
748 X_WIDTH,
749 Y_WIDTH,
750 vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
751 MEMC_TGTID,
752 XICU_TGTID,
753 MTTY_TGTID,
754 BDEV_TGTID,
755 disk_name,
756 MEMC_WAYS,
757 MEMC_SETS,
758 L1_IWAYS,
759 L1_ISETS,
760 L1_DWAYS,
761 L1_DSETS,
762 XRAM_LATENCY,
763 loader,
764 frozen_cycles,
765 trace_from,
766 trace_proc_ok,
767 trace_proc_id,
768 trace_memc_ok,
769 trace_memc_id
770 );
771
772#if USE_OPENMP
773 } // end critical
774#endif
775 } // end for
776#if USE_OPENMP
777 }
778#endif
779
780 //////////////////////////////////////////////////////////////////
781 // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
782 // - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
783 // - 3 local initiators : IOC, CMA, PIC
784 // There is no PROC, no MEMC and no XICU in this cluster,
785 // but the crossbar has (NB_PROCS_MAX + 3) intiators and
786 // 8 targets, in order to use the same SRCID and TGTID space
787 // (same mapping table for the internal components,
788 // and for the external peripherals)
789 //////////////////////////////////////////////////////////////////
790
791 std::cout << std::endl;
792 std::cout << " Building IO cluster (external peripherals)" << std::endl;
793 std::cout << std::endl;
794
795 size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
796
797 //////////// vci_local_crossbar
798 VciLocalCrossbar<vci_param_int>*
799 iobus = new VciLocalCrossbar<vci_param_int>(
800 "iobus",
801 maptabd, // mapping table
802 cluster_io, // cluster_xy
803 NB_PROCS_MAX + 3, // number of local initiators
804 8, // number of local targets
805 BDEV_TGTID ); // default target index
806
807 //////////// vci_framebuffer
808 VciFrameBuffer<vci_param_int>*
809 fbuf = new VciFrameBuffer<vci_param_int>(
810 "fbuf",
811 IntTab(cluster_io, FBUF_TGTID),
812 maptabd,
813 FBUF_X_SIZE, FBUF_Y_SIZE );
814
815 //////////// vci_block_device
816 VciBlockDeviceTsar<vci_param_int>*
817 bdev = new VciBlockDeviceTsar<vci_param_int>(
818 "bdev",
819 maptabd,
820 IntTab(cluster_io, BDEV_SRCID),
821 IntTab(cluster_io, BDEV_TGTID),
822 disk_name,
823 512, // block size
824 64 ); // burst size
825
826 //////////// vci_multi_nic
827 VciMultiNic<vci_param_int>*
828 mnic = new VciMultiNic<vci_param_int>(
829 "mnic",
830 IntTab(cluster_io, MNIC_TGTID),
831 maptabd,
832 NB_NIC_CHANNELS,
833 NIC_MAC4,
834 NIC_MAC2,
835 NIC_RX_NAME,
836 NIC_TX_NAME );
837
838 ///////////// vci_chbuf_dma
839 VciChbufDma<vci_param_int>*
840 cdma = new VciChbufDma<vci_param_int>(
841 "cdma",
842 maptabd,
843 IntTab(cluster_io, CDMA_SRCID),
844 IntTab(cluster_io, CDMA_TGTID),
845 64, // burst size
846 NB_CMA_CHANNELS );
847
848 ////////////// vci_multi_tty
849 std::vector<std::string> vect_names;
850 for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
851 {
852 std::ostringstream term_name;
853 term_name << "ext_" << id;
854 vect_names.push_back(term_name.str().c_str());
855 }
856
857 VciMultiTty<vci_param_int>*
858 mtty = new VciMultiTty<vci_param_int>(
859 "mtty",
860 IntTab(cluster_io, MTTY_TGTID),
861 maptabd,
862 vect_names );
863
864 ///////////// vci_iopic
865 VciIopic<vci_param_int>*
866 iopic = new VciIopic<vci_param_int>(
867 "iopic",
868 maptabd,
869 IntTab(cluster_io, IOPI_SRCID),
870 IntTab(cluster_io, IOPI_TGTID),
871 32,
872 5000 );
873
874 ////////////// vci_dspin wrappers
875 VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
876 wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
877 "wt_bdev",
878 vci_srcid_width );
879
880 VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
881 wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
882 "wi_bdev",
883 vci_srcid_width );
884
885 ///////////////////////////////////////////////////////////////
886 // Net-list
887 ///////////////////////////////////////////////////////////////
888
889 // iobus
890 iobus->p_clk (signal_clk);
891 iobus->p_resetn (signal_resetn);
892
893 iobus->p_target_to_up (signal_vci_cmd_from_noc);
894 iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
895
896 iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
897 iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
898 iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
899 iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
900 iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
901 iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
902 iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
903 iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
904
905 for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
906 {
907 iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
908 }
909 iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
910 iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
911 iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
912
913 std::cout << " - IOBUS connected" << std::endl;
914
915 // block_device
916 bdev->p_clk (signal_clk);
917 bdev->p_resetn (signal_resetn);
918 bdev->p_vci_target (signal_vci_tgt_bdev);
919 bdev->p_vci_initiator (signal_vci_ini_bdev);
920 bdev->p_irq (signal_irq_bdev);
921
922 std::cout << " - BDEV connected" << std::endl;
923
924 // frame_buffer
925 fbuf->p_clk (signal_clk);
926 fbuf->p_resetn (signal_resetn);
927 fbuf->p_vci (signal_vci_tgt_fbuf);
928
929 std::cout << " - FBUF connected" << std::endl;
930
931 // multi_nic
932 mnic->p_clk (signal_clk);
933 mnic->p_resetn (signal_resetn);
934 mnic->p_vci (signal_vci_tgt_mnic);
935 for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
936 {
937 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
938 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
939 }
940
941 std::cout << " - MNIC connected" << std::endl;
942
943 // chbuf_dma
944 cdma->p_clk (signal_clk);
945 cdma->p_resetn (signal_resetn);
946 cdma->p_vci_target (signal_vci_tgt_cdma);
947 cdma->p_vci_initiator (signal_vci_ini_cdma);
948 for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
949 {
950 cdma->p_irq[i] (signal_irq_cdma[i]);
951 }
952
953 std::cout << " - CDMA connected" << std::endl;
954
955 // multi_tty
956 mtty->p_clk (signal_clk);
957 mtty->p_resetn (signal_resetn);
958 mtty->p_vci (signal_vci_tgt_mtty);
959 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
960 {
961 mtty->p_irq[i] (signal_irq_mtty_rx[i]);
962 }
963
964 std::cout << " - MTTY connected" << std::endl;
965
966 // iopic
967 // NB_NIC_CHANNELS <= 2
968 // NB_CMA_CHANNELS <= 4
969 // NB_TTY_CHANNELS <= 8
970 iopic->p_clk (signal_clk);
971 iopic->p_resetn (signal_resetn);
972 iopic->p_vci_target (signal_vci_tgt_iopi);
973 iopic->p_vci_initiator (signal_vci_ini_iopi);
974 for ( size_t i=0 ; i<32 ; i++)
975 {
976 if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
977 else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
978 else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
979 else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
980 else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
981 else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
982 else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev);
983 else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
984 else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
985 else if(i < 24) iopic->p_hwi[i] (signal_irq_false);
986 else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);
987// else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);
988 else iopic->p_hwi[i] (signal_irq_false);
989 }
990
991 std::cout << " - IOPIC connected" << std::endl;
992
993 // vci/dspin wrappers
994 wi_iobus->p_clk (signal_clk);
995 wi_iobus->p_resetn (signal_resetn);
996 wi_iobus->p_vci (signal_vci_cmd_to_noc);
997 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
998 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
999
1000 // vci/dspin wrappers
1001 wt_iobus->p_clk (signal_clk);
1002 wt_iobus->p_resetn (signal_resetn);
1003 wt_iobus->p_vci (signal_vci_cmd_from_noc);
1004 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
1005 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
1006
1007 // Clock & RESET for clusters
1008 for (size_t x = 0; x < (X_SIZE); x++)
1009 {
1010 for (size_t y = 0; y < (Y_SIZE); y++)
1011 {
1012 clusters[x][y]->p_clk (signal_clk);
1013 clusters[x][y]->p_resetn (signal_resetn);
1014 }
1015 }
1016
1017 // Inter Clusters horizontal connections
1018 if (X_SIZE > 1)
1019 {
1020 for (size_t x = 0; x < (X_SIZE-1); x++)
1021 {
1022 for (size_t y = 0; y < (Y_SIZE); y++)
1023 {
1024 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
1025 clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
1026 clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
1027 clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
1028
1029 clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
1030 clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
1031 clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
1032 clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
1033
1034 clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
1035 clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
1036 clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
1037 clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
1038
1039 clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
1040 clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
1041 clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
1042 clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
1043
1044 clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
1045 clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
1046 clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
1047 clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
1048 }
1049 }
1050 }
1051 std::cout << std::endl << "Horizontal connections done" << std::endl;
1052
1053 // Inter Clusters vertical connections
1054 if (Y_SIZE > 1)
1055 {
1056 for (size_t y = 0; y < (Y_SIZE-1); y++)
1057 {
1058 for (size_t x = 0; x < X_SIZE; x++)
1059 {
1060 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
1061 clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
1062 clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
1063 clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
1064
1065 clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
1066 clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
1067 clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
1068 clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
1069
1070 clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
1071 clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
1072 clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
1073 clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
1074
1075 clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
1076 clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
1077 clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
1078 clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
1079
1080 clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
1081 clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
1082 clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
1083 clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
1084 }
1085 }
1086 }
1087 std::cout << std::endl << "Vertical connections done" << std::endl;
1088
1089 // East & West boundary cluster connections
1090 for (size_t y = 0; y < (Y_SIZE); y++)
1091 {
1092 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
1093 clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
1094 clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
1095 clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
1096
1097 clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
1098 clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
1099 clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
1100 clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
1101
1102 clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
1103 clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
1104 clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
1105 clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
1106
1107 clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
1108 clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
1109 clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
1110 clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
1111
1112 clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
1113 clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
1114 clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
1115 clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
1116 }
1117
1118 std::cout << std::endl << "West & East boundaries connections done" << std::endl;
1119
1120 // North & South boundary clusters connections
1121 for (size_t x = 0; x < X_SIZE; x++)
1122 {
1123 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
1124 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
1125 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
1126 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
1127
1128 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
1129 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
1130 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
1131 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
1132
1133 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
1134 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
1135 clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
1136 clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
1137
1138 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
1139 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
1140 clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
1141 clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
1142
1143 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
1144 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
1145 clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
1146 clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
1147 }
1148
1149 std::cout << std::endl << "North & South boundaries connections done" << std::endl;
1150
1151 std::cout << std::endl;
1152
1153 ////////////////////////////////////////////////////////
1154 // Simulation
1155 ///////////////////////////////////////////////////////
1156
1157 sc_start(sc_core::sc_time(0, SC_NS));
1158 signal_resetn = false;
1159 signal_irq_false = false;
1160
1161 // set network boundaries signals default values
1162 // for all boundary clusters but the IO cluster
1163 for (size_t x = 0; x < X_SIZE ; x++)
1164 {
1165 for (size_t y = 0; y < Y_SIZE ; y++)
1166 {
1167 for (size_t face = 0; face < 4; face++)
1168 {
1169 if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
1170 {
1171 signal_dspin_bound_cmd_in [x][y][face].write = false;
1172 signal_dspin_bound_cmd_in [x][y][face].read = true;
1173 signal_dspin_bound_cmd_out[x][y][face].write = false;
1174 signal_dspin_bound_cmd_out[x][y][face].read = true;
1175
1176 signal_dspin_bound_rsp_in [x][y][face].write = false;
1177 signal_dspin_bound_rsp_in [x][y][face].read = true;
1178 signal_dspin_bound_rsp_out[x][y][face].write = false;
1179 signal_dspin_bound_rsp_out[x][y][face].read = true;
1180 }
1181
1182 signal_dspin_bound_m2p_in [x][y][face].write = false;
1183 signal_dspin_bound_m2p_in [x][y][face].read = true;
1184 signal_dspin_bound_m2p_out[x][y][face].write = false;
1185 signal_dspin_bound_m2p_out[x][y][face].read = true;
1186
1187 signal_dspin_bound_p2m_in [x][y][face].write = false;
1188 signal_dspin_bound_p2m_in [x][y][face].read = true;
1189 signal_dspin_bound_p2m_out[x][y][face].write = false;
1190 signal_dspin_bound_p2m_out[x][y][face].read = true;
1191
1192 signal_dspin_bound_cla_in [x][y][face].write = false;
1193 signal_dspin_bound_cla_in [x][y][face].read = true;
1194 signal_dspin_bound_cla_out[x][y][face].write = false;
1195 signal_dspin_bound_cla_out[x][y][face].read = true;
1196 }
1197 }
1198 }
1199
1200 // set default values for VCI signals connected to unused ports on iobus
1201 signal_vci_tgt_memc.rspval = false;
1202 signal_vci_tgt_xicu.rspval = false;
1203 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
1204
1205 sc_start(sc_core::sc_time(1, SC_NS));
1206 signal_resetn = true;
1207
1208 if (gettimeofday(&t1, NULL) != 0)
1209 {
1210 perror("gettimeofday");
1211 return EXIT_FAILURE;
1212 }
1213
1214 // variable used for IRQ trace
1215 bool prev_irq_bdev = false;
1216 bool prev_irq_mtty_rx[8];
1217 bool prev_irq_proc[16][16][4];
1218
1219 for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false;
1220
1221 for( size_t x = 0 ; x<16 ; x++ )
1222 for( size_t y = 0 ; y<16 ; y++ )
1223 for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false;
1224
1225 for (uint64_t n = 1; n < ncycles && !stop_called; n++)
1226 {
1227 // Monitor a specific address for L1 & L2 caches
1228 // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
1229 // clusters[1][1]->memc->cache_monitor(0x110002c078ULL);
1230
1231 // stats display
1232 if( (n % 5000000) == 0)
1233 {
1234
1235 if (gettimeofday(&t2, NULL) != 0)
1236 {
1237 perror("gettimeofday");
1238 return EXIT_FAILURE;
1239 }
1240
1241 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
1242 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
1243 std::cerr << "platform clock frequency "
1244 << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
1245
1246 if (gettimeofday(&t1, NULL) != 0)
1247 {
1248 perror("gettimeofday");
1249 return EXIT_FAILURE;
1250 }
1251 }
1252
1253 // trace display
1254 if ( trace_ok and (n > trace_from) )
1255 {
1256 std::cout << "****************** cycle " << std::dec << n ;
1257 std::cout << " ************************************************" << std::endl;
1258
1259 size_t l = 0;
1260 size_t x = 0;
1261 size_t y = 0;
1262
1263 if ( trace_proc_ok )
1264 {
1265 l = trace_proc_id % NB_PROCS_MAX ;
1266 x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ;
1267 y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1);
1268
1269 std::ostringstream proc_signame;
1270 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
1271 clusters[x][y]->proc[l]->print_trace(1);
1272 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
1273
1274 std::ostringstream xicu_signame;
1275 xicu_signame << "[SIG]XICU_" << x << "_" << y ;
1276 clusters[x][y]->xicu->print_trace(0);
1277 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
1278 }
1279
1280 if ( trace_memc_ok )
1281 {
1282 x = trace_memc_id >> Y_WIDTH;
1283 y = trace_memc_id & ((1<<Y_WIDTH) - 1);
1284
1285 std::ostringstream smemc;
1286 smemc << "[SIG]MEMC_" << x << "_" << y;
1287 std::ostringstream sxram;
1288 sxram << "[SIG]XRAM_" << x << "_" << y;
1289
1290 clusters[x][y]->memc->print_trace();
1291 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
1292 clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
1293 }
1294
1295 // trace coherence signals
1296 // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
1297 // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
1298 // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
1299 // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
1300
1301 // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
1302 // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
1303 // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
1304 // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
1305
1306 // trace xbar(s) m2p
1307 // clusters[0][0]->xbar_m2p->print_trace();
1308 // clusters[1][0]->xbar_m2p->print_trace();
1309 // clusters[0][1]->xbar_m2p->print_trace();
1310 // clusters[1][1]->xbar_m2p->print_trace();
1311
1312 // trace router(s) m2p
1313 // clusters[0][0]->router_m2p->print_trace();
1314 // clusters[1][0]->router_m2p->print_trace();
1315 // clusters[0][1]->router_m2p->print_trace();
1316 // clusters[1][1]->router_m2p->print_trace();
1317
1318 // trace external ioc
1319 bdev->print_trace();
1320 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
1321 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
1322
1323 // trace external iopic
1324 iopic->print_trace();
1325 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
1326 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
1327
1328 // trace internal tty
1329 // clusters[0][0]->mtty->print_trace();
1330 // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
1331
1332 } // end trace
1333
1334 if (0)
1335 {
1336 // trace BDV interrupts events
1337 if ( signal_irq_bdev.read() != prev_irq_bdev )
1338 {
1339 prev_irq_bdev = signal_irq_bdev.read();
1340 std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()
1341 << " at cycle " << n << std::endl;
1342 }
1343
1344 // trace TTY interrupts events
1345 for ( size_t x = 0 ; x < 8 ; x++ )
1346 {
1347 if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )
1348 {
1349 prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();
1350 std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "
1351 << signal_irq_mtty_rx[x].read()
1352 << " at cycle " << n << std::endl;
1353 }
1354 }
1355
1356 // trace processor interrupts events
1357 for ( size_t x = 0 ; x < X_SIZE ; x++ )
1358 for ( size_t y = 0 ; y < Y_SIZE ; y++ )
1359 for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )
1360 {
1361 if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )
1362 {
1363 prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];
1364 std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "
1365 << clusters[x][y]->signal_proc_irq[i]
1366 << " at cycle " << n << std::endl;
1367 }
1368 }
1369
1370 // trace VCI transactions on IOPIC and XCU(0,0)
1371 signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");
1372 signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");
1373 clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");
1374 }
1375
1376 sc_start(sc_core::sc_time(1, SC_NS));
1377 }
1378 // Free memory
1379 for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++)
1380 {
1381 size_t x = i / (Y_SIZE);
1382 size_t y = i % (Y_SIZE);
1383 delete clusters[x][y];
1384 }
1385
1386 return EXIT_SUCCESS;
1387}
1388
1389
1390void handler(int dummy = 0)
1391{
1392 stop_called = true;
1393 sc_stop();
1394}
1395
1396void voidhandler(int dummy = 0) {}
1397
1398int sc_main (int argc, char *argv[])
1399{
1400 signal(SIGINT, handler);
1401 signal(SIGPIPE, voidhandler);
1402
1403 try {
1404 return _main(argc, argv);
1405 } catch (std::exception &e) {
1406 std::cout << e.what() << std::endl;
1407 } catch (...) {
1408 std::cout << "Unknown exception occured" << std::endl;
1409 throw;
1410 }
1411 return 1;
1412}
1413
1414
1415// Local Variables:
1416// tab-width: 3
1417// c-basic-offset: 3
1418// c-file-offsets:((innamespace . 0)(inline-open . 0))
1419// indent-tabs-mode: nil
1420// End:
1421
1422// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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